[all-commits] [llvm/llvm-project] 3b2d22: [𝘀𝗽𝗿] initial version

Pengcheng Wang via All-commits all-commits at lists.llvm.org
Tue Nov 12 01:54:57 PST 2024 

  Branch: refs/heads/users/wangpc-pp/spr/riscv-enable-shouldtracklanemasks-when-having-vector-instructions
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b2d22d49f5181b1eddde933f2d772e75cca8790
      https://github.com/llvm/llvm-project/commit/3b2d22d49f5181b1eddde933f2d772e75cca8790
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-12 (Tue, 12 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/abds-neg.ll
    M llvm/test/CodeGen/RISCV/abds.ll
    M llvm/test/CodeGen/RISCV/abdu-neg.ll
    M llvm/test/CodeGen/RISCV/abdu.ll
    M llvm/test/CodeGen/RISCV/add-before-shl.ll
    M llvm/test/CodeGen/RISCV/add-imm.ll
    M llvm/test/CodeGen/RISCV/addcarry.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/alu16.ll
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/and.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/avgceils.ll
    M llvm/test/CodeGen/RISCV/avgceilu.ll
    M llvm/test/CodeGen/RISCV/avgfloors.ll
    M llvm/test/CodeGen/RISCV/avgflooru.ll
    M llvm/test/CodeGen/RISCV/bf16-promote.ll
    M llvm/test/CodeGen/RISCV/bfloat-arith.ll
    M llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/bfloat-fcmp.ll
    M llvm/test/CodeGen/RISCV/bfloat-mem.ll
    M llvm/test/CodeGen/RISCV/bfloat.ll
    M llvm/test/CodeGen/RISCV/bitextract-mac.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
    M llvm/test/CodeGen/RISCV/compress.ll
    M llvm/test/CodeGen/RISCV/condbinops.ll
    M llvm/test/CodeGen/RISCV/condops.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div-pow2.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/double-calling-conv.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-imm.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/double-previous-failure.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
    M llvm/test/CodeGen/RISCV/double_reduct.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/float-arith.ll
    M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-intrinsics.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/fold-binop-into-select.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpenv.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
    M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
    M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/global-merge.ll
    M llvm/test/CodeGen/RISCV/half-arith-strict.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/half-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/llvm.exp10.ll
    M llvm/test/CodeGen/RISCV/llvm.frexp.ll
    M llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
    M llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
    M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
    M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/or-is-add.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr51206.ll
    M llvm/test/CodeGen/RISCV/pr56457.ll
    M llvm/test/CodeGen/RISCV/pr58511.ll
    M llvm/test/CodeGen/RISCV/pr65025.ll
    M llvm/test/CodeGen/RISCV/pr68855.ll
    M llvm/test/CodeGen/RISCV/pr69586.ll
    M llvm/test/CodeGen/RISCV/pr84653_pr85190.ll
    M llvm/test/CodeGen/RISCV/pr95271.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rem.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
    M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
    M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
    M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
    M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
    M llvm/test/CodeGen/RISCV/rvv/expandload.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
    M llvm/test/CodeGen/RISCV/rvv/pr52475.ll
    M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
    M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
    M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfirst-byte-compare-index.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
    M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/select-const.ll
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
    M llvm/test/CodeGen/RISCV/shift-and.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/shl-cttz.ll
    M llvm/test/CodeGen/RISCV/shlimm-addimm.ll
    M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
    M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll
    M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
    M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/tail-calls.ll
    M llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
    M llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/xtheadmac.ll
    M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
    M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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