[all-commits] [llvm/llvm-project] d1e17a: [RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1e17a3f23a30815030b784d813141a469b3d7fb
      https://github.com/llvm/llvm-project/commit/d1e17a3f23a30815030b784d813141a469b3d7fb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-11 (Mon, 11 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/shift.ll

  Log Message:
  -----------
  [RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)

Unless the shift amount is constant. In that case we zero extend the
shift amount and promote the other input the same way widenScalar would.
I'm not using widenScalar because that requires a separate call for each
operand so it was easier to do both operands at once.



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