[all-commits] [llvm/llvm-project] 37b4df: [Clang] Remove the wrong assumption when rebuildin...
wanglei via All-commits
all-commits at lists.llvm.org
Sun Nov 10 22:15:25 PST 2024
Branch: refs/heads/users/wangleiat/spr/loongarch-avoid-indirect-branch-jumps-using-the-ra-register
Home: https://github.com/llvm/llvm-project
Commit: 37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
https://github.com/llvm/llvm-project/commit/37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
[Clang] Remove the wrong assumption when rebuilding SizeOfPackExprs for constraint normalization (#115120)
In 463a4f150, we assumed that all the template argument packs are of
size 1 when normalizing a constraint expression because I mistakenly
thought those packs were obtained from their injected template
parameters. This was wrong because we might be checking constraints when
instantiating a friend declaration within a class template
specialization, where the parent class template is specialized with
non-dependent template arguments.
In that sense, we shouldn't assume any pack size nor expand anything in
such a scenario. Moreover, there are no intermediate (substituted but
unexpanded) AST nodes for template template parameters, so we have to
special-case their transformations by looking into the instantiation
scope instead of extracting anything from template arguments.
Fixes #115098
Commit: c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
https://github.com/llvm/llvm-project/commit/c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
Log Message:
-----------
[Coroutines] Inline the `.noalloc` ramp function marked coro_safe_elide (#114004)
Commit: d233fedfb0de882353c348cd1ac57dab619efa6d
https://github.com/llvm/llvm-project/commit/d233fedfb0de882353c348cd1ac57dab619efa6d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
Log Message:
-----------
[Coroutines] Respect noinline attributes when eliding heap allocation (#115384)
Commit: 9061e6e58a78046963f0eb5991e98346e01a0bf7
https://github.com/llvm/llvm-project/commit/9061e6e58a78046963f0eb5991e98346e01a0bf7
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
Log Message:
-----------
[GlobalISel][AArch64] Legalize G_EXTRACT_VECTOR_ELT for SVE (#115161)
AArch64InstrGISel.td defines:
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
There are many patterns for SVE. Let's exploit that fact.
Commit: c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
https://github.com/llvm/llvm-project/commit/c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
Author: T-Tie <t_tttie at 163.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)
Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
Commit: 1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
https://github.com/llvm/llvm-project/commit/1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
Author: Sebastian Kreutzer <SebastianKreutzer at gmx.net>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M clang/test/Driver/XRay/xray-shared.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
Log Message:
-----------
Reapply "[XRay][AArch64] Support -fxray-shared (#114431)" (#115300)
This patch implements support for `-fxray-shared` on AArch64 and fixes a
remaining issue in the previous PR #114431.
A bug in the XRay `CMakeLists.txt` caused the XRay assembly sources to
be built for every architecture in `XRAY_DSO_SUPPORTED_ARCH` on Apple.
This led to the compiler trying to compile AArch64 assembly for X86
targets and vice versa.
This is addressed here by ensuring that assembly sources are only built
for the matching architecture (see fixup commit).
**Original PR description:**
This patch adds support for `-fxray-shared` on AArch64. This feature,
introduced in #113548 for x86_64, enables the instrumentation of shared
libraries with XRay.
Changes:
- Adds AArch64 to the list of targets supporting `-fxray-shared`
- Introduces PIC versions of the AArch64 XRay trampolines
- Adjusts relevant XRay tests
Commit: a25d91a164b0a283dd809cf9b4d9442d24173fb7
https://github.com/llvm/llvm-project/commit/a25d91a164b0a283dd809cf9b4d9442d24173fb7
Author: Gergely Futo <gergely.futo at hightec-rt.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
Log Message:
-----------
[RISCV] Skip DAG combine for bitcast fabs/fneg (#115325)
Disable the DAG combine for bitcast fabs/fneg in case of the zdinx
extension.
The combine folds the fabs/fneg nodes in some cases. This might result
in suboptimal code if compiled with the zdinx extension. In case of the
zdinx extension, there is no need to load the double value from an x
register to an f register, so the combine can be skipped.
Commit: 984bca9d1faaa1fa5c694f8f2a5524b2374d204a
https://github.com/llvm/llvm-project/commit/984bca9d1faaa1fa5c694f8f2a5524b2374d204a
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
Log Message:
-----------
[GVN][NewGVN] Take call attributes into account in expressions (#114545)
Drop `canBeReplacedBy` and take call attributes into account in
expressions.
Address comment
https://github.com/llvm/llvm-project/pull/114011#pullrequestreview-2409772313.
Commit: f02b1cc99e12ac0147d5c334f130a305d85e477a
https://github.com/llvm/llvm-project/commit/f02b1cc99e12ac0147d5c334f130a305d85e477a
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
Log Message:
-----------
[ASTWriter] Detect more non-affecting FileIDs to reduce source location duplication (#112015)
Currently, any FileID that references a module map file that was
required for a compilation is considered as affecting. This misses an
important opportunity to reduce the source location space taken by the
resulting PCM.
In particular, consider the situation where the same module map file is
passed multiple times in the dependency chain:
```shell
$ clang -fmodule-map-file=foo.modulemap ... -o mod1.pcm
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod1.pcm ... -o mod2.pcm
...
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod$((N-1)).pcm ... -o mod$N.pcm
```
Because `foo.modulemap` is read before reading any of the `.pcm` files,
we have to create a unique `FileID` for it when creating each module.
However, when reading the `.pcm` files, we will reuse the `FileID`
loaded from it for the same module map file and the `FileID` we created
can never be used again, but we will still mark it as affecting and it
will take the source location space in the output PCM.
For a chain of N dependencies, this results in the file taking `N *
(size of file)` source location space, which could be significant. For
examples, we observer internally that some targets that run out of 2GB
of source location space end up wasting up to 20% of that space in
module maps as described above.
I take extra care to still write the InputFile entries for those files that occupied
source location space before. It is required for correctness of clang-scan-deps.
Commit: d6d73ec89e493c69cf24dc3a710d861e2ce08acb
https://github.com/llvm/llvm-project/commit/d6d73ec89e493c69cf24dc3a710d861e2ce08acb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable vector.flat_transpose for scalable vectors (#115338)
Disables `vector.flat_transpose` for scalable vectors. As per the docs:
> This is the counterpart of llvm.matrix.transpose in MLIR
I'm not aware of any use of any matrix-multiply intrinsics in the
context of scalable vectors, hence disabling.
Note, this is a follow-on for #102573 in which I disabled
`vector.matrix_multiply`.
Commit: ff07df6620c32571c7e13ff96ec7976c63ed0ab8
https://github.com/llvm/llvm-project/commit/ff07df6620c32571c7e13ff96ec7976c63ed0ab8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
Log Message:
-----------
[InstCombine] Drop nsw in negation of select (#112893)
Closes https://github.com/llvm/llvm-project/issues/112666 and
https://github.com/llvm/llvm-project/issues/114181.
Commit: b9dd60228cbb2a173380a450f0f71ca43e917783
https://github.com/llvm/llvm-project/commit/b9dd60228cbb2a173380a450f0f71ca43e917783
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/sve-hadd.ll
Log Message:
-----------
[DAGCombiner] Remove a hasOneUse check in visitAND (#115142)
For some reason there was a hasOneUse check on the splat for the
second operand and it's not obvious to me why. The check blocks
optimisations for lowering of nodes like AVGFLOORU and AVGCEILU.
In a follow-on patch I also plan to improve the generated code
for AVGCEILU further by teaching computeKnownBits about
zero-extending masked loads.
Commit: 58a17e1bbc54357385d0b89cfc5635e402c31ef6
https://github.com/llvm/llvm-project/commit/58a17e1bbc54357385d0b89cfc5635e402c31ef6
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-AVX512 (#114070)
Commit: 4f3bf1c62ceb85d2e33857ada26b565822e65600
https://github.com/llvm/llvm-project/commit/4f3bf1c62ceb85d2e33857ada26b565822e65600
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 58a17e1bbc54
Commit: d74127e78aa7f8ab07b0926d25920444dde6c73c
https://github.com/llvm/llvm-project/commit/d74127e78aa7f8ab07b0926d25920444dde6c73c
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[flang][OpenMP][MLIR] Add MLIR op for loop directive (#113911)
Adds MLIR op that corresponds to the `loop` directive.
Commit: 546066e4f74d50c974248b0ed247f65ebf24b75c
https://github.com/llvm/llvm-project/commit/546066e4f74d50c974248b0ed247f65ebf24b75c
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/DIBuilder.cpp
Log Message:
-----------
Fix DIBuilder::createVariantPart after f6617d65e496
which ended up passing 0 for the Discriminator arg, Discriminator for
the DataLocation arg, etc.
The DICompositeType::get's new NumExtraInhabitants parameter is at the
end, and has a default value, so no change in the caller is necessary.
See comment on https://github.com/llvm/llvm-project/pull/112590
Commit: ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
https://github.com/llvm/llvm-project/commit/ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/PDB.cpp
A lld/test/COFF/arm64ec-pdb.test
Log Message:
-----------
[LLD][COFF] Use correct machine types in PDB records on ARM64EC (#115309)
Commit: 799e520c51f47c54769e5bd8ce6ce2d2d3931445
https://github.com/llvm/llvm-project/commit/799e520c51f47c54769e5bd8ce6ce2d2d3931445
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/attr-target-clones-aarch64.c
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/lib/Target/AArch64/AArch64FMV.td
Log Message:
-----------
[FMV] Remove feature dgh. (#115363)
It belongs to the HINT space so it can be executed as NOP if the
hardware doesn't support it.
Reviewed in ACLE -> https://github.com/ARM-software/acle/pull/357
Commit: 4bcd4d843f660c1a435159a2964f0c4cf4564ab1
https://github.com/llvm/llvm-project/commit/4bcd4d843f660c1a435159a2964f0c4cf4564ab1
Author: Weaver <Tom.Weaver at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
Log Message:
-----------
Revert "clang/AMDGPU: Restore O3 checks in default-attributes.hip (#115238)"
This reverts commit 889d67785905ea85cdb17b2bf2b4b6f010b641f5.
Caused the following build bot failures, author has failed to address:
https://lab.llvm.org/buildbot/#/builders/144/builds/11132
https://lab.llvm.org/buildbot/#/builders/46/builds/7541
https://lab.llvm.org/buildbot/#/builders/190/builds/9077
Please fix before recommitting.
Commit: 2c49301d91d743c4424997c5f670a453439b4b86
https://github.com/llvm/llvm-project/commit/2c49301d91d743c4424997c5f670a453439b4b86
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
Log Message:
-----------
[IR] Remove variadic overload of StructType::setBody. NFC. (#114421)
This is unused in-tree.
Commit: 31af00fda73df8e85e30c71f66e096d486ec8c8b
https://github.com/llvm/llvm-project/commit/31af00fda73df8e85e30c71f66e096d486ec8c8b
Author: amilendra <amilendra.kodithuwakku at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/test/MC/AArch64/spe.s
Log Message:
-----------
[AArch64][v8.7-A] Fix inconsistency in SPE_EEF feature (#115296)
The `SPE-EEF` system-register only feature introduced in Armv8.7-a adds
support for an extra system register (`PMSNEVFR_EL1`) to the Statistical
Profiling extension.
However, `SPE-EEF` is gated even for Armv8.7-a and the `spe-eef`
subtarget-feature is needed to enable it.
This behavior is inconsistent with the implementation for other
system-register only features as they can be used ungated under
supported architectures.
(e.g. HCX : Enable Armv8.7-A `HCRX_EL2` system register).
GCC/Binutils too do not add command line flags for features that only
enable system registers.
Fix by enabling `SPE-EEF` unconditionally under v8.7-A and above.
Commit: 0a7e5e34569737447e9e3e08b5f87883300061e5
https://github.com/llvm/llvm-project/commit/0a7e5e34569737447e9e3e08b5f87883300061e5
Author: Alona Enraght-Moony <code at alona.page>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/docs/UserDocumentation.rst
Log Message:
-----------
[libc++][docs] Document _LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION (#115405)
This was added in 681cde7dd8b5613dbafc9ca54e0288477f946be3, but isn't
currently documented.
Commit: df3f18b071d853896318d2d37186fc6289ffdb2b
https://github.com/llvm/llvm-project/commit/df3f18b071d853896318d2d37186fc6289ffdb2b
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of Windows host (#115337)
Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of
Windows host.
Commit: 39bce77bd6cdb334810ed95249683484e44c1165
https://github.com/llvm/llvm-project/commit/39bce77bd6cdb334810ed95249683484e44c1165
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: XFAIL on Darwin for older compiler verions
Follow-up to https://github.com/llvm/llvm-project/pull/111859. Prior
to this PR we would never run these tests with DWARFv5 on older Clang
versions (since default wasn't DWARFv5 on macOS until recently). The
patch explicitly started running some of these tests with DWARFv5.
These were failing on the macOS matrix bot (with Clang-15/Clang-17).
```
======================================================================
FAIL: test_inline_static_members_dwarf5_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 150, in test_inline_static_members_dwarf5
self.check_inline_static_members("-gdwarf-5")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
```
Commit: 34bf9dd6d39cb2bf75731cea7a26c3563720cb67
https://github.com/llvm/llvm-project/commit/34bf9dd6d39cb2bf75731cea7a26c3563720cb67
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: fix XFAIL decorators
The `compiler` parameter is not supported in the `expectedFailureDarwin`
decorator.
Change the decorator to `expectedFailureAll`, which is fine because
this only affects the `dsym` variant (which is only a macOS variant).
Commit: 3797daa5448f3471c0d7d1c67838922a83a06fa1
https://github.com/llvm/llvm-project/commit/3797daa5448f3471c0d7d1c67838922a83a06fa1
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
Log Message:
-----------
[AArch64] Create set.fpmr intrinsic and assembly lowering (#114248)
This patch introduces new llvm.set.fpmr intrinsics for setting value in
FPMR register and adds its lowering to series of read-compare-write
instructions. This intrinsic will be generated during lowering of FP8 C
intrinsics into LLVM-IR introduced in later patch.
***This is an experimental implementation of handling fp8 intriniscs and
is likely to change in the future.***
Commit: 6e4cd463e580046feb66597a61db352c63fd783b
https://github.com/llvm/llvm-project/commit/6e4cd463e580046feb66597a61db352c63fd783b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
Log Message:
-----------
[lldb] s/assertEquals/assertEqual TestDAP_sendEvent
New unittest versions don't have the "s" version.
Commit: e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
https://github.com/llvm/llvm-project/commit/e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Remove forced-sw-shadow-stack in RISCVFeatures.td (#115447)
This patch removes forced-sw-shadow-stack related statements in
RISCVFeatures.td, which was missed in the last patch
https://github.com/llvm/llvm-project/pull/115355
Commit: 0daca808ce111f21db8c0ee9ea5d2509d6034557
https://github.com/llvm/llvm-project/commit/0daca808ce111f21db8c0ee9ea5d2509d6034557
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/C/C2y/n3344.c
Log Message:
-----------
Fix issues with WG14 N3344 changes
This amends 24e2e259a06d9aa67dc278ac24dcb98da9dd63f6 with a fix for
'register void *', which is still okay as a function parameter.
Commit: 724b432410fd59c63cc313d41824eda5ec84052f
https://github.com/llvm/llvm-project/commit/724b432410fd59c63cc313d41824eda5ec84052f
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/stdalign.h
Log Message:
-----------
[z/OS] Make sure __alignas_is_defined and __alignof_is_defined are defined on z/OS. (#115368)
Commit: afa178d36017ab565c33a8639be16355a054b95b
https://github.com/llvm/llvm-project/commit/afa178d36017ab565c33a8639be16355a054b95b
Author: lfrenot <leon.frenot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
Log Message:
-----------
[mlir][LLVM] Add exact flag (#115327)
The implementation is mostly based on the one existing for the nsw and
nuw flags.
If the exact flag is present, the corresponding operation returns a
poison value when the result is not exact. (For a division, if rounding
happens; for a right shift, if a non-zero bit is shifted out.)
Commit: 5fbe9b958dc3035480406c2cd4524e4827d2dfaf
https://github.com/llvm/llvm-project/commit/5fbe9b958dc3035480406c2cd4524e4827d2dfaf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/cfguard-off-instrumented.s
Log Message:
-----------
[LLD][COFF] Set __guard_flags to CF_INSTRUMENTED if any object is instrumented (#115374)
Commit: 0e39b1348e5fcadb129a6f113e5d708a526d8faa
https://github.com/llvm/llvm-project/commit/0e39b1348e5fcadb129a6f113e5d708a526d8faa
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/test/CMakeLists.txt
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
[mlir] Remove the mlir-spirv-cpu-runner (move to mlir-cpu-runner) (#114563)
This commit builds on and completes the work done in
9f6c632ecda08bfff76b798c46d5d7cfde57b5e9 to eliminate the need for a
separate mlir-spirv-cpu-runner binary. Since the MLIR processing is
already done outside this runner, the only real difference between it
and the mlir-cpu-runner is the final linking step between the nested
LLVM IR modules. By moving this step into mlir-cpu-runner behind a new
command-line flag (`--link-nested-modules`), this commit is able to
completely remove the runner component of the mlir-spirv-cpu-runner.
The runtime libraries and the tests are moved and renamed to fit into
the Execution Engine and Integration tests, following the model of the
similar migration done for the CUDA Runner in D97463.
Commit: 231e03ba7e82896847dbc27d457dbb208f04699c
https://github.com/llvm/llvm-project/commit/231e03ba7e82896847dbc27d457dbb208f04699c
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[AArch64] Add select-opt test with select transformed to cast.
Add tests with add and sub binops with zext i1 operands.
Commit: e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
https://github.com/llvm/llvm-project/commit/e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
A clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros (#112849)
So far, these macros can be used in contexts where no meaningful
wavefront size is available. We therefore deprecate these macros, to
replace them with a more resilient interface to access wavefront size
information where it is available.
For SWDEV-491529.
Commit: 32c744ae339dc356060636bcdf75a5e2a67fca00
https://github.com/llvm/llvm-project/commit/32c744ae339dc356060636bcdf75a5e2a67fca00
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator (#115480)
It is broken after #115337
https://lab.llvm.org/buildbot/#/builders/195/builds/794
Commit: b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
https://github.com/llvm/llvm-project/commit/b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ast-print-openacc-loop-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
Log Message:
-----------
[OpenACC] Implement `loop` restrictions on `for` loops. (#115370)
OpenACC restricts the contents of a 'for' loop affected by a 'loop'
construct without a 'seq'. The loop variable must be integer, pointer,
or random-access-iterator, it must monotonically increase/decrease, and
the trip count must be computable at runtime before the function.
This patch tries to implement some of these limitations to the best of
our ability, though it causes us to be perhaps overly restrictive at the
moment. I expect we'll revisit some of these rules/add additional
supported forms of loop-variable and 'monotonically increasing' here,
but the currently enforced rules are heavily inspired by the OMP
implementation here.
Commit: 844fe8f662de6d1a51f4a04b37fadb96b2009bd0
https://github.com/llvm/llvm-project/commit/844fe8f662de6d1a51f4a04b37fadb96b2009bd0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][nfc] Rename @genbool_* as @constant_mask_* (#115335)
Renames `@genbool_*` tests as `@constant_mask_*`. That's to better
highlight which Op is tested and for better consistency with other test.
In addition,`@genbool_2d` is moved _above_ it's counterparts with
scalable vectors (again, for consistency).
Commit: d5677b630d0faf38e2e92797415ff80676f86063
https://github.com/llvm/llvm-project/commit/d5677b630d0faf38e2e92797415ff80676f86063
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/commands/target/basic/TestTargetCommand.py
Log Message:
-----------
[lldb] Fixed TestTargetCommand.py in case of Windows host and Linux target (#115470)
Fixed TestTargetCommand.py in case of Windows host and Linux target.
Commit: 107af4a62ee9afb4be2cba1bc7c12afb677445ef
https://github.com/llvm/llvm-project/commit/107af4a62ee9afb4be2cba1bc7c12afb677445ef
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Introduce struct PredInfo. NFC. (#115457)
This just provides a neater encapsulation of the info about the
predicate for an edge, rather than ValueWeightPair aka std::pair.
Commit: 644a9a4327af4fb4f7b09832cafe3c82843231b5
https://github.com/llvm/llvm-project/commit/644a9a4327af4fb4f7b09832cafe3c82843231b5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
Log Message:
-----------
[CodeExtractor][NFC] Refactor-out applyFirstDebugLoc. (#115358)
Split-off from #114419
Commit: ab9178e3e73dc715463e1019ed2cd449dc18bb18
https://github.com/llvm/llvm-project/commit/ab9178e3e73dc715463e1019ed2cd449dc18bb18
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
Log Message:
-----------
[ARM] Add a couple of new MVE reduction tests. NFC
Nowadays we generate add(zext(mul(sext, sext)) with nneg zext and the multi-use
test is awkward to get right. This should help our test coverage with the vplan
cost transition.
Commit: 3c3f19ca5ea03428edacbd5d087b991c447c47dc
https://github.com/llvm/llvm-project/commit/3c3f19ca5ea03428edacbd5d087b991c447c47dc
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/Intrinsics.cpp
Log Message:
-----------
Revert "[NFC][LLVM] Use namespace `Intrinsic` in `Intrinsics.cpp` (#114822)"
This reverts commit c2b61fcb3cd4ffa286b24437b7b6d66f0dee6c25.
Intrinsic namespace contains memcpy which is a naming conflict with
memcpy from string.h header.
Commit: 53e6f627d7e81633b2e159675884bfcce11bdc00
https://github.com/llvm/llvm-project/commit/53e6f627d7e81633b2e159675884bfcce11bdc00
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] _mm_movpi64_epi64 - convert to shufflevector pattern instead of bitcasting to i64
Don't bitcast a v1i64 to i64 as constant expressions will struggle to handle this - convert to a shufflevector concat pattern like _mm_move_epi64 instead
Commit: 0f040433d325aa68ec6840aa179f3f314c26153a
https://github.com/llvm/llvm-project/commit/0f040433d325aa68ec6840aa179f3f314c26153a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Update MMX intrinsic tests for both C/C++
Requires update to movmsk call to handle additional markers
Commit: 77bec78878762e34150fe23734fa43df796c873c
https://github.com/llvm/llvm-project/commit/77bec78878762e34150fe23734fa43df796c873c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Do not look for last instruction in schedule block for buildvectors
If looking for the insertion point for the node and the node is
a buildvector node, the compiler should not use scheduling info for such
nodes, they may contain only partial info, which is not fully correct
and may cause compiler crash.
Fixes #114082
Commit: f7bb12901e2955b972273a06dd028ab4b2822b44
https://github.com/llvm/llvm-project/commit/f7bb12901e2955b972273a06dd028ab4b2822b44
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Add tanpif16 function (#115183)
- Implementation of `tan` for 16-bit floating point inputs scaled by pi.
i.e,. `tanpif16()`
- Implementation of Tanpi in MPFRWrapper for MPFR versions < 4.2
- Exhaustive tests for `tanpif16()`
Commit: 1645d99bc9c16b1f9e2f08e36d67054498d8751e
https://github.com/llvm/llvm-project/commit/1645d99bc9c16b1f9e2f08e36d67054498d8751e
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
Log Message:
-----------
[libc++][hardening] Use `static_assert` for `__(static_)bounded_iter` (#115304)
We can't `static_assert` `__libcpp_is_contiguous_iterator` for
`__wrap_iter` currently because `__wrap_iter` is also used for wrapping
user-defined fancy pointers.
Fixes #115002.
Commit: 9aea6671085f02e6127750103ca48ae6a09ceeb8
https://github.com/llvm/llvm-project/commit/9aea6671085f02e6127750103ca48ae6a09ceeb8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Log Message:
-----------
[symbolizer] Change the ErrorHandler from llvm::function_ref to std::function. (#115477)
This fixes dangling `ErrorHandler` references
([here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp#L48-L53)
is an example).
`llvm::function_ref` doesn't own the callable, and it is not safe to
store a function_ref (the `PlainPrinterBase` stores a
`llvm::function_ref` which can easily lead to dangling references).
Commit: 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
https://github.com/llvm/llvm-project/commit/8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-lifetimebound.c
Log Message:
-----------
[clang] Permit lifetimebound in all language modes (#115482)
Lifetimebound annotations can help diagnose common cases of dangling
including escaping the address of a stack variable from a function. This
is useful in all C family languages, restricting these diagnostics to
C++ is an artificial limitation.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: da9499ebfb323602c42aeb674571fe89cec20ca6
https://github.com/llvm/llvm-project/commit/da9499ebfb323602c42aeb674571fe89cec20ca6
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293)
This patch introduces the amended feature flag for
[FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES),
'**sve-aes**'. The existing flag associated with this feature,
'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for
backwards compatibility.
The
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension)
documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1
when
> there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions
and if the associated ACLE intrinsics are available.
The front-end has been amended such that it is compatible with +sve2-aes
and +sve2+sve-aes.
Commit: 7844257fc2afe490ae4b923a770d20dabed5c3c6
https://github.com/llvm/llvm-project/commit/7844257fc2afe490ae4b923a770d20dabed5c3c6
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Use explicit #include instead of transitive #include (#115420)
This benchmark test currently uses `std::unique_ptr` without explicitly
`#include <memory>`. I think we should not rely on transitive inclusion.
Commit: c93eb43a63d3b5c90e828608b5c2063644a3b161
https://github.com/llvm/llvm-project/commit/c93eb43a63d3b5c90e828608b5c2063644a3b161
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lua_api/TestFileHandle.lua
Log Message:
-----------
[lldb] Fix TestFileHandle.lua
- Explicitly create an `SBFile`.
- Add missing call to `close`.
- Use `SetErrorFile` in TestLegacyFileErr.
Commit: e734de1f5a3c2ec0c88221eb0991b0922e30d902
https://github.com/llvm/llvm-project/commit/e734de1f5a3c2ec0c88221eb0991b0922e30d902
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
Revert "[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros" (#115499)
Reverts llvm/llvm-project#112849 due to test failure on Mac, reported by
@nico
Commit: 6737ba40406030cd8a7ea706cd56302f8be7a4b4
https://github.com/llvm/llvm-project/commit/6737ba40406030cd8a7ea706cd56302f8be7a4b4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Update the lifetimebound doc.
The lifetimebound attr is not C++ only anymore after 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Commit: c9552283c0bf277eba490cde9fd913510f4111c0
https://github.com/llvm/llvm-project/commit/c9552283c0bf277eba490cde9fd913510f4111c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for MMX _mm_set*_pi* intrinsics
Commit: 2407ff4645e9124507a4b5d910603ff7fc9e5734
https://github.com/llvm/llvm-project/commit/2407ff4645e9124507a4b5d910603ff7fc9e5734
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_movpi64_epi64
Commit: 51e8f822f39174eaf83b1d5798de329518970b02
https://github.com/llvm/llvm-project/commit/51e8f822f39174eaf83b1d5798de329518970b02
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr62014.ll
Log Message:
-----------
[X86] pr62014.ll - regenerate test checks with vpternlog comments
Commit: 71f82bba35c48eaf98c50aeeb4d2675156681c02
https://github.com/llvm/llvm-project/commit/71f82bba35c48eaf98c50aeeb4d2675156681c02
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
Log Message:
-----------
[SPIRV] Use heterogenous lookups with std::map (NFC) (#115425)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 6ce44266fc2d06dfcbefd8146279473ccada52ca
https://github.com/llvm/llvm-project/commit/6ce44266fc2d06dfcbefd8146279473ccada52ca
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/lib/IR/Dialect.cpp
Log Message:
-----------
[mlir] Use heterogenous lookups with std::map (NFC) (#115426)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: a4819d6aa30f849770c258abba67a4b721642ebf
https://github.com/llvm/llvm-project/commit/a4819d6aa30f849770c258abba67a4b721642ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/IR/MLIRContext.cpp
Log Message:
-----------
[mlir] Simplify code with StringMap::operator[] (NFC) (#115427)
Commit: bc7e5c2016e287b768d2a3a1de15f6bb644622ae
https://github.com/llvm/llvm-project/commit/bc7e5c2016e287b768d2a3a1de15f6bb644622ae
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Avoid repeated hash lookups (NFC) (#115428)
Commit: 2f243a5fb754c3688dfa225ce8073a281bca1a24
https://github.com/llvm/llvm-project/commit/2f243a5fb754c3688dfa225ce8073a281bca1a24
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for 0e39b1348e5fcadb129a6f113e5d708a526d8faa
Commit: 3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
https://github.com/llvm/llvm-project/commit/3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
Log Message:
-----------
[llvm-reduce] Reduce samesign flag from icmp (#115492)
Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Log Message:
-----------
[AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)
We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
`fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
`fma extract(Rn, 0), Rm, Ra -> fmadd`
The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
`fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
`fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`
Commit: 4027400d2ceefb5ce68d4508e5f30dc40c4f535b
https://github.com/llvm/llvm-project/commit/4027400d2ceefb5ce68d4508e5f30dc40c4f535b
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
A clang/test/C/C2y/n3342.c
M clang/test/Misc/warning-flags.c
M clang/test/Sema/declspec.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3342 (#115494)
This paper made qualified function types implementation-defined. We have
always supported this as an extension, so now we're documenting our
behavior.
Note, we still warn about this by default even in C2y mode because a
qualified function type is a sign of programmer confusion.
Commit: f756d38abf2ec40ee06ee5aa668db444e5d6f485
https://github.com/llvm/llvm-project/commit/f756d38abf2ec40ee06ee5aa668db444e5d6f485
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3342.c
Log Message:
-----------
Fix failing test bot
Fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11191
Commit: e5e15f9128b69f77668465b715b7984b8d5ad75a
https://github.com/llvm/llvm-project/commit/e5e15f9128b69f77668465b715b7984b8d5ad75a
Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
add QuietMisdreavus to Clang/ExtractAPI code owners (#115206)
Adding myself to the ExtractAPI code owners listing so i can participate
in code reviews.
Commit: 19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
https://github.com/llvm/llvm-project/commit/19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/vector-sext.ll
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use broadcast on AVX2+ targets
Make use of AVX2 broadcasts to splat the source integer across all lanes to simplify the per-lane byte shuffles.
Prep work to avoid a regression in the fix for #66150
Commit: 79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
https://github.com/llvm/llvm-project/commit/79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use SelectionDAG::getSplat helper instead of shuffle(scalar_to_vector(x))
Commit: 92e0fb0c944254312d7b9c6ca64a026643617f60
https://github.com/llvm/llvm-project/commit/92e0fb0c944254312d7b9c6ca64a026643617f60
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
Log Message:
-----------
[DebugInfo][LoopUnroll] Preserve DebugLocs on optimized cond branches (#114225)
This patch fixes a simple error where as part of loop unrolling we
optimize conditional loop-exiting branches into unconditional branches
when we know that they will or won't exit the loop, but does not
propagate the source location of the original branch to the new one.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
Log Message:
-----------
[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)
Fixes 2 old TODOs
Commit: b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
https://github.com/llvm/llvm-project/commit/b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Remove one SSAUpdater::AddAvailableValue. NFCI. (#115472)
Commit: 39358f846d1e336def88ff9c25581fab392d59fe
https://github.com/llvm/llvm-project/commit/39358f846d1e336def88ff9c25581fab392d59fe
Author: stefankoncarevic <skoncare at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/named-ops.mlir
Log Message:
-----------
[mlir][linalg] Add Grouped Convolution Ops: conv_2d_nhwgc_gfhwc and conv_2d_nhwgc_gfhwc_q (#108192)
This patch adds two new ops: linalg::Conv2DNhwgcGfhwcOp and
linalg::Conv2DNhwgcGfhwcQOp, and uses them to convert tosa group conv2d
Ops.
- Added linalg::Conv2DNhwgcGfhwcOp and linalg::Conv2DNhwgcGfhwcQOp.
- Updated the conversion process to use these new ops for tosa group
conv2d operations.
Commit: c3c2f46f7bd5891af13fef56a8754007f11ff6c1
https://github.com/llvm/llvm-project/commit/c3c2f46f7bd5891af13fef56a8754007f11ff6c1
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/test/C/C2y/n3346.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Claim conformance and add test coverage for WG14 N3346 (#115516)
This converts some undefined behaviors during initialization to instead
be constraint violations. Clang has always implemented these as
constraints, so no compiler changes were needed.
Commit: f7eba08497a2a46f2c10737a110f6b778faf1615
https://github.com/llvm/llvm-project/commit/f7eba08497a2a46f2c10737a110f6b778faf1615
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ObjectYAML/ELFEmitter.cpp
Log Message:
-----------
[ObjectYAML][ELF] Fix misspelling in `Elf_Verdaux` var name (NFC)
Commit: 60972a893e2bf915f6ff043c9396dea9619456fb
https://github.com/llvm/llvm-project/commit/60972a893e2bf915f6ff043c9396dea9619456fb
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/obj2yaml/elf2yaml.cpp
Log Message:
-----------
[ObjectYAML][ELF] Allow verdaux entry offset to be user-defined
Commit: b85e5b49d3efc37e837757a5154884648dc57113
https://github.com/llvm/llvm-project/commit/b85e5b49d3efc37e837757a5154884648dc57113
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Speculatively fix test bots
This should address the issues found by:
https://lab.llvm.org/buildbot/#/builders/12/builds/9226
https://lab.llvm.org/buildbot/#/builders/140/builds/10487
https://lab.llvm.org/buildbot/#/builders/27/builds/1752
Commit: d30a6dcfa06196dd98fc898219eb12bab04a56de
https://github.com/llvm/llvm-project/commit/d30a6dcfa06196dd98fc898219eb12bab04a56de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
Log Message:
-----------
[AMDGPU] Reorganize tests to unblock #112403 (#115503)
We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the `[15 x i32]` arguments to
`[13 x i32]` to bypass the issue.
Commit: e215a1e27d84adad2635a52393621eb4fa439dc9
https://github.com/llvm/llvm-project/commit/e215a1e27d84adad2635a52393621eb4fa439dc9
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
Commit: 4661467003e7bc7f9bb89ab581517617d2a36c62
https://github.com/llvm/llvm-project/commit/4661467003e7bc7f9bb89ab581517617d2a36c62
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
A clang/test/C/C2y/n3341.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3341 (#115478)
This paper made empty structures and unions implementation-defined. We
have always supported this as a GNU extension, so now we're documenting
our behavior and removing the extension warning in C2y mode.
Commit: b70d1302cf2edaf95817a90f161691c684945273
https://github.com/llvm/llvm-project/commit/b70d1302cf2edaf95817a90f161691c684945273
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Another speculative fix for WG14 N3346
This time it's for builders that don't default to C11 or later, such as:
https://lab.llvm.org/buildbot/#/builders/144/builds/11201
Commit: 2808f05e83643b3d5ef128340f6f4da994ed71e3
https://github.com/llvm/llvm-project/commit/2808f05e83643b3d5ef128340f6f4da994ed71e3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3341.c
Log Message:
-----------
Update test case for bots which don't default to C17
Commit: 17f3e00911b860d535f41185e605c47babcc2039
https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
The increase in fallbacks that was previously reported were not caused
by this change.
Original description:
This matches InstCombine and DAGCombine.
RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.
Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
Commit: e4d57d6a729fd955ccbdd8834065356f26284f3d
https://github.com/llvm/llvm-project/commit/e4d57d6a729fd955ccbdd8834065356f26284f3d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
Log Message:
-----------
[OpenACC] Remove 'loop' link to parent construct
After implementing 'loop', we determined that the link to its parent
only ever uses the type, not the construct itself. This patch removes
it, as it is both a waste and causes problems with serialization.
Commit: e53c46a9084caac115d7f694e5f16f904b0d7124
https://github.com/llvm/llvm-project/commit/e53c46a9084caac115d7f694e5f16f904b0d7124
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
Log Message:
-----------
[Statepoint] Treat result of atomicrmw xchg as a base pointer (#97280)
Atomic RMW Xchg wasn't handled before when searching for known base
pointers in the IR.
Commit: 40740c4494d971ce410e2051b8d3ea7bbe081c76
https://github.com/llvm/llvm-project/commit/40740c4494d971ce410e2051b8d3ea7bbe081c76
Author: Siddhesh Deodhar <153800103+siddhesh195 at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
Log Message:
-----------
Fix crash when using when using --finalize-memref-to-llvm (#112433)
This patch fixes crash when attempting to convert uint to int address
space during finalize-memref-to-llvm by doing the following:
1. Add a check to verify that IntegerAttr is signed int before calling
IntegerAttr::getInt()
2. Emit error when getMemRefAddressSpace returns a failure()
Closes #111242
---------
Co-authored-by: Christian Ulmann <christianulmann at gmail.com>
Commit: 2b885f056585f82903f067840e54557a5b444b65
https://github.com/llvm/llvm-project/commit/2b885f056585f82903f067840e54557a5b444b65
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Fix test for bots that don't default to C17
Commit: a749c98b49dc9a3863b685212d70be98b4f189c3
https://github.com/llvm/llvm-project/commit/a749c98b49dc9a3863b685212d70be98b4f189c3
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Baze] Add missing lldbDataFormatter.py back to BUILD.bazel. (#115519)
- [x] Add `utils/lldbDataFormatters.py` back.
Commit: fe5a64d1160209f22624b112b2629b0d6c4bb264
https://github.com/llvm/llvm-project/commit/fe5a64d1160209f22624b112b2629b0d6c4bb264
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
Log Message:
-----------
[fang][cuda] Allow * in call chevron syntax (#115381)
Using `*` in call chevron syntax should be allowed. This patch updates
the parser to allow this usage.
```
call sub<<<*,nbBlock>>>()
```
Commit: 86405ed1012c97b063cbde12350fdea141e1ab78
https://github.com/llvm/llvm-project/commit/86405ed1012c97b063cbde12350fdea141e1ab78
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
Log Message:
-----------
[DebugInfo][Reassociate] Preserve DebugLocs when reassociating subs (#114226)
In NegateValue in Reassociate, we return the negation of an existing
value in order to break a subtract into an negate + add, potentially
creating a new instruction to perform the negation, but we neglect to
propagate the DebugLoc of the sub being replaced to the negate
instruction if one is created. This patch adds that propagation.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 40e545098e8bb5a18988316331e46c4557378afa
https://github.com/llvm/llvm-project/commit/40e545098e8bb5a18988316331e46c4557378afa
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[clang][CIR] Move CIRGen types into clang::CIRGen (#115385)
https://github.com/llvm/clangir/issues/1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.
Commit: c72389d4feef9eafc902f99c41f85ed218b5bedf
https://github.com/llvm/llvm-project/commit/c72389d4feef9eafc902f99c41f85ed218b5bedf
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
Log Message:
-----------
[clang][CIR] Merge the mlir::cir namespace into cir (#115386)
https://github.com/llvm/clangir/issues/1025 discusses the motivation.
The mechanical parts of this change were done via:
find clang \( -name '*.h' -o -name '*.cpp' -o -name '*.td' \) -print0 |
xargs -0 perl -pi -e 's/mlir::cir/cir/g'
find clang \( -name '*.h' -o -name '*.cpp' \) -print0 | xargs -0 perl
-pi -e 's/::cir/cir/g'
There were some manual fixups and a clang-format run afterwards.
Commit: 0dbdb3251fe1f276785015c1de3b0a1035c9de8f
https://github.com/llvm/llvm-project/commit/0dbdb3251fe1f276785015c1de3b0a1035c9de8f
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Remove mlir-spirv-cpu-runner after 0e39b1348e5fcadb129a6f113e… (#115533)
…5d708a526d8faa
Commit: e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
https://github.com/llvm/llvm-project/commit/e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/AST/Decl.cpp
Log Message:
-----------
[clang] Avoid unnecessary call to clang::NamespaceDecl::isRedundantInlineQualifierFor(). (#115196)
We observed 2X slowdown in lldb's expression evaluation with
https://github.com/llvm/llvm-project/pull/109147 in some cases. It turns
out that calling `isRedundantInlineQualifierFor` is quite expensive.
Using short-circuit evaluation in the if statement to avoid unnecessary
calls to that function.
Commit: 5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
https://github.com/llvm/llvm-project/commit/5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
[RISCV] Add sub_to_add to RISCVPostLegalizerCombiner.
Commit: e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
https://github.com/llvm/llvm-project/commit/e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
Log Message:
-----------
[GlobalISel][AArch64] Allow vector ptr to int unmerges (#115228)
Vector pointer -> scalar integer unmerges are already legal. This
loosens the verifier check for vector-of-pointers -> vectors.
Commit: a29e623e1257b100b507c592a405fee2e0ff34b9
https://github.com/llvm/llvm-project/commit/a29e623e1257b100b507c592a405fee2e0ff34b9
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
Log Message:
-----------
[compiler-rt] Make add_custom_libcxx() resilient to DESTDIR being set
If DESTDIR is set in the environment during the build/test stage, the
local libc++ installation will be installed under DESTDIR instead of being
in the build directory.
See https://github.com/llvm/llvm-project/pull/115077#issuecomment-2464640457
and https://gitlab.kitware.com/cmake/cmake/-/issues/18165.
Pull Request: https://github.com/llvm/llvm-project/pull/115525
Commit: bbcd35270ef4597402b924d547d845893e7fd165
https://github.com/llvm/llvm-project/commit/bbcd35270ef4597402b924d547d845893e7fd165
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (#115539)
…293)"
This reverts commit da9499ebfb323602c42aeb674571fe89cec20ca6.
Commit: 6fb36f0bd0a34e6429960247cf088557ae7a6e96
https://github.com/llvm/llvm-project/commit/6fb36f0bd0a34e6429960247cf088557ae7a6e96
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
Log Message:
-----------
[flang][OpenMP] Remove std::variant with single alternative, NFC
Commit: 7dffc96a54f90569d6226dd5713c80fc8f30c76f
https://github.com/llvm/llvm-project/commit/7dffc96a54f90569d6226dd5713c80fc8f30c76f
Author: vporpo <vporpodas at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Clean up dead instructions (#115267)
When scalars get replaced by vectors the original scalars may become
dead. In that case erase them.
Commit: 144bdf3eb7128518ed162c5a168e3ec90922cd9e
https://github.com/llvm/llvm-project/commit/144bdf3eb7128518ed162c5a168e3ec90922cd9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
Log Message:
-----------
[VPlan] Also check if plan for best legacy VF contains simplifications.
The plan for the VF chosen by the legacy cost model could also contain
additional simplifications that cause cost differences. Also check if it
contains simplifications.
Fixes https://github.com/llvm/llvm-project/issues/114860.
Commit: db6f476e8e29c42691a3c3ea97d7230af2be5df8
https://github.com/llvm/llvm-project/commit/db6f476e8e29c42691a3c3ea97d7230af2be5df8
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Use "countMaxActiveBits() <= 5" to define uint5Bits (#115543)
countMaxTrailingOnes() is not correct. This patch follows the suggestion
from https://github.com/llvm/llvm-project/pull/115372.
Commit: 30ee3f4ec767f2f183d74eb949afa80b8b6261e2
https://github.com/llvm/llvm-project/commit/30ee3f4ec767f2f183d74eb949afa80b8b6261e2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)
Commit: 552f6fe4d503900cae7620f2ddfd7393be670d27
https://github.com/llvm/llvm-project/commit/552f6fe4d503900cae7620f2ddfd7393be670d27
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
Log Message:
-----------
[RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (#115402)
We don't add a custom node for REMW as we can detect it with (srem
(sexti32), (sexti32)).
Commit: dbad9412909a1879f29a4f717b2bf149c9a58369
https://github.com/llvm/llvm-project/commit/dbad9412909a1879f29a4f717b2bf149c9a58369
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Basic/Attributes.cpp
Log Message:
-----------
[NFC][Clang] Use StringSwitch instead of array for parsing attribute scope (#115414)
Commit: b99d4112585302cbd01f9b851a04adc6e4fb5218
https://github.com/llvm/llvm-project/commit/b99d4112585302cbd01f9b851a04adc6e4fb5218
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactoring breakpoints to not use the `g_dap` reference. (#115208)
Refactoring breakpoints to not use the `g_dap` reference.
Instead, when a breakpoint is constructed it will be passed a DAP
reference that it should use for its lifetime.
This is part of a larger refactor to remove the global `g_dap` variable
to allow us to create multiple DAP instances.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: ca33649abe5fad93c57afef54e43ed9b3249cd86
https://github.com/llvm/llvm-project/commit/ca33649abe5fad93c57afef54e43ed9b3249cd86
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
Commit: ccc9d7dc7af535aa240a96bc999911ee9ba2d534
https://github.com/llvm/llvm-project/commit/ccc9d7dc7af535aa240a96bc999911ee9ba2d534
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Update and extend ptradd.ll test. NFC
We can now support v4p0 pointers without running into verifier issues.
Commit: 441b82b20bf3a622155354e17ae66e0ccff50796
https://github.com/llvm/llvm-project/commit/441b82b20bf3a622155354e17ae66e0ccff50796
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/test/Dialect/Vector/int-range-interface.mlir
Log Message:
-----------
[mlir][NFC] IntegerRangeAnalysis: don't loop over splat attr (#115399)
Reland https://github.com/llvm/llvm-project/pull/115229 which was
reverted by https://github.com/llvm/llvm-project/pull/115388 because it
was hitting an assertion in IREE. From the original change: If the
`DenseIntElementsAttr` is a splat value, there is no need to loop over
the entire attr. Instead, just update with the splat value.
The problem with the original implementation is that `SplatElementsAttr`
might be an attr of non `APInt` (e.g. float) elements. Instead, check if
`DenseIntElementsAttr` is splat and use the splat value. Added a test to
ensure there's no crash when handling float attrs.
Commit: 8a7a7b5ffc690bd012cf090d31d47ec938248ba3
https://github.com/llvm/llvm-project/commit/8a7a7b5ffc690bd012cf090d31d47ec938248ba3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Remove unneeded code connecting blocks in VPBB:splitAt (NFC).
insertBlockAfter already takes care of transferring successors. Remove
unneeded code to transfer them manually.
Commit: 26a9f3f5906c62cff7f2245b98affa432b504a87
https://github.com/llvm/llvm-project/commit/26a9f3f5906c62cff7f2245b98affa432b504a87
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Cleanup getSameOpcode, return InstructionsState::invalid() for non-valid inputs
Just a cleanup and related changes
Commit: 8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
https://github.com/llvm/llvm-project/commit/8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/JSONUtils.cpp
Log Message:
-----------
[lldb-dap] Fix lldb-dap build for windows, missing PATH_MAX. (#115551)
This should fix https://lab.llvm.org/buildbot/#/builders/141/builds/3722
Commit: 7a6a52a2f0c6af63f210562d4a0345232d30d54d
https://github.com/llvm/llvm-project/commit/7a6a52a2f0c6af63f210562d4a0345232d30d54d
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/SandboxIR/Instruction.cpp
Log Message:
-----------
[SandboxIR] Remove incorrect assertion. (#115553)
`insertBefore` can be called on a detached instruction, and we can't
check that the underlying instructions are ordered because instructions
without BB parents have no order.
This problem showed up as a different assertion failure in
`llvm::Instruction::comesBefore` in one of the unit tests when
`EXPENSIVE_CHECKS` are enabled.
Commit: fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
https://github.com/llvm/llvm-project/commit/fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
Log Message:
-----------
[AMDGPU] Disable verifier in `call-args-inreg-no-sgpr-for-csrspill-xfail.ll`
Similar to f9bd083, this could fix expensive check failure.
Commit: d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
https://github.com/llvm/llvm-project/commit/d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Support derived type in cuf.alloc (#115550)
Number of bytes to allocate was not computed when using `cuf.alloc` with
a derived type. Update the conversion to compute the number of bytes and
emit an error when type is not supported.
Commit: 023483f5ba6bbbec64bb340578b00bfa3399691d
https://github.com/llvm/llvm-project/commit/023483f5ba6bbbec64bb340578b00bfa3399691d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
Log Message:
-----------
[flang][cuda][NFC] Add test for <<<*, block>>> lowering (#115534)
Chevron syntax has been update to allow `*` to be used for the grid
value. Make sure we set the three grid values to -1, 1, 1 in lowering.
Commit: 6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
https://github.com/llvm/llvm-project/commit/6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/runtime/CUDA/kernel.cpp
Log Message:
-----------
[flang][cuda] Compute grid x when calling a kernel with <<<*, block>>> (#115538)
`-1, 1, 1` is passed when calling a kernel with the `<<<*, block>>>`
syntax. Query the device to compute the grid.x value.
Commit: 50850bc78b00b991cb361cb94a151befd83f6a5d
https://github.com/llvm/llvm-project/commit/50850bc78b00b991cb361cb94a151befd83f6a5d
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[LV] Add test for preserving flags when widening casts; NFC
Commit: 8af5ae0648f85b9196a794700ebe5468a0cefd6b
https://github.com/llvm/llvm-project/commit/8af5ae0648f85b9196a794700ebe5468a0cefd6b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[VPlan] Preserve IR flags when widening casts
We have `nneg` for both `sext` and `uitofp`.
Fixes #114856
Closes #115373
Commit: 738250989ce516f02f809bdfde474a039c77e81f
https://github.com/llvm/llvm-project/commit/738250989ce516f02f809bdfde474a039c77e81f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
Log Message:
-----------
[Clang][perf-training] Do build of libLLVMSupport for perf training (#111625)
This adds a build of the libLLVMSupport to the lit suite that is used
for generating profile data. This helps to improve both PGO and BOLT
optimization of clang over the existing hello world training program.
I considered building all of LLVM instead of just libLLVMSupport, but
there is only a marginal increase in performance for PGO only builds
when training with a build of all of LLVM, and I didn't think it was
enough to justify the increased build times given that it is the default
configuration.
The benchmark[1] I did showed that using libLLVMSupport for training
gives a 1.35 +- 0.02 speed up for clang optimized with PGO + BOLT vs
just 1.05 +- 0.01 speed up when training with hello world.
For comparison, training with a full LLVM build gave a speed up of 1.35
+- 0.1.
Raw data:
| PGO Training | BOLT Training | Speed Up | Error Range |
| ------------ | ------------- | -------- | ----------- |
| LLVM Support | LLVM Support | 1.35 | 0.02 |
| LLVM All | LLVM All | 1.34 | 0.01 |
| LLVM Support | Hello World | 1.29 | 0.02 |
| LLVM All | PGO-ONLY | 1.27 | 0.02 |
| LLVM Support | PGO-ONLY | 1.22 | 0.02 |
| Hello World | Hello World | 1.05 | 0.01 |
| Hello World | PGO-ONLY | 1.03 | 0.01 |
Time it takes to generate profile data (on a 64-core system):
| Training Data | PGO | BOLT |
| ------------- | ----- | ----- |
| LLVM All | 1090s | 3239s |
| LLVM Support | 91s | 655s |
| Hello World | 2s | 9s |
[1] Benchmark was compiling SemaDecl.cpp
Commit: d936924f5e22e8efbc27873f62e8dfc6e410fcf9
https://github.com/llvm/llvm-project/commit/d936924f5e22e8efbc27873f62e8dfc6e410fcf9
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Profile/YAMLProfileReader.cpp
Log Message:
-----------
[BOLT][NFC] Make YamlProfileToFunction a DenseMap (#108712)
YAML function profiles have sparse function IDs, assigned from
sequential function IDs from profiled binary. For example, for one large
binary, YAML profile has 15K functions, but the highest ID is ~600K,
close to number of functions in the profiled binary.
In `matchProfileToFunction`, `YamlProfileToFunction` vector was resized
to match function ID, which entails a 40X overcommit. Change the type of
`YamlProfileToFunction` to DenseMap to reduce memory utilization.
#99891 makes use of it for profile lookup associated with a given binary
function.
Commit: 62a7bb09e3646780b7bceb7cef4eba257e3a9818
https://github.com/llvm/llvm-project/commit/62a7bb09e3646780b7bceb7cef4eba257e3a9818
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Resolve CHECK prefix conflict and add a bunch of FIXMEs to bitmanip tests. NFC
Commit: bc1aa2863bd33756a5cc0b729792be0aabed67f4
https://github.com/llvm/llvm-project/commit/bc1aa2863bd33756a5cc0b729792be0aabed67f4
Author: Lei Wang <wlei at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/test/Other/new-pm-pgo-O0.ll
Log Message:
-----------
[SampleFDO] Support enabling sample loader pass in O0 mode (#113985)
Add support for enabling sample loader pass in O0 mode(under
`-fsample-profile-use`). This can help verify PGO raw profile count
quality or provide a more accurate performance proxy(predictor), as O0
mode has minimal or no compiler optimizations that might otherwise
impact profile count accuracy.
- Explicitly disable the sample loader inlining to ensure it only emits
sampling annotation.
- Use flattened profile for O0 mode.
- Add the pass after `AddDiscriminatorsPass` pass to work with
`-fdebug-info-for-profiling`.
Commit: cb98366ea4ce02e739eb4091c6227b67b60616c9
https://github.com/llvm/llvm-project/commit/cb98366ea4ce02e739eb4091c6227b67b60616c9
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add exp10m1f (#115565)
Commit: ff98efa329f3866ed7ddd461e9473729c2b91568
https://github.com/llvm/llvm-project/commit/ff98efa329f3866ed7ddd461e9473729c2b91568
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV][GISel] Enable shift_immed_chain in RISCVPostLegalizerCombiner
This helps combine back to back shifts that may get created when
sext_inreg is legalized.
Commit: 818d715989a82a54bac038b9c293e34dbea45f5c
https://github.com/llvm/llvm-project/commit/818d715989a82a54bac038b9c293e34dbea45f5c
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] atan2: isTriviallyVectorizable; add to massv and accelerate veclibs (#113637)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
- Return true for atan2 from isTriviallyVectorizable
- Add atan2 to VecFuncs.def for massv and accelerate libraries.
- Add atan2 to hasOptimizedCodeGen
- Add atan2 support in llvm/lib/Analysis/ValueTracking.cpp
llvm::getIntrinsicForCallSite and update vectorization tests
- Add atan2 name check to isLoweredToCall in
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
- Note: there's no test coverage for these names in isLoweredToCall, except that Transforms/TailCallElim/inf-recursion.ll is impacted by the "fabs" case
Thanks to @jroelofs for the atan2 accelerate veclib and associated test
additions, plus the hasOptimizedCodeGen addition.
Part of: Implement the atan2 HLSL Function #70096.
Commit: ff2251543069d9a195256617620b5fdf81512471
https://github.com/llvm/llvm-project/commit/ff2251543069d9a195256617620b5fdf81512471
Author: Alan Zhao <ayzhao at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
R clang/test/CodeGen/X86/amx_avx512_api.c
R clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
R llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
R llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
R llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
R llvm/test/MC/Disassembler/X86/amx-avx512.txt
R llvm/test/MC/X86/amx-avx512-att.s
R llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070
Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
Commit: f791cfc822fab3fa87b4aa10ef96a3401481850f
https://github.com/llvm/llvm-project/commit/f791cfc822fab3fa87b4aa10ef96a3401481850f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port ff2251543069
Commit: 7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
https://github.com/llvm/llvm-project/commit/7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/lib/MC/MCPseudoProbe.cpp
Log Message:
-----------
[MC] Use StringRefs from pseudo_probe_desc section if it's mapped
Add `IsMMapped` flag to `buildGUID2FuncDescMap` controlling whether to
allocate a string in `FuncNameAllocator` or use StringRef directly.
Keep it false by default, only set it for BOLT use case because BOLT
keeps file sections in memory while processing them. llvm-profgen
constructs GUID2FuncDescMap and then releases the binary.
For medium sized binary with 0.8 GiB .pseudo_probe_desc section, this
saves 0.7 GiB peak RSS in perf2bolt.
Test Plan: no-op for llvm-profgen, NFC for perf2bolt
Reviewers: maksfb, dcci, wlei-llvm, rafaelauler, ayermolo
Reviewed By: wlei-llvm
Pull Request: https://github.com/llvm/llvm-project/pull/112996
Commit: b70eb8631386bbccca5a07bb0253aa738d4cda81
https://github.com/llvm/llvm-project/commit/b70eb8631386bbccca5a07bb0253aa738d4cda81
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
Log Message:
-----------
[lld][WebAssemlby] Implement --thinlto-object-suffix-replace/--thinlto-prefix-replace (#114625)
Fixes: #79604
Commit: 6548b6354d1d990e1c98736f5e7c3de876bedc8e
https://github.com/llvm/llvm-project/commit/6548b6354d1d990e1c98736f5e7c3de876bedc8e
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
Commit: d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
https://github.com/llvm/llvm-project/commit/d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
Log Message:
-----------
[HLSL] Add Append/ConsumeStructuredBuffer definitions to HLSLExternalSemaSource (#113643)
Adds `AppendStructuredBuffer` and `ConsumeStructuredBuffer` definition
to HLSLExternalSemaSource. Adds separate tests for the AST shape and
element types, and adds constructor/handle.fromBinding test case to
shared test file for structured buffers.
These buffers do not have any subscript operators. Append and Consume
methods will be added later in llvm/llvm-project#112968.
Fixes #112777
Commit: c93e001ca695e905cb965b36d63f7a348d1dd809
https://github.com/llvm/llvm-project/commit/c93e001ca695e905cb965b36d63f7a348d1dd809
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
Log Message:
-----------
[FIX][AMDGPU] Fix test case failures that caused by reapply of #112403
Commit: 60ea60e36eb6de19e8e509e5b50a390e95801321
https://github.com/llvm/llvm-project/commit/60ea60e36eb6de19e8e509e5b50a390e95801321
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Log Message:
-----------
[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC
Commit: c61832444d7539eddb939df1107a751a6784aff3
https://github.com/llvm/llvm-project/commit/c61832444d7539eddb939df1107a751a6784aff3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Teach extractCallsFromIR to look into inline stacks (#115441)
To undrift the profile, we need to extract as many caller-callee pairs
from the IR as we can to maximize the number of call sites in the
profile we can undrift.
Now, since MemProfUsePass runs after early inlining, some functions
have been inlined, and we may no longer have bodies for those
functions in the IR. To cope with this, this patch teaches
extractCallsFromIR to extract caller-calee pairs from inline stacks.
The output format of extractCallsFromIR remains the same. We still
return a map from caller GUIDs to lists of corresponding call sites.
Commit: 1bf385f10291101163a346c8f075d56e1578351b
https://github.com/llvm/llvm-project/commit/1bf385f10291101163a346c8f075d56e1578351b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
Log Message:
-----------
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
Commit: fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
https://github.com/llvm/llvm-project/commit/fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Add a comment why an export file is needed. (#115556)
- [x] Add follow-up comment on why the export file is needed in
BUILD.bazel
Commit: 501a58344179242f702f55e0ee5c039290426c54
https://github.com/llvm/llvm-project/commit/501a58344179242f702f55e0ee5c039290426c54
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
Log Message:
-----------
[TableGen][SelectionDAG] Remove the `implicit` DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`
However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`
The latter form is also more flexible as it allows reordering output
operands.
In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.
Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
Commit: 5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
https://github.com/llvm/llvm-project/commit/5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
Author: Mirko <mirkomueller97 at live.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/LiveRangeShrink.cpp
A llvm/test/CodeGen/X86/lrshrink-debug.ll
Log Message:
-----------
[CodeGen][X86] LiveRangeShrink: fix increment after end (#115276)
This fixes the infinite loop discovered in #114195.
Since we skip debug instructions at the start of the loop we do not need
to skip them again at the end of the loop.
Commit: 8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
https://github.com/llvm/llvm-project/commit/8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
Commit: cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
https://github.com/llvm/llvm-project/commit/cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 8f4401374ca1
Commit: 09b372aa60548b8ee94a801d3d966001ad60a677
https://github.com/llvm/llvm-project/commit/09b372aa60548b8ee94a801d3d966001ad60a677
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576)
SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses
a literal constant operand.
For vectors, SelectionDAG uses a type with the same number of elements
as other operand of the sext_inreg. I assume for GISel we would just use
the scalar size.
Commit: b83399eab603320d3c2998450f4ada83e7fe746c
https://github.com/llvm/llvm-project/commit/b83399eab603320d3c2998450f4ada83e7fe746c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
Log Message:
-----------
[GlobalISel] Remove unused includes (NFC) (#115429)
Identified with misc-include-cleaner.
Commit: fe6366928201b7500ee7e903c01bf4bbd661ee2d
https://github.com/llvm/llvm-project/commit/fe6366928201b7500ee7e903c01bf4bbd661ee2d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
A llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Support `MachineFunction` in `OptNoneInstrumentation` (#115471)
Support `MachineFunction` in `OptNoneInstrumentation`, also add
`isRequired` to all necessary passes.
Commit: 9afec3ca3e926cd481af372b72ee5bd7e54942d0
https://github.com/llvm/llvm-project/commit/9afec3ca3e926cd481af372b72ee5bd7e54942d0
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Fix test failure in #115471 (#115596)
Add triple to indicate this is x86 test.
Commit: 5a41800ea1d9bf382cf1039da6016550ddb072d7
https://github.com/llvm/llvm-project/commit/5a41800ea1d9bf382cf1039da6016550ddb072d7
Author: Afanasyev Ivan <ivafanas at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[SROA] Fix NumPromoted statistic for SROA pass (#115586)
`NumPromoted` stat should not be increased if `SROASkipMem2Reg` is set
and nothing is changed.
Commit: 10f35a04c94e96c1cc0497f2b3b2ab8536a98059
https://github.com/llvm/llvm-project/commit/10f35a04c94e96c1cc0497f2b3b2ab8536a98059
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Log Message:
-----------
[InstCombine] add control for SimplifyDemandedVectorElts depth limit (#113717)
Allows customizing the depth of the recursive search on vectors that
InstCombine does when looking for unused elements.
We find it helpful to be able to customize this for compile time
reasons.
Commit: 5a08acc1e7874a6cb4b273988b83e587e6fea605
https://github.com/llvm/llvm-project/commit/5a08acc1e7874a6cb4b273988b83e587e6fea605
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
Log Message:
-----------
[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)
Without this, you get an error "Do not know how to soften the result of
this operator!" when compiling for a soft float target.
The libcall names match those defined in glibc
<https://www.gnu.org/software/libc/manual/html_node/Misc-FP-Arithmetic.html>
and more recently added to LLVM's libc
<https://github.com/llvm/llvm-project/pull/86016>.
Commit: ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
https://github.com/llvm/llvm-project/commit/ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
Log Message:
-----------
[RISCV] When using global merging, don't enable merging of external globals by default (#115484)
AArch64 left this disabled after seeing some cases of slightly worse
codegen that weren't tracked down, so I suggest as a path to
incrementally moving towards enable globals merging we follow suit, and
evaluate turning on later.
This patch disables merging of external globals, but also adds a flag to
override that. This reduces churn in test cases, simplifies benchmarking
runs, and this flag can be removed later.
A follow-on PR enables the globals merging pass by default (and as it's
based on this commit, merging of external globals is disabled just as
they are for AArch64).
Commit: 8833a4474654f7413ae3c53a15e350e06bce2d2e
https://github.com/llvm/llvm-project/commit/8833a4474654f7413ae3c53a15e350e06bce2d2e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Connect scalar header to CFG in VPlan unit test.
This makes sure the VPIRBasicBlock is deleted when the VPlan is
destroyed.
Fixes https://github.com/llvm/llvm-project/issues/114623.
Commit: 581106759a3eb85d37aa004e0ad795dc8b433080
https://github.com/llvm/llvm-project/commit/581106759a3eb85d37aa004e0ad795dc8b433080
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/lto-arm64ec.ll
Log Message:
-----------
[LLD][COFF] Support ARM64EC in BitcodeFile::getMachineType (#115474)
Commit: 1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
https://github.com/llvm/llvm-project/commit/1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
Log Message:
-----------
[InstCombine] Add extra tests for preserving load metadata.
Test cases for https://github.com/llvm/llvm-project/issues/115595.
Commit: 56253c79c61fb5478bc3162cfe1e25e98791a148
https://github.com/llvm/llvm-project/commit/56253c79c61fb5478bc3162cfe1e25e98791a148
Author: David Green <david.green at arm.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Generate ptrtoint/inttoptr as opposed to bitcast in unmerge combine. (#115225)
When combining unmerge we could end up with ptr to i64 bitcasts. Make
sure they are created as ptrtoint/inttoptr instead.
Commit: 7ac62f33cffb618758edb6a0997c21b2319fbf9b
https://github.com/llvm/llvm-project/commit/7ac62f33cffb618758edb6a0997c21b2319fbf9b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add load/select test with noundef/invariant.load.
Further extends the test coverage added in 1aff96b3dfc with a load with
noundef and invariant.load metadata, which may trigger UB.
Commit: 6beaa123a2899f52dd5f37b881d7fc398d70e167
https://github.com/llvm/llvm-project/commit/6beaa123a2899f52dd5f37b881d7fc398d70e167
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrUtils.td
Log Message:
-----------
[X86] Make use of `null_frag` (NFC) (#115601)
Commit: 1d41543c95f884e6ebecc63ab9d0d30ce481345c
https://github.com/llvm/llvm-project/commit/1d41543c95f884e6ebecc63ab9d0d30ce481345c
Author: lntue <lntue at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M libc/src/math/generic/log1p.cpp
M libc/test/src/math/smoke/log1p_test.cpp
Log Message:
-----------
[libc][math] Fix log1p SEGV with large inputs when FTZ/DAZ flags are set. (#115541)
Commit: 3654183afb283c9515a482f07fde730dd458a883
https://github.com/llvm/llvm-project/commit/3654183afb283c9515a482f07fde730dd458a883
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Allow promotion if target is a declaration (#115555)
Fixes an oversight in the MemProf ICP handling, that was blocking
promotion/cloning of indirect calls when the profiled target is a
declaration (i.e wasn't imported). There is no issue promoting in
that case, and in fact the comment mentions we should attempt to at
least import as declarations to enable more promotion.
Note that normal ICP currently requires that the target be a definition,
which is how this check ended up here. The comment there says that it
must be a definition because ThinLTO could remove declarations for
symbols found to be globally dead in the binary. However, here we are
always performing MemProf ICP in the ThinLTO backends, which is after
the globally dead symbols are removed (via dropDeadSymbols before
starting the optimization pipeline) [1].
For now, guard this with an option (flag is off which means the new
promotion is enabled by default) to simplify debugging or disabling it
if
this proves problematic.
[1] In fact we could also be more aggressive in regular ICP when invoked
in the ThinLTO backend
Commit: 6fb2a6044f11e251c3847d227049d9dae8b87796
https://github.com/llvm/llvm-project/commit/6fb2a6044f11e251c3847d227049d9dae8b87796
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] Add test coverage for #115575
Commit: 958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
https://github.com/llvm/llvm-project/commit/958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] scalarizeBinopOrCmp - check for out of bounds element indices
Fixes #115575
Commit: ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
https://github.com/llvm/llvm-project/commit/ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
Log Message:
-----------
[Inliner] Prevent adding pointer attributes to non-pointer arguments (#115569)
Fixes a crash seen after #114311
Commit: c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
https://github.com/llvm/llvm-project/commit/c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
Log Message:
-----------
[lldb-dap] Use heterogenous lookups with std::map (NFC) (#115590)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: eedff8b4c0c667c39b034f02c9a40693dff63eda
https://github.com/llvm/llvm-project/commit/eedff8b4c0c667c39b034f02c9a40693dff63eda
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
Log Message:
-----------
[DebugInfo] Simplify code with std::map::operator[] (NFC) (#115591)
Commit: dfe43bd1ca46c59399b7cbbf81b09256232e27f9
https://github.com/llvm/llvm-project/commit/dfe43bd1ca46c59399b7cbbf81b09256232e27f9
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
Log Message:
-----------
[X86] Remove unused includes (NFC) (#115593)
Identified with misc-include-cleaner.
Commit: 95eeae195e608797314d71f7327e638a98764471
https://github.com/llvm/llvm-project/commit/95eeae195e608797314d71f7327e638a98764471
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add PredIdx and SuccIdx arguments to connectBlocks (NFC).
Add extra arguments to connectBlocks which allow selecting which
existing predecessor/successor to update. This avoids having to
disconnect blocks first unnecessarily.
Suggested in https://github.com/llvm/llvm-project/pull/114292.
Commit: f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
https://github.com/llvm/llvm-project/commit/f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/tools/llvm-pdbutil/PdbYaml.h
Log Message:
-----------
[llvm] Add explicit visibility macros to YAMLTraits classes (#111484)
These symbols need to be exported for llvm-pdbutil when using windows
shared library builds.
Exclude the YAML traits declared in llvm-pdbutil so there not declared
as dllimported which will causing missing symbol errors for windows
shared library builds.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
window.
Commit: 230946fad69c952dc434aa3e2f92853c1ee8d304
https://github.com/llvm/llvm-project/commit/230946fad69c952dc434aa3e2f92853c1ee8d304
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
Log Message:
-----------
[ADT] Mark reverse and concat as nodiscard (#115611)
It may not be immediately obvious if these two functions modify the
given ranges or return a view over them. We have seen downstream code
that mistakenly assumed the given range would be mutated.
Add the `[[nodiscard]]` attribute to prevent these errors. Also clarify
the lack of mutation in the documentation comments.
Commit: 69fb9bcde0312e672e6f2280f8662784731d79e6
https://github.com/llvm/llvm-project/commit/69fb9bcde0312e672e6f2280f8662784731d79e6
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
Log Message:
-----------
Fix false positive in bugprone-throw-keyword-missing (#115302)
Fixes #115055
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
https://github.com/llvm/llvm-project/commit/ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add insertOnEdge to VPBlockUtils (NFC).
Add a new helper to insert a new VPBlockBase on an edge between 2
blocks. Suggested in https://github.com/llvm/llvm-project/pull/114292
and also useful for some existing code.
Commit: c236dbc343b497c11790adc61cf4e041aeb42dbc
https://github.com/llvm/llvm-project/commit/c236dbc343b497c11790adc61cf4e041aeb42dbc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[Vectorize] Simplify code with MapVector::operator[] (NFC) (#115592)
Commit: 0ac4821b718dd14e80d3856efa532d52df6878bb
https://github.com/llvm/llvm-project/commit/0ac4821b718dd14e80d3856efa532d52df6878bb
Author: Javed Absar <106147771+javedabsar1 at users.noreply.github.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
Log Message:
-----------
[mlir][linalg] unfold projected permutation. (#114704)
Patterns to decompose the input operand(s) of a linalg.generic that has
a projected permutation` affine-map -- i.e. effectively a folded `transpose`,
`broadcast`, or a mixture of two -- into explicit transpose and broadcast.
This is useful for instance when trying to recognize named ops.
email: quic_mabsar at quicinc.com
Commit: 10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
https://github.com/llvm/llvm-project/commit/10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
Log Message:
-----------
[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: 38b0e1c939e818564019bb5bff95a0f1abbf9d19
https://github.com/llvm/llvm-project/commit/38b0e1c939e818564019bb5bff95a0f1abbf9d19
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Add legalizer-info-validation test. NFC
Based on the same test from AArch64. I used a reasonable superset
ISA string to get the most coverage. Might be worth adding more
RUN lines in the future.
Commit: 08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
https://github.com/llvm/llvm-project/commit/08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
Log Message:
-----------
Fix mistakes in #113532 (#115631)
Found during review #115151
Commit: d6e65a66095cc3c93ea78669bc41d0885780e8ea
https://github.com/llvm/llvm-project/commit/d6e65a66095cc3c93ea78669bc41d0885780e8ea
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
Fix a warning. [-Wunused-but-set-variable]
Commit: 3cdd86bb476bb90e535552fe86ba5f9d15f33d37
https://github.com/llvm/llvm-project/commit/3cdd86bb476bb90e535552fe86ba5f9d15f33d37
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Make GetMinMaxCost support FixedVectorType when REVEC is enabled. (#115417)
Commit: 639cafd05f5559c8fed92d58705dec817f876e23
https://github.com/llvm/llvm-project/commit/639cafd05f5559c8fed92d58705dec817f876e23
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Use boolean predicated legalization action methods to remove a custom lambda. (#115628)
Commit: f344367f583538746b13a5560bcdedacbd295ee7
https://github.com/llvm/llvm-project/commit/f344367f583538746b13a5560bcdedacbd295ee7
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/test/ELF/aarch64-feature-pac.s
Log Message:
-----------
[PAC][lld] Test warning emitted for non-PAuth-marked files with `-z pac-plt` (#112958)
b6162622c054f changed semantics of `-z pac-plt` initially introduced in
e208208a3132c, so, the following comment from test/ELF/aarch64-feature-pac.s
is no longer true:
> There are no warnings in this case as the choice to use PAC in PLT entries
> is orthogonal to the choice of using PAC in relocatable objects. The
> presence of the PAC .note.gnu.property is an indication of preference by
> the relocatable object.
This patch updates the test so we ensure a warning is emitted for an
input file when `-z pac-plt` is passed but the file does not have
GNU_PROPERTY_AARCH64_FEATURE_1_PAC set in GNU_PROPERTY_AARCH64_FEATURE_1_AND
property.
Commit: e4c14190bb097162e15cd5822b3de97ea7bac0d6
https://github.com/llvm/llvm-project/commit/e4c14190bb097162e15cd5822b3de97ea7bac0d6
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
M mlir/test/Analysis/test-dominance.mlir
M mlir/test/lib/IR/TestDominance.cpp
Log Message:
-----------
[mlir][IR] `DominanceInfo`: Fix inconsistency in proper block/op dominance (#115413)
An operation is considered to properly dominate itself in a graph
region. That's because there is no concept of "dominance" in a graph
region. (`dominates` returns "true" for all pairs of ops in the same
block. It makes sense to do the same for `properlyDominates`.)
Previously, a block was *not* considered to dominate itself in a graph
region. This commit fixes this asymmetry between ops and blocks: both
are now properly dominating themselves in a graph region.
Commit: e1495283cf74590fbdeb6d46ad815b4d10b1902f
https://github.com/llvm/llvm-project/commit/e1495283cf74590fbdeb6d46ad815b4d10b1902f
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/test/Driver/riscv-profiles.c
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.
We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024
So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.
Commit: 59770a43826f19ed2a735b1e461a43c63bd456bf
https://github.com/llvm/llvm-project/commit/59770a43826f19ed2a735b1e461a43c63bd456bf
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
Log Message:
-----------
[NFC] Correct imprecise file location in the comment. (#115630)
Commit: 4edd711b4d7ec60117bf77ab79491dba8cf3bb76
https://github.com/llvm/llvm-project/commit/4edd711b4d7ec60117bf77ab79491dba8cf3bb76
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor prefetch intrinsics (#115527)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.prefetch.1D -> 5D variants, supporting both Tile
and Im2Col modes. These intrinsics optionally support cache_hints as
indicated by the boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in cp-async-bulk-tensor-prefetch.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d822c099eeacc69f6bf834a6373a41d0c9f84a3e
https://github.com/llvm/llvm-project/commit/d822c099eeacc69f6bf834a6373a41d0c9f84a3e
Author: Douglas <8796590+dgg5503 at users.noreply.github.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[JITLink] Use `rsplit` on `-sectcreate` argument in llvm-jitlink (#115511)
This accounts for cases where the file path may contain an `@` symbol.
In such cases, the split occurs too early causing argument parsing to
fail.
Commit: 27bf45aa36386136db179c494358670a994a98a5
https://github.com/llvm/llvm-project/commit/27bf45aa36386136db179c494358670a994a98a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
Log Message:
-----------
[InstCombine] Fix poison safety of folding shufflevector into select (#115483)
We are allowed to fold shufflevector into select iff the condition is
guaranteed not to be poison or the RHS is a poison.
Alive2: https://alive2.llvm.org/ce/z/28zEWR
Closes https://github.com/llvm/llvm-project/issues/115465.
Commit: a5a1612deb7af713835b5c8cf22105c5699bc62d
https://github.com/llvm/llvm-project/commit/a5a1612deb7af713835b5c8cf22105c5699bc62d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
Log Message:
-----------
[VPlan] Consistently use DEBUG_TYPE loop-vectorize.
This ensures debug messages in VPlan.cpp are included in the commonly
used -debug-only=loop-vectorize.
Commit: 81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
https://github.com/llvm/llvm-project/commit/81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
Log Message:
-----------
[ORC] Move some typedefs from Core.h to a new header, CoreContainers.h. NFC.
This is a first step towards breaking up Core.h
Commit: 3d2849bd151f415b59044736e069c7605339b8e2
https://github.com/llvm/llvm-project/commit/3d2849bd151f415b59044736e069c7605339b8e2
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Move MaterializationUnit from Core.h into its own header. NFC.
Continuing Core.h clean-up.
Commit: 7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
https://github.com/llvm/llvm-project/commit/7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Switch to C++17 nested namespaces. NFC.
Commit: ac30a0f349c960184c0165adcd87baecfc48a1af
https://github.com/llvm/llvm-project/commit/ac30a0f349c960184c0165adcd87baecfc48a1af
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
Log Message:
-----------
[PAC][lld] Do not emit warnings for `-z pac-plt` with valid PAuth core info (#112959)
When PAuth core info is present and (platform,version) is not (0,0),
treat input files as pac-enabled and do not emit a warning with
`-z pac-plt` passed.
Commit: 2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
https://github.com/llvm/llvm-project/commit/2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/any
M libcxx/include/module.modulemap
M libcxx/include/type_traits
M libcxx/include/variant
Log Message:
-----------
[libc++][NFC] Merge add_{const, cv, volatile}.h into a single header (#115610)
There isn't much benefit in having granular headers for only a few
simple lines of code.
Commit: ad2d313f7455fe27896db8df9ea9aadd60b53436
https://github.com/llvm/llvm-project/commit/ad2d313f7455fe27896db8df9ea9aadd60b53436
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2c10664afafc
Commit: 7c13477351046c115ad86e047f3f7346bb925b19
https://github.com/llvm/llvm-project/commit/7c13477351046c115ad86e047f3f7346bb925b19
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Log Message:
-----------
[X86] Delete unused X86setcc_commute node (NFC) (#115650)
The last use was removed by 87aa59a0.
Commit: 99f1019f596f745c720e97137bcadb239c573e3e
https://github.com/llvm/llvm-project/commit/99f1019f596f745c720e97137bcadb239c573e3e
Author: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/docs/SafeBuffers.rst
Log Message:
-----------
[NFC] Trivial doc fixup in SafeBuffers.rst
Commit: 1d6d073fbbaebbde6891501fe20f02a0ea345131
https://github.com/llvm/llvm-project/commit/1d6d073fbbaebbde6891501fe20f02a0ea345131
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
Log Message:
-----------
[AArch64] Remove FeatureUseScalarIncVL
FeatureUseScalarIncVL is a tuning feature, used to control whether addvl or
add+cnt is used. It was previously added as a dependency for FeatureSVE2, an
architecture feature but this can be seen as a layering violation. The main
disadvantage is that -use-scalar-inc-vl cannot be used without disabling sve2
and all dependant features.
This patch now replaces that with an option that if unset defaults to hasSVE ||
hasSME, but is otherwise overriden by the option. The hope is that no cpus will
rely on the tuning feature (or we can readdit if needed.
Commit: c8f33738a5a801b5bc083ae9b2ced39ef1b12980
https://github.com/llvm/llvm-project/commit/c8f33738a5a801b5bc083ae9b2ced39ef1b12980
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64] Rewrite arm64-ext.ll test and cleanup. NFC
Commit: 91a48e06463b23679907e151bdfec3e6093e9f16
https://github.com/llvm/llvm-project/commit/91a48e06463b23679907e151bdfec3e6093e9f16
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64][GlobalISel] Implicitly truncate APInt in matchExt combine.
The APInt using FirstRealElt + 1 is intended to match the next element, which
might overflow the size of MaskBits. This prevents a new assert in APInt from
triggering.
Commit: 5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
https://github.com/llvm/llvm-project/commit/5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115626)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: a44ee8ec1c87be76e147d97f3be90a7e8630421b
https://github.com/llvm/llvm-project/commit/a44ee8ec1c87be76e147d97f3be90a7e8630421b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115633)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 2c0f463b2546a98e6215f3a85940ab9c0971d2aa
https://github.com/llvm/llvm-project/commit/2c0f463b2546a98e6215f3a85940ab9c0971d2aa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[Vectorize] Simplify code with DenseMap::operator[] (NFC) (#115635)
Commit: 1e25c921d523151e6ed2ffe86029ea2e2b267a6c
https://github.com/llvm/llvm-project/commit/1e25c921d523151e6ed2ffe86029ea2e2b267a6c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Log Message:
-----------
[AArch64/GISel] Remove unused includes (NFC) (#115636)
Identified with misc-include-cleaner.
Commit: 15ce2e183fb801ff418eb1347a9d5893e5665782
https://github.com/llvm/llvm-project/commit/15ce2e183fb801ff418eb1347a9d5893e5665782
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/source/Commands/CommandObjectMultiword.cpp
Log Message:
-----------
[lldb] Use heterogenous lookups with std::map (NFC) (#115590) (#115634)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: ff0698b258eba9afd888159358c7369c3f85e9ae
https://github.com/llvm/llvm-project/commit/ff0698b258eba9afd888159358c7369c3f85e9ae
Author: Will <william.fedele1 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix examples for float to int saturating intrinsics (#115629)
As per the [LangRef:Simple
Constants](https://llvm.org/docs/LangRef.html#simple-constants), exact
decimal values of floating-point constants are required. For instance,
23.9 is a repeating decimal in binary and results in the reported error.
https://godbolt.org/z/1h7ETPnf6
Fixes #113529.
Commit: 028ea71fdda0c02cd11421cd1d26bec6f378666e
https://github.com/llvm/llvm-project/commit/028ea71fdda0c02cd11421cd1d26bec6f378666e
Author: Julian Schmidt <git.julian.schmidt at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
Log Message:
-----------
[clang-tidy] fix insertion location for function pointers in cppcoreguidelines-init-variables (#112091)
Previously, the insertion location for the `= nullptr` fix would be
after the variable name. However, if the variable is of type function
pointer that is not an alias, then the insertion would happen inside the
type specification: `void (*a1)(void*);` -> `void (*a1 =
nullptr)(void*);`.
With this change, the insertion location will be at the next
'terminator'. That is, at the next `,` or `;`, as that will finish the
current declaration: `void (a1)(void*) = nullptr;`.
Fixes #112089
Commit: 7111d031f19ce7d523796b4812d6afcb2958b025
https://github.com/llvm/llvm-project/commit/7111d031f19ce7d523796b4812d6afcb2958b025
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
Log Message:
-----------
[Xtensa] Fix Clang -Wundefined-bool-conversion after #113450
Commit: 3006dddfe091bcb95924d72dddbb84f73186a344
https://github.com/llvm/llvm-project/commit/3006dddfe091bcb95924d72dddbb84f73186a344
Author: Janis Heims <janis.heims at undertheprinter.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/test/CodeGen/M68k/multiple-return.ll
Log Message:
-----------
[M68k] fix call frame destruction elimination when returning structs (#107579)
Fixes #106213.
This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.
Commit: dc11c0601577afb8f67513d041ee25dabe3555b9
https://github.com/llvm/llvm-project/commit/dc11c0601577afb8f67513d041ee25dabe3555b9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
Log Message:
-----------
[ORC] Move absoluteSymbols from Core.h to new AbsoluteSymbols.h header. NFC.
Continuing Core.h clean-up.
If you see any errors about a missing absoluteSymbols function you need to
include the new AbsoluteSymbols.h header.
Commit: 0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
https://github.com/llvm/llvm-project/commit/0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port dc11c0601577
Commit: 3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
https://github.com/llvm/llvm-project/commit/3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
Author: Doug Wyatt <doug at sonosphere.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
Log Message:
-----------
[Clang] SemaFunctionEffects: When verifying a function, ignore any conditional noexcept expression. (#115342)
---------
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
Commit: e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
https://github.com/llvm/llvm-project/commit/e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (#115436)
This is a follow-up patch for
https://github.com/llvm/llvm-project/pull/101811.
That we can remove the type checking for fp16 from SemaRISCV.cpp.
Fixes: https://github.com/llvm/llvm-project/issues/101621 and
https://github.com/llvm/llvm-project/issues/94306
Commit: 595f3e925adaffcb10d40e2e704c67556e9afb18
https://github.com/llvm/llvm-project/commit/595f3e925adaffcb10d40e2e704c67556e9afb18
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
Log Message:
-----------
[mlir][IR][NFC] `PostDominanceInfo`: Mark all functions as `const` (#115597)
Same as `DominanceInfo`, all functions should be `const`.
Commit: 5082acce4fd3646d5760c02b2c21d9cd2a1d7130
https://github.com/llvm/llvm-project/commit/5082acce4fd3646d5760c02b2c21d9cd2a1d7130
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Add custom libc++ workaround for CMake < 3.26
The INSTALL_BYPRODUCTS ExternalProject_Add() argument was only added in
CMake 3.26 and the current minimum is 3.20. Work around this by using an
explicit ExternalProject_Add_Step() call for the install step with a
BYPRODUCTS argument. We can't keep using the `install` name here since that
is reserved by the CMake implementation and results in errors when used.
This commit should be reverted once LLVM depends on CMake 3.26.
Pull Request: https://github.com/llvm/llvm-project/pull/115677
Commit: 5ca082cdfed2e0d3d9499d2c70d8a38dacd2539e
https://github.com/llvm/llvm-project/commit/5ca082cdfed2e0d3d9499d2c70d8a38dacd2539e
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix evl type on float VP reduction intrinsics (#115421)
Looks like a search-and-replace typo
Commit: b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
https://github.com/llvm/llvm-project/commit/b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
Log Message:
-----------
[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)
This PR enables scalable loop vectorization for f16 with zvfhmin and
bf16 with zvfbfmin.
Enabling this was dependent on filling out the gaps for scalable
zvfhmin/zvfbfmin codegen, but everything that the loop vectorizer might
emit should now be handled.
It does this by marking f16 and bf16 as legal in
`isLegalElementTypeForRVV`. There are a few users of
`isLegalElementTypeForRVV` that have already been enabled in other PRs:
- `isLegalStridedLoadStore` #115264
- `isLegalInterleavedAccessType` #115257
- `isLegalMaskedLoadStore` #115145
- `isLegalMaskedGatherScatter` #114945
The remaining user is `isLegalToVectorizeReduction`. We can't promote
f16/bf16 reductions to f32 so we need to disable them for scalable
vectors. The cost model actually marks these as invalid, but for
out-of-tree reductions `ComputeReductionResult` doesn't get costed and
it will end up emitting a reduction intrinsic regardless, so we still
need to mark them as illegal. We might be able to remove this
restriction later for fmax and fmin reductions.
Commit: a912c81f651109c677dcfdf2b1173a78e853a19d
https://github.com/llvm/llvm-project/commit/a912c81f651109c677dcfdf2b1173a78e853a19d
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Core/LVLocation.cpp
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
Log Message:
-----------
[llvm-debuginfo-analyzer] Fix crash with thread local storage. (#113904)
The DW_OP_GNU_push_tls_address, DW_OP_form_tls_address DWARF
location forms generated for thread local storage variables, caused a
crash in the DWARFReader, due to incorrect number of operands.
Commit: ffc7feadece139c88f0e6930f16bfa9293747adc
https://github.com/llvm/llvm-project/commit/ffc7feadece139c88f0e6930f16bfa9293747adc
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
Log Message:
-----------
[mlir][mesh] Handling changed halo region sizes during spmdization (#114238)
* Changed `MeshSharding::sharded_dims_sizes` from representing sizes per
shard to offsets to origin per shard.
- Local shard size are now a simple subtraction
- Offsets are now readily available without a reduction operation
- Enables constant value/shape propagation through standard
canonicalization
- Renamed to `sharded_dims_offsets` accordingly.
* First spmdization pattern for halo regions.
- Triggers when source and destination shardings differ only in their
halo sizes
- Copies local data from source into a new tensor and calls update_halo
- Supports arbitrary mesh dimensions (unlike the other patterns which
work on 1d meshes only)
* `UpdateHaloOp` implements `DestinationStyleOpInterface` and accepts
tensors and memrefs
- also accepts target and source halo sizes; both are required for
proper lowering
* minor refactoring for testing partial MeshSharding equality
* Canonicalization for ShardingOp folding constant values into
respective `static_*` attributes
Commit: 2eaf50716abae064804b9f9d27e157a98c83be2b
https://github.com/llvm/llvm-project/commit/2eaf50716abae064804b9f9d27e157a98c83be2b
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/jr-without-ra.ll
Log Message:
-----------
[LoongArch] Precommit test for avoid indirect branch jumps through ra. NFC
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/115423
Commit: 49caeb4da0902a49541a5a5cba79b48068d350d0
https://github.com/llvm/llvm-project/commit/49caeb4da0902a49541a5a5cba79b48068d350d0
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/stdalign.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/AST/ast-print-openacc-loop-construct.cpp
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
M clang/test/C/C2y/n3344.c
A clang/test/C/C2y/n3346.c
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/CodeGenHIP/default-attributes.hip
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/Driver/XRay/xray-shared.cpp
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-profiles.c
M clang/test/Driver/x86-target-features.c
M clang/test/Misc/warning-flags.c
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-cpu-supports.c
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/attr-target-clones-aarch64.c
M clang/test/Sema/declspec.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
M clang/www/c_status.html
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/runtime/CUDA/kernel.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/log1p.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/log1p_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libcxx/docs/UserDocumentation.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/any
M libcxx/include/module.modulemap
M libcxx/include/type_traits
M libcxx/include/variant
M libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/PDB.cpp
M lld/COFF/Writer.cpp
M lld/ELF/Driver.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
A lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/cfguard-off-instrumented.s
A lld/test/COFF/lto-arm64ec.ll
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/source/Commands/CommandObjectMultiword.cpp
M lldb/test/API/commands/target/basic/TestTargetCommand.py
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVLocation.cpp
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
A llvm/test/CodeGen/X86/lrshrink-debug.ll
A llvm/test/CodeGen/X86/optnone.mir
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/vector-sext.ll
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/test/MC/AArch64/spe.s
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
M llvm/test/Other/new-pm-pgo-O0.ll
M llvm/test/ThinLTO/X86/memprof-icp.ll
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.h
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/include/mlir/IR/Dominance.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/Dominance.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Analysis/test-dominance.mlir
M mlir/test/CMakeLists.txt
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/Dialect/Vector/invalid.mlir
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
M mlir/test/lib/IR/TestDominance.cpp
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5-bogner
[skip ci]
Commit: 2e43ace08226f62481e05d0f7bce737b7b036d76
https://github.com/llvm/llvm-project/commit/2e43ace08226f62481e05d0f7bce737b7b036d76
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/stdalign.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/AST/ast-print-openacc-loop-construct.cpp
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
M clang/test/C/C2y/n3344.c
A clang/test/C/C2y/n3346.c
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/CodeGenHIP/default-attributes.hip
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/Driver/XRay/xray-shared.cpp
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-profiles.c
M clang/test/Driver/x86-target-features.c
M clang/test/Misc/warning-flags.c
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-cpu-supports.c
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/attr-target-clones-aarch64.c
M clang/test/Sema/declspec.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
M clang/www/c_status.html
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/runtime/CUDA/kernel.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/log1p.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/log1p_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libcxx/docs/UserDocumentation.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/any
M libcxx/include/module.modulemap
M libcxx/include/type_traits
M libcxx/include/variant
M libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/PDB.cpp
M lld/COFF/Writer.cpp
M lld/ELF/Driver.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
A lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/cfguard-off-instrumented.s
A lld/test/COFF/lto-arm64ec.ll
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/source/Commands/CommandObjectMultiword.cpp
M lldb/test/API/commands/target/basic/TestTargetCommand.py
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVLocation.cpp
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
A llvm/test/CodeGen/X86/lrshrink-debug.ll
A llvm/test/CodeGen/X86/optnone.mir
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/vector-sext.ll
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/test/MC/AArch64/spe.s
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
M llvm/test/Other/new-pm-pgo-O0.ll
M llvm/test/ThinLTO/X86/memprof-icp.ll
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.h
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/include/mlir/IR/Dominance.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/Dominance.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Analysis/test-dominance.mlir
M mlir/test/CMakeLists.txt
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/Dialect/Vector/invalid.mlir
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
M mlir/test/lib/IR/TestDominance.cpp
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
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Compare: https://github.com/llvm/llvm-project/compare/f86330d4615c...2e43ace08226
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