[all-commits] [llvm/llvm-project] b2e2d8: [RISCV] Enable scalable loop vectorization for zvf...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
      https://github.com/llvm/llvm-project/commit/b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-11-11 (Mon, 11 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll

  Log Message:
  -----------
  [RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)

This PR enables scalable loop vectorization for f16 with zvfhmin and
bf16 with zvfbfmin.

Enabling this was dependent on filling out the gaps for scalable
zvfhmin/zvfbfmin codegen, but everything that the loop vectorizer might
emit should now be handled.

It does this by marking f16 and bf16 as legal in
`isLegalElementTypeForRVV`. There are a few users of
`isLegalElementTypeForRVV` that have already been enabled in other PRs:

- `isLegalStridedLoadStore` #115264
- `isLegalInterleavedAccessType` #115257
- `isLegalMaskedLoadStore` #115145
- `isLegalMaskedGatherScatter` #114945

The remaining user is `isLegalToVectorizeReduction`. We can't promote
f16/bf16 reductions to f32 so we need to disable them for scalable
vectors. The cost model actually marks these as invalid, but for
out-of-tree reductions `ComputeReductionResult` doesn't get costed and
it will end up emitting a reduction intrinsic regardless, so we still
need to mark them as illegal. We might be able to remove this
restriction later for fmax and fmin reductions.



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