[all-commits] [llvm/llvm-project] ce067c: AMDGPU: Rename test file
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Sun Nov 10 20:31:43 PST 2024
Branch: refs/heads/users/arichardson/spr/reapply-runtimes-allow-building-against-an-installed-llvm-tree
Home: https://github.com/llvm/llvm-project
Commit: ce067c5a3b96e009964dc60d6b6a0f4b33c345c7
https://github.com/llvm/llvm-project/commit/ce067c5a3b96e009964dc60d6b6a0f4b33c345c7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
R llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
Log Message:
-----------
AMDGPU: Rename test file
Commit: 592c0fe55f6d9a811028b5f3507be91458ab2713
https://github.com/llvm/llvm-project/commit/592c0fe55f6d9a811028b5f3507be91458ab2713
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Evaluate/fold-real.cpp
M flang/test/Evaluate/errors01.f90
Log Message:
-----------
[flang] Tweak a SCALE/IEEE_SCALB folding overflow warning message (#114994)
Commit: 7c3fdcc27603cd2d6b01fa7b057b3099da75bc8d
https://github.com/llvm/llvm-project/commit/7c3fdcc27603cd2d6b01fa7b057b3099da75bc8d
Author: Artem Belevich <tra at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/CodeGenCUDA/Inputs/cuda.h
A clang/test/CodeGenCUDA/grid-constant.cu
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/SemaCUDA/Inputs/cuda.h
A clang/test/SemaCUDA/grid-constant.cu
Log Message:
-----------
[CUDA] Add support for __grid_constant__ attribute (#114589)
LLVM support for the attribute has been implemented already, so it just
plumbs it through to the CUDA front-end.
One notable difference from NVCC is that the attribute can be used
regardless of the targeted GPU. On the older GPUs it will just be
ignored. The attribute is a performance hint, and does not warrant a
hard error if compiler can't benefit from it on a particular GPU
variant.
Commit: a993dfcdbf64ef7a8bd7e5ec4d97287b650d4f50
https://github.com/llvm/llvm-project/commit/a993dfcdbf64ef7a8bd7e5ec4d97287b650d4f50
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
A flang/test/Transforms/debug-assumed-rank-array.fir
Log Message:
-----------
[flang][debug] Support assumed-rank arrays. (#114404)
The assumed-rank array are represented by DIGenericSubrange in debug
metadata. We have to provide 2 things.
1. Expression to get rank value at the runtime from descriptor.
2. Assuming the dimension number for which we want the array information
has been put on the DWARF expression stack, expressions which will
extract the lowerBound, count and stride information from the descriptor
for the said dimension.
With this patch in place, this is how I see an assumed_rank variable
being evaluated by GDB.
```
function mean(x) result(y)
integer, intent(in) :: x(..)
...
end
program main
use mod
implicit none
integer :: x1,xvec(3),xmat(3,3),xtens(3,3,3)
x1 = 5
xvec = 6
xmat = 7
xtens = 8
print *,mean(xvec), mean(xmat), mean(xtens), mean(x1)
end program main
(gdb) p x
$1 = (6, 6, 6)
(gdb) p x
$2 = ((7, 7, 7) (7, 7, 7) (7, 7, 7))
(gdb) p x
$3 = (((8, 8, 8) (8, 8, 8) (8, 8, 8)) ((8, 8, 8) (8, 8, 8) (8, 8, 8)) ((8, 8, 8) (8, 8, 8) (8, 8, 8)))
(gdb) p x
$4 = 5
```
Commit: 9b9369e0bb0131ba0336d9adb4ef098b6dafc7f4
https://github.com/llvm/llvm-project/commit/9b9369e0bb0131ba0336d9adb4ef098b6dafc7f4
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir][tensor] Improve `FoldTensorCastProducerOp` (dynamic shapes) (#114559)
Currently, `FoldTensorCastProducerOp` incorrectly folds the following:
```mlir
%pack = tensor.pack %src
padding_value(%pad : i32)
inner_dims_pos = [0, 1]
inner_tiles = [%c8, 1]
into %cast : tensor<7x?xi32> -> tensor<1x1x?x1xi32>
%res = tensor.cast %pack : tensor<1x1x?x1xi32> to tensor<1x1x8x1xi32>
```
as (note the static trailing dim in the result and dynamic tile
dimension that corresponds to that):
```mlir
%res = tensor.pack %src
padding_value(%pad : i32)
inner_dims_pos = [0, 1]
inner_tiles = [%c8, 1]
into %cast : tensor<7x?xi32> -> tensor<1x1x8x1xi32>
```
This triggers an Op verification failure and is due to the fact that the
folder does not update the inner tile sizes in the pack Op. This PR
addresses that.
Note, supporting other Ops with size-like attributes is left as a TODO.
Commit: d02d9ce314f823181430e9f21c89806f9227c95f
https://github.com/llvm/llvm-project/commit/d02d9ce314f823181430e9f21c89806f9227c95f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/Tensor/IR/TensorOps.cpp:4781:17: error: unused
variable 'tileSize' [-Werror,-Wunused-variable]
Commit: a33d42ad5f916f5b782076ca84fe565589079c6f
https://github.com/llvm/llvm-project/commit/a33d42ad5f916f5b782076ca84fe565589079c6f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Log Message:
-----------
[gn build] Port ff5551cdb07f
Commit: c695a32576525b047f92b90de71eb707c152e29c
https://github.com/llvm/llvm-project/commit/c695a32576525b047f92b90de71eb707c152e29c
Author: David Olsen <dolsen at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
A clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CIRGenAction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CIR/hello.c
Log Message:
-----------
[CIR] Call code gen; create empty cir.func op (#113483)
Finish hooking up ClangIR code gen into the Clang control flow,
initializing enough that basic code gen is possible.
Add an almost empty `cir.func` op to the ClangIR dialect. Currently the
only property of the function is its name. Add the code necessary to
code gen a cir.func op.
Create essentially empty files
clang/lib/CIR/Dialect/IR/{CIRAttrs.cpp,CIRTypes.cpp}. These will be
filled in later as attributes and types are defined in the ClangIR
dialect.
(Part of upstreaming the ClangIR incubator project into LLVM.)
Commit: 803f957e87e4083f6d61c8991171eeeaf0e6bd61
https://github.com/llvm/llvm-project/commit/803f957e87e4083f6d61c8991171eeeaf0e6bd61
Author: jimingham <jingham at apple.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M lldb/source/Symbol/CompileUnit.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpoinsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/common.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/main.cpp
Log Message:
-----------
Fix a thinko in the CallSite handling code: (#114896)
I have to check for the sc list size being changed by the call-site
search, not just that it had more than one element.
Added a test for multiple CU's with the same name in a given module,
which would have caught this mistake.
We were also doing all the work to find call sites when the found decl
and specified decl's only difference was a column, but the incoming
specification hadn't specified a column (column number == 0).
Commit: 17d956588a2cc508acf98574f913eaef6d0e1af3
https://github.com/llvm/llvm-project/commit/17d956588a2cc508acf98574f913eaef6d0e1af3
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/include/sanitizer/tsan_interface_atomic.h
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
Reapply "[tsan] Don't use `enum __tsan_memory_order` in tsan interface"" (#115034)
In C++ it's UB to use undeclared values as enum.
And there is support __ATOMIC_HLE_ACQUIRE and
__ATOMIC_HLE_RELEASE need such values.
So use `int` in TSAN interface, and mask out
irrelevant bits and cast to enum ASAP.
`ThreadSanitizer.cpp` already declare morder parameterd
in these functions as `i32`.
This may looks like a slight change, as we
previously didn't mask out additional bits for `fmo`,
and `NoTsanAtomic` call. But from implementation
it's clear that they are expecting exact enum.
Reverts llvm/llvm-project#115032
Reapply llvm/llvm-project#114724
Commit: db69d6939a93d1e401abe6bfe114e55b69297975
https://github.com/llvm/llvm-project/commit/db69d6939a93d1e401abe6bfe114e55b69297975
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/memory.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Support data transfer from descriptor to a pointer (#115023)
Data transfer from a variable with a descriptor to a pointer. We create
a descriptor for the pointer so we can use the flang runtime to perform
the transfer. The Assign function handles all corner cases. We add a new
entry points `CUFDataTransferDescDescNoRealloc` to avoid reallocation
since the variable on the LHS is not an allocatable.
Commit: e566ae8812af77d4ebfd14f4ebe6055a1f71cc02
https://github.com/llvm/llvm-project/commit/e566ae8812af77d4ebfd14f4ebe6055a1f71cc02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 support for G_ABS on RV64.
I plan to remove s32 as a legal type to match SelectionDAG
and to remove i32 from the GPR regclass on RV64.
Commit: 8b659736f7393314a797b6cf2fa346316a624ecb
https://github.com/llvm/llvm-project/commit/8b659736f7393314a797b6cf2fa346316a624ecb
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
Log Message:
-----------
[SystemZ] Make lit test more specific (#115050)
The lit test fmuladd-soft-float.ll only specifies s390x as platform,
but the test is Linux specific, causing problems when run on z/OS.
This change updates the triple to fix this.
Commit: db1882e2484013066139f0b3f77d968d84a79158
https://github.com/llvm/llvm-project/commit/db1882e2484013066139f0b3f77d968d84a79158
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
M compiler-rt/lib/xray/xray_interface_internal.h
A compiler-rt/lib/xray/xray_s390x.cpp
A compiler-rt/lib/xray/xray_trampoline_s390x.S
M compiler-rt/lib/xray/xray_tsc.h
Log Message:
-----------
[SystemZ][XRay] XRay runtime support for SystemZ (#113252)
Adds the runtime support routines for XRay on SystemZ. Only function
entry/exit is implemented.
Commit: 4a37799a489d80e505e3e20722570c47673476be
https://github.com/llvm/llvm-project/commit/4a37799a489d80e505e3e20722570c47673476be
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSubtarget.h
A llvm/test/CodeGen/SystemZ/xray.ll
Log Message:
-----------
[SystemZ][XRay] Implement XRay instrumentation for SystemZ (#113253)
Expands pseudo instructions PATCHABLE_FUNCTION_ENTER and PATCHABLE_RET
into a small instruction sequence which calls into the XRay library.
Commit: 0c60573d1c2d19133d84da092b240f32e0574be5
https://github.com/llvm/llvm-project/commit/0c60573d1c2d19133d84da092b240f32e0574be5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
clang/AMDGPU: Emit grid size builtins with range metadata (#113038)
These cannot be 0.
Commit: 0b40f979298a2e7d4c3da7c067fc9747d0f93653
https://github.com/llvm/llvm-project/commit/0b40f979298a2e7d4c3da7c067fc9747d0f93653
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
R llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
Log Message:
-----------
AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)
0 does not make sense as a value for this to be, much less the default.
Also stop emitting each individual field if it is the default, rather than
if any element was the default. Also fix the name of the test since it didn't
exactly match the real attribute name.
Commit: 0428f2cb5a91cc93897252c9dc4883efea3dbd9a
https://github.com/llvm/llvm-project/commit/0428f2cb5a91cc93897252c9dc4883efea3dbd9a
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M clang/test/Driver/XRay/xray-mode-flags.cpp
Log Message:
-----------
[SystemZ][XRay] Enable XRay for SystemZ in clang (#113254)
With the support for xray for SystemZ in place, the option can now be
enabled in clang.
Commit: e8644e3b474136da43344a5afeeae63268f980e1
https://github.com/llvm/llvm-project/commit/e8644e3b474136da43344a5afeeae63268f980e1
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
Log Message:
-----------
[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)
Some old "t16" VOP2 instructions are actually in fake16 format. Correct
and update test file
Commit: fbbd8b0741586794721639715d1d974db56f83ac
https://github.com/llvm/llvm-project/commit/fbbd8b0741586794721639715d1d974db56f83ac
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Semantics/rewrite-parse-tree.cpp
A flang/test/Semantics/rewrite03.f90
Log Message:
-----------
[flang] Fix rewriting of misparsed statement functions (#112934)
Fortran's syntax is ambiguous for some assignment statements (to array
elements or to the targets of pointers returned by functions) that
appear as the first executable statements in a subprogram or BLOCK
construct. Is A(I)=X a statement function definition at the end of the
specification part, or ar array element assignment statement, or an
assignment to a pointer returned by a function named A?
Since f18 builds a parse tree for the entire source file before
beginning any semantic analysis, we can't tell which is which until
after name resolution, at which point the symbol table has been built.
So we have to walk the parse tree and rewrite some misparsed statement
function definitions that really were assignment statements.
There's a bug in that code, though, due to the fact that the
implementation used state in the parse tree walker to hold a list of
misparsed statement function definitions extracted from one
specification part to be reinserted at the beginning of the next
execution part that is visited; it didn't work for misparsed cases BLOCK
constructs. Their parse tree nodes encapsulate a parser::Block, not an
instance of the wrapper class parser::ExecutionPart. So misparsed
statement functions in BLOCK constructs were being rewritten into
assignment statement that were inserted at the beginning of the
executable part of the following subprogram, if and wherever one
happened to occur. This led to crashes in lowering and much
astonishment.
A simple fix would have been to adjust the rewriting code to always
insert the list at the next visited parser::Block, since
parser::ExecutionPart is just a wrapper around Block anyway; but this
patch goes further to do the "right thing", which is a restructuring of
the rewrite that avoids the use of state and any assumptions about parse
tree walking visitation order.
Fixes https://github.com/llvm/llvm-project/issues/112549.
Commit: 07e053fb95e131244dafab04aae84650de383664
https://github.com/llvm/llvm-project/commit/07e053fb95e131244dafab04aae84650de383664
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/runtime/assign.cpp
Log Message:
-----------
[flang][runtime] Fix finalization case in assignment (#113611)
There were two bugs in derived type array assignment processing that
caused finalization to fail to occur for a test case. The first bug was
an off-by-one error in address overlap testing that caused a false
positive result for the test, whose left-hand side's allocatable's
descriptor was immediately adjacent in memory to the right-hand side's
array's data.
The second bug was that in such overlap cases (even when legitimate)
finalization would fail due to the LHS's descriptor having been copied
to a temporary for deferred deallocation and then nullified.
This patch corrects the overlap analysis for this test, and also
properly finalizes the LHS when overlap does exist. Some nearby dead
code was removed to avoid future confusion.
Fixes https://github.com/llvm/llvm-project/issues/113375.
Commit: 850d42fb145c636a3b56a7616c3e3c5c188c1916
https://github.com/llvm/llvm-project/commit/850d42fb145c636a3b56a7616c3e3c5c188c1916
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Parser/token-sequence.h
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/token-sequence.cpp
A flang/test/Preprocessing/defined-in-macro.F90
Log Message:
-----------
[flang] Handle "defined" in macro expansions (#114844)
The preprocessor implements "defined(X)" and "defined X" in if/elif
directive expressions in such a way that they only work at the top
level, not when they appear in macro expansions. Fix that, which is a
little tricky due to the need to detect the "defined" keyword before
applying any macro expansion to its argument, and add a bunch of tests.
Fixes https://github.com/llvm/llvm-project/issues/114064.
Commit: 97982a8c605fac7c86d02e641a6cd7898b3ca343
https://github.com/llvm/llvm-project/commit/97982a8c605fac7c86d02e641a6cd7898b3ca343
Author: dlav-sc <daniil.avdeev at syntacore.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/branch-relaxation.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/kcfi-mir.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr58025.ll
M llvm/test/CodeGen/RISCV/pr58286.ll
M llvm/test/CodeGen/RISCV/pr63365.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr88365.ll
M llvm/test/CodeGen/RISCV/prolog-epilogue.ll
M llvm/test/CodeGen/RISCV/push-pop-opt-crash.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvbi.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
M llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
Log Message:
-----------
[RISCV][CFI] add function epilogue cfi information (#110810)
This patch adds CFI instructions in the function epilogue.
Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret
After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret
This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.
Commit: b8ac87f34a6f4405bf8d91339a10f188db30aa3b
https://github.com/llvm/llvm-project/commit/b8ac87f34a6f4405bf8d91339a10f188db30aa3b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/lib/AsmParser/LLLexer.cpp
A llvm/test/Assembler/c-style-comment.ll
A llvm/test/Assembler/invalid-c-style-comment0.ll
A llvm/test/Assembler/invalid-c-style-comment1.ll
A llvm/test/Assembler/invalid-c-style-comment2.ll
A llvm/test/Assembler/invalid-c-style-comment3.ll
Log Message:
-----------
[LLVM][AsmParser] Add support for C style comments (#111554)
Add support for C style comments in LLVM assembly.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 97262afa6d78bcf332f26a02834b43ac31f87f94
https://github.com/llvm/llvm-project/commit/97262afa6d78bcf332f26a02834b43ac31f87f94
Author: Eric <eric at efcs.ca>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
Allow specifying libcxx builder image. (#110303)
This change attempts to shift the libc++ builders over to new backend
infrastructure that allows running an arbitrary container for the
libc++ job.
This has been a long time in the making, and support from github
and gke is finally at the point where it's possible (hopefully).
This change should also demonstrate another important property:
No Downtime Upgrades.
If this goes well, we'll be able to test the upgrade as a part
of the PR process, and then commiting it to main should (ideally)
not break anything.
Commit: fedb9fdb98314ff0ddff065dbd6ef8b2b7e6ec96
https://github.com/llvm/llvm-project/commit/fedb9fdb98314ff0ddff065dbd6ef8b2b7e6ec96
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M libc/src/sys/socket/linux/recvmsg.cpp
Log Message:
-----------
[libc] Fix sendmsg iovec unpoisoning (#115057)
The unpoisoning for sendmsg had a typo where it would not unpoison all
of the elements in the iovec, causing msan errors. This patch fixes
that.
Commit: a353e258ba495be58263d6cc6e382e6dde298361
https://github.com/llvm/llvm-project/commit/a353e258ba495be58263d6cc6e382e6dde298361
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
M llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
M llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-3.ll
M llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
Log Message:
-----------
[LAA] Don't require Stride == 1/-1 for inbounds pointer AddRecs nowrap. (#113126)
If we have a pointer AddRec, the maximum increment is
2^(pointer-index-wdith - 1) - 1. This means that if incrementing the
AddRec wraps, the distance between the previously accessed location and
the wrapped location is > 2^(pointer-index-wdith - 1), i.e. if the GEP
for the AddRec is inbounds, this would be poison due to the object being
larger than half the pointer index type space. The poison would be
immediate UB when the memory access gets executed..
Similar reasoning can be applied for decrements.
PR: https://github.com/llvm/llvm-project/pull/113126
Commit: 823625cf1d9aba4017a486cfdd3e4b9b94c5ef49
https://github.com/llvm/llvm-project/commit/823625cf1d9aba4017a486cfdd3e4b9b94c5ef49
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[nfc][tsan] Simplify morder conversion (#115075)
All valid values should fit into a byte.
This slightly reduce generated code on x86_64.
Commit: dccb1fe879d6a949884523eab66a8a51cee93d1a
https://github.com/llvm/llvm-project/commit/dccb1fe879d6a949884523eab66a8a51cee93d1a
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s
Log Message:
-----------
[RISCV] Update latency of MUL & CPOP in SiFive P600's scheduling model (#115042)
It should be 2 cycles rather than 3 cycles.
Commit: 6d7e51de5ec46c1fcc7a7e80135f561a88a1296b
https://github.com/llvm/llvm-project/commit/6d7e51de5ec46c1fcc7a7e80135f561a88a1296b
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
Log Message:
-----------
[AMDGPU] Extend type support for update_dpp intrinsic (#114597)
We can split 64-bit DPP as a post-RA pseudo if control values are
supported, but cannot handle other types.
Commit: c1cec8c0dc5b0296f0bc86745b867ff72c0a21e3
https://github.com/llvm/llvm-project/commit/c1cec8c0dc5b0296f0bc86745b867ff72c0a21e3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
Log Message:
-----------
[SLP][NFC]Add a test with missed splat ordering for loads, NFC
Commit: ce0d085842c652620969001b9d0c12912cec2c24
https://github.com/llvm/llvm-project/commit/ce0d085842c652620969001b9d0c12912cec2c24
Author: vporpo <vporpodas at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Pass.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Query the scheduler for legality (#114616)
This patch adds the legality check of whether the candidate instructions
can be scheduled together. This uses a Scheduler object.
Commit: 5e75f294f1e2900e75f1f1e2cc4e5abe46366047
https://github.com/llvm/llvm-project/commit/5e75f294f1e2900e75f1f1e2cc4e5abe46366047
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
Log Message:
-----------
[ORC] Replace RedirectionManager::SymbolAddrMap typedef with SymbolMap. NFC.
They're the same type -- no need for a separate typedef here.
Commit: 13b5899c2904ba6b1f5223bf86679d046212da98
https://github.com/llvm/llvm-project/commit/13b5899c2904ba6b1f5223bf86679d046212da98
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/X86/pr114520.ll
Log Message:
-----------
[SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors if FMAXNUM needs to be promoted. (#114943)
In #70357, I changed a isLegalOrCustom to isLegalOrCustomOrPromote in
visitSelect to enable integer min/max to be formed when the operation
was promoted. Unfortunately, this also affected floating point. For
floating point, fmaxnum may require a libcall so we also need to check
if the operation on the promoted type is legal or custom.
Other changes to RISC-V have seen made the original change untested so
this patch restores the original isLegalOrCustom.
Fixes #114520.
Commit: a20b902b356e84ec4380d324f7c72772fef0c114
https://github.com/llvm/llvm-project/commit/a20b902b356e84ec4380d324f7c72772fef0c114
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Copy some Zbb and Zbkb IR tests. NFC
These are copies of SDAG tests with some of the more specialized
cases removed. We can add them later when we're ready to improve them.
Commit: 339f395ecef9b7f501a4c4d2b54f85c7f723b50c
https://github.com/llvm/llvm-project/commit/339f395ecef9b7f501a4c4d2b54f85c7f723b50c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
Log Message:
-----------
[RISCV][GISel] Enable commute_constant_to_rhs in RISCVPostLegalizerCombiner.
Commit: 3163f8348faf858dec920f303e95dcf48dc1ea72
https://github.com/llvm/llvm-project/commit/3163f8348faf858dec920f303e95dcf48dc1ea72
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Log Message:
-----------
[RISCV][GISel] Use boolean predicated legalization action methods to simplify code. NFC (#115063)
These allow us to pass a subtarget feature to conditionally enable the
legalization action.
These were added by a3010c77910c706be4c51ce4a95d51211e335a1f and are
used by AArch64.
Commit: 332fda86fb20c6c2cdc58976a8739c6a13110734
https://github.com/llvm/llvm-project/commit/332fda86fb20c6c2cdc58976a8739c6a13110734
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/include/__flat_map/flat_map.h
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove <string> and <vector> includes from <flat_map> (#114876)
`<string>` doesn't seem to be required at all and `flat_map` doesn't
support `vector<bool>`, so we can include just `vector<T>`. This cuts
the include time in half on my system.
Commit: a905203b9ea5ff1b68ca5ab760d6101f64ff3362
https://github.com/llvm/llvm-project/commit/a905203b9ea5ff1b68ca5ab760d6101f64ff3362
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
Log Message:
-----------
[RISCV] Prefer strided load for interleave load with only one lane active (#115069)
If only one of the elements is actually used, then we can legally use a
strided load in place of the segment load. Doing so reduces vector
register pressure, so if both segment and strided are believed to be
element/segment at a time, then prefer the strided load variant.
Note that I've seen the vectorizer emitting wide interleave loads to
represent a strided load, so this does happen in practice. It doesn't
matter much for small LMUL*NF, but at large NF can start causing
problems in register allocation.
Note that this patch only covers the fixed vector formation cases. In
theory, we should do the same patch for scalable, but we can currently
only represent NF2 in scalable IR, and NF2 is assumed to be optimized to
better than segment-at-a-time by default, so there's currently nothing
to do.
Commit: 4d374479bea4b33c5623ccfedc0870e396fc34cd
https://github.com/llvm/llvm-project/commit/4d374479bea4b33c5623ccfedc0870e396fc34cd
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[nfc][tsan] Replace some macros with templates (#114931)
Commit: 320389d4289c9bca579d74e9416bedb7fd4a0ef2
https://github.com/llvm/llvm-project/commit/320389d4289c9bca579d74e9416bedb7fd4a0ef2
Author: vporpo <vporpodas at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
A llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][BottomUpVec] Generate vector instructions (#115087)
This patch implements some very basic code generation, for some opcodes.
Commit: d047488d4c4657be401ae01aa985c5a749f15168
https://github.com/llvm/llvm-project/commit/d047488d4c4657be401ae01aa985c5a749f15168
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec] Fix build warnings in VecUtilsTest
Commit: 435e58468a1a99a4bbfad88d060abd37a9bc6928
https://github.com/llvm/llvm-project/commit/435e58468a1a99a4bbfad88d060abd37a9bc6928
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/OpenMP/allocate_allocator_modifier_ast_print.cpp
A clang/test/OpenMP/allocate_allocator_modifier_codegen.cpp
A clang/test/OpenMP/allocate_allocator_modifier_messages.cpp
Log Message:
-----------
[clang][OpenMP] Add 'allocator' modifier for 'allocate' clause. (#114883)
The 'allocator' modifier is now accepted in the 'allocate' clause. Added
LIT tests covering codegen, PCH, template handling, and serialization
for 'allocator' modifier.
Added support for allocator-modifier to release notes.
Testing
- New allocate modifier LIT tests.
- OpenMP LIT tests.
- check-all
- relevant sollve_vv test cases
tests/5.2/scope/test_scope_allocate_construct.c
Commit: 92be2cb08632ea38f6fbc41adfeb475ba27447dd
https://github.com/llvm/llvm-project/commit/92be2cb08632ea38f6fbc41adfeb475ba27447dd
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/fp-rounding.ll
Log Message:
-----------
[LoongArch] Use LSX for scalar FP rounding with explicit rounding mode (#114766)
LoongArch FP base ISA only have frint.{s/d} instruction which reads the
global rounding mode. Utilize LSX for explicit rounding mode for scalar
ceil/floor/trunc/roundeven calls when -mlsx opend. It is faster than
calling the libm library functions.
Same as what gcc did:
https://gcc.gnu.org/pipermail/gcc-cvs/2023-November/394218.html
Commit: 4c3e1e3c4af1d215501a3b42655333a1167f0ab3
https://github.com/llvm/llvm-project/commit/4c3e1e3c4af1d215501a3b42655333a1167f0ab3
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/include/llvm/MC/MCSchedule.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/MC/MCDisassembler/Disassembler.cpp
M llvm/lib/MC/MCSchedule.cpp
A llvm/test/CodeGen/AArch64/latency.ll
A llvm/test/CodeGen/ARM/latency.ll
Log Message:
-----------
[llvm][AsmPrinter] Add an option to print instruction latencies (#113243)
... matching what we have in the disassembler. This isn't turned on by
default since several of the scheduling models are not completely
accurate, and we don't want to be misleading.
Commit: db21dbd12a13c96786669df9142a3061813c47fb
https://github.com/llvm/llvm-project/commit/db21dbd12a13c96786669df9142a3061813c47fb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV][GISel] Add constant_fold_cast_op to RISCVPostLegalizerCombiner.
Commit: 11b768af3ed672c18c4197bf43273b31ccc3c95e
https://github.com/llvm/llvm-project/commit/11b768af3ed672c18c4197bf43273b31ccc3c95e
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
Log Message:
-----------
[SandboxVec][BottomUpVec] Fix bug in invalidation of analyses
This makes sure we don't preserve analyses when we modify the IR.
This was causing errors in the EXPENSIVE_CHECKS build.
Commit: 9bc3102bea80f422f4f3b788186f6e1c636e0fba
https://github.com/llvm/llvm-project/commit/9bc3102bea80f422f4f3b788186f6e1c636e0fba
Author: Yun-Fly <yunfei.song at intel.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.cpp
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.td
Log Message:
-----------
[mlir][scf] Extend consumer fusion to multiple tilable users (#111955)
Before, consumer fusion expects single usage(or others are terminator
op). This patch supports multiple tilable consumers fusion.
E.g.
```
%0 = scf.for {
...
%p = tiledProducer
...
}
%1 = tilableConsumer1 ins(%0 : ...)
%2 = tilableConsumer2 ins(%0 : ...)
```
===>
```
%0:3 = scf.for {
...
%p = tiledProducer
%1 = tiledConsumer1 ins(%p : ...)
%2 = tiledConsumer2 ins(%p : ...)
...
}
```
The key process is ensuring that the first user of loop
should not dominate any define of consumer operand(s).
Commit: 7c20bdf373d6cd7f35dee5c71cf94f0eb1be3200
https://github.com/llvm/llvm-project/commit/7c20bdf373d6cd7f35dee5c71cf94f0eb1be3200
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M lldb/unittests/Host/AlarmTest.cpp
Log Message:
-----------
[lldb] Fix synchronization in AlarmTest (NFC)
ThreadSanitizer detected a data race as if synchronized via sleep.
Commit: 3a26feb607c8cecc13d6ca4ed5213c3f9c10932c
https://github.com/llvm/llvm-project/commit/3a26feb607c8cecc13d6ca4ed5213c3f9c10932c
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
Log Message:
-----------
[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin (#114945)
In preparation for allowing zvfhmin and zvfbfmin in
isLegalElementTypeForRVV, this lowers fixed-length masked gathers and
scatters
We need to mark f16 and bf16 as legal in isLegalMaskedGatherScatter
otherwise ScalarizeMaskedMemIntrin will just scalarize them, but we can
move this back into isLegalElementTypeForRVV afterwards.
The scalarized codegen required #114938, #114927 and #114915 to not
crash.
Commit: 7fb13a934f19797cd722f2a80355690c21d6e3b9
https://github.com/llvm/llvm-project/commit/7fb13a934f19797cd722f2a80355690c21d6e3b9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
Log Message:
-----------
[ORC] lazyReexports: Swap IndirectStubsManager for RedirectableSymbolsManager.
RedirectableSymbolsManager is a native SymbolStringPtr API (requires fewer
string operations) and has a narrower interface that permits a wider range of
implementations.
IndirectStubsManager is updated to make it a RedirectableSymbolsManager so that
existing uses continue to work.
Commit: 895a8e66c6d1e42519909981ab1bb0ad41231029
https://github.com/llvm/llvm-project/commit/895a8e66c6d1e42519909981ab1bb0ad41231029
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
Log Message:
-----------
[AArch64][GISel] Support neon.abs intrinsic for vector types (#107226)
This patch lowers the intrinsic to G_ABS and thus supports the intrinsic in GISel.
Commit: 236fda550d36d35a00785938c3e38b0f402aeda6
https://github.com/llvm/llvm-project/commit/236fda550d36d35a00785938c3e38b0f402aeda6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CGSCCPassManager.cpp
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DemandedBits.cpp
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp
M llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp
M llvm/lib/Analysis/InstCount.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[Analysis] Remove unused includes (NFC) (#114936)
Identified with misc-include-cleaner.
Commit: 9ba0e5c27de210ca04937e87042e5e8541a9ee21
https://github.com/llvm/llvm-project/commit/9ba0e5c27de210ca04937e87042e5e8541a9ee21
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
R llvm/test/CodeGen/LoongArch/merge-load-store.ll
Log Message:
-----------
Revert "[LoongArch][NFC] Pre-commit tests for codegen with alias analysis"
This reverts commit 445db93844cb50eeb6f587bef0749c2950b46e70.
Commit: a165bbddf9b47c11a0869d09cc32de1d2b19f89f
https://github.com/llvm/llvm-project/commit/a165bbddf9b47c11a0869d09cc32de1d2b19f89f
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/merge-load-store.ll
Log Message:
-----------
[LoongArch][NFC] Reland "Pre-commit tests for codegen with alias analysis"
Commit: e48d8f9fea69095757d3593a567316197ec70450
https://github.com/llvm/llvm-project/commit/e48d8f9fea69095757d3593a567316197ec70450
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
Log Message:
-----------
[Clang] Correctly initialize placeholder fields from their initializers (#114196)
We made the incorrect assumption that names of fields are unique when
creating their default initializers.
We fix that by keeping track of the instantiaation pattern for field
decls that are placeholder vars,
like we already do for unamed fields.
Fixes #114069
Commit: d22d63a7855840dd6398b77dcad71f001788ac86
https://github.com/llvm/llvm-project/commit/d22d63a7855840dd6398b77dcad71f001788ac86
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/LoopUtils.h
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
Log Message:
-----------
[MLIR][Affine] Fix signature of mlir::affine::permuteLoops (#111100)
The method doesn't mutate its argument. A mutable one was being passed
only to get around ArrayRef providing const on elements, which MLIR
doesn't use on IR types.
Commit: cbc7812565b0b0d60c0dadbd3743650f863237d4
https://github.com/llvm/llvm-project/commit/cbc7812565b0b0d60c0dadbd3743650f863237d4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
Log Message:
-----------
[RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC
We already have a Zfinx RUN line for rv64f-float-convert.ll.
Commit: 492812f613280034b7c514d74113750814a3de76
https://github.com/llvm/llvm-project/commit/492812f613280034b7c514d74113750814a3de76
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
Log Message:
-----------
[WebAssembly] Fix rethrow's index calculation (#114693)
So far we have assumed that we only rethrow the exception caught in the
innermost EH pad. This is true in code we directly generate, but after
inlining this may not be the case. For example, consider this code:
```ll
ehcleanup:
%0 = cleanuppad ...
call @destructor
cleanupret from %0 unwind label %catch.dispatch
```
If `destructor` gets inlined into this function, the code can be like
```ll
ehcleanup:
%0 = cleanuppad ...
invoke @throwing_func
to label %unreachale unwind label %catch.dispatch.i
catch.dispatch.i:
catchswitch ... [ label %catch.start.i ]
catch.start.i:
%1 = catchpad ...
invoke @some_function
to label %invoke.cont.i unwind label %terminate.i
invoke.cont.i:
catchret from %1 to label %destructor.exit
destructor.exit:
cleanupret from %0 unwind label %catch.dispatch
```
We lower a `cleanupret` into `rethrow`, which assumes it rethrows the
exception caught by the nearest dominating EH pad. But after the
inlining, the nearest dominating EH pad is not `ehcleanup` but
`catch.start.i`.
The problem exists in the same manner in the new (exnref) EH, because it
assumes the exception comes from the nearest EH pad and saves an exnref
from that EH pad and rethrows it (using `throw_ref`).
This problem can be fixed easily if `cleanupret` has the basic block
where its matching `cleanuppad` is. The bitcode instruction `cleanupret`
kind of has that info (it has a token from the `cleanuppad`), but that
info is lost when when we enter ISel, because `TargetSelectionDAG.td`'s
`cleanupret` node does not have any arguments:
https://github.com/llvm/llvm-project/blob/5091a359d9807db8f7d62375696f93fc34226969/llvm/include/llvm/Target/TargetSelectionDAG.td#L700
Note that `catchret` already has two basic block arguments, even though
neither of them means `catchpad`'s BB.
This PR adds the `cleanuppad`'s BB as an argument to `cleanupret` node
in ISel and uses it in the Wasm backend. Because this node is also used
in X86 backend we need to note its argument there too but nothing more
needs to change there as long as X86 doesn't need it.
---
- Details about changes in the Wasm backend:
After this PR, our pseudo `RETHROW` instruction takes a BB, which means
the EH pad whose exception it needs to rethrow. There are currently two
ways to generate a `RETHROW`: one is from `llvm.wasm.rethrow` intrinsic
and the other is from `CLEANUPRET` we discussed above. In case of
`llvm.wasm.rethrow`, we add a '0' as a placeholder argument when it is
lowered to a `RETHROW`, and change it to a BB in LateEHPrepare. As
written in the comments, this PR doesn't change how this BB is computed.
The BB argument will be converted to an immediate argument as with other
control flow instructions in CFGStackify.
In case of `CLEANUPRET`, it already has a BB argument pointing to an EH
pad, so it is just converted to a `RETHROW` with the same BB argument in
LateEHPrepare. This will also be lowered to an immediate in CFGStackify
with other control flow instructions.
---
Fixes #114600.
Commit: f4270045f49d4936cd1d60e49f780ae9b1c18fab
https://github.com/llvm/llvm-project/commit/f4270045f49d4936cd1d60e49f780ae9b1c18fab
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
M llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
Log Message:
-----------
[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
Commit: 84ce230e4298672bb5247170d6183b31aa06fc4b
https://github.com/llvm/llvm-project/commit/84ce230e4298672bb5247170d6183b31aa06fc4b
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M libcxx/include/__random/binomial_distribution.h
Log Message:
-----------
[libcxx] Use `lgamma` rather than `lgamma_r` with LLVM libc (#109556)
`lgamma_r` is currently only available on GPU targets.
Commit: 4480a22c2b8587c761a44c4290e3fdd9e4be75d3
https://github.com/llvm/llvm-project/commit/4480a22c2b8587c761a44c4290e3fdd9e4be75d3
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
Log Message:
-----------
[LV][EVL] Emit vp.merge intrinsic to enable out-loop reduction in EVL vectorization. (#101641)
Following #90184, this patch emits vp.merge intrinsic, which is used to
set the inactive lanes in a select operation to the RHS instead of
undef. Currently, it is applied to out-loop reduction for EVL
vectorization.
This patch performs transformation to convert
select(header_mask, LHS, RHS)
into
vp.merge(all-true, LHS, RHS, EVL)
And always use the predicated reduction select to set the incoming value
of the reduction phi to support out-loop reduction when using tail
folding with EVL.
TODO: Postpone the adjustment of the predicated reduction select to
VPlanTransform. The current adjustment might be too early, which could
lead to a situation where the predicated reduction select is adjusted,
but the EVL recipes cannot be successfully generated during
VPlanTransform.
Commit: 5adb5c05a2e9f31385fbba8b0436cbc07d91a44d
https://github.com/llvm/llvm-project/commit/5adb5c05a2e9f31385fbba8b0436cbc07d91a44d
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/memcmp-optsize.ll
A llvm/test/CodeGen/RISCV/memcmp.ll
Log Message:
-----------
[RISCV] Add tests for memcmp expansion
We add tests for the following cases:
* Length = 0, 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, 31, 32, 63, 64, 127,
128, runtime.
* Comparisons against zero.
* RUN lines for scalar/vector w/ or w/o strict align.
* Optimize for size.
Reviewers: topperc, preames
Reviewed By: topperc, preames
Pull Request: https://github.com/llvm/llvm-project/pull/107824
Commit: 0e907c17214aa3b1a60b66867fea3cc0f0dcbaa0
https://github.com/llvm/llvm-project/commit/0e907c17214aa3b1a60b66867fea3cc0f0dcbaa0
Author: Iñaki Amatria Barral <140811900+inaki-amatria at users.noreply.github.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Semantics/mod-file.cpp
A flang/test/Semantics/Inputs/modfile70.mod
M flang/test/Semantics/modfile63.f90
A flang/test/Semantics/modfile70.f90
Log Message:
-----------
[flang] Prevent errors from being suppressed (#114420)
`ModFileReader::Say()` flags all messages as errors, but Flang was
mistakenly suppressing two errors when the `-w` flag was used, as they
were incorrectly conditioned to warning suppression. This fix ensures
that errors are reported regardless of the `-w` flag.
This commit also replaces two uses of `_warn_en_US` with `_err_en_US` to
prevent potential confusion in the future.
Commit: 6d719d9700261283e7f90cdaffb64a62d526f583
https://github.com/llvm/llvm-project/commit/6d719d9700261283e7f90cdaffb64a62d526f583
Author: Sylvestre Ledru <sylvestre at debian.org>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
M compiler-rt/lib/xray/xray_interface_internal.h
R compiler-rt/lib/xray/xray_s390x.cpp
R compiler-rt/lib/xray/xray_trampoline_s390x.S
M compiler-rt/lib/xray/xray_tsc.h
Log Message:
-----------
Revert "[SystemZ][XRay] XRay runtime support for SystemZ (#113252)"
for causing: https://github.com/llvm/llvm-project/issues/115129
This reverts commit db1882e2484013066139f0b3f77d968d84a79158.
Commit: 41248b598b8b18febc62ea61938870def2421126
https://github.com/llvm/llvm-project/commit/41248b598b8b18febc62ea61938870def2421126
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/docs/CodeReview.rst
M llvm/docs/Contributing.rst
Log Message:
-----------
[docs] Update docs on code-review process (#111735)
Clarify expectations for handling new comments post-LGTM but pre-commit.
This change aims to standardize expectations when new comments are added
after a patch has received LGTM but before it has been committed.
Currently, approaches to this vary, and this update seeks to clarify
best practices.
Commit: 7a5b040e20394a4794b4360a56de8a172b5e27f4
https://github.com/llvm/llvm-project/commit/7a5b040e20394a4794b4360a56de8a172b5e27f4
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
Log Message:
-----------
[RISCV] Add initial support of memcmp expansion
There are two passes that have dependency on the implementation
of `TargetTransformInfo::enableMemCmpExpansion` : `MergeICmps` and
`ExpandMemCmp`.
This PR adds the initial implementation of `enableMemCmpExpansion`
so that we can have some basic benefits from these two passes.
We don't enable expansion when there is no unaligned access support
currently because there are some issues about unaligned loads and
stores in `ExpandMemcmp` pass. We should fix these issues and enable
the expansion later.
Vector case hasn't been tested as we don't generate inlined vector
instructions for memcmp currently.
Reviewers: preames, arcbbb, topperc, asb, dtcxzyw
Reviewed By: topperc, preames
Pull Request: https://github.com/llvm/llvm-project/pull/107548
Commit: c96a85abfde822f2eda9076eb40078389b21f23e
https://github.com/llvm/llvm-project/commit/c96a85abfde822f2eda9076eb40078389b21f23e
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
Log Message:
-----------
[mlir][VectorToSPIRV] Add conversion for vector.extract with dynamic indices (#114137)
Commit: dc55d31f4cf5c97b56f6b7e1c24b70674cc15a01
https://github.com/llvm/llvm-project/commit/dc55d31f4cf5c97b56f6b7e1c24b70674cc15a01
Author: Longsheng Mou <moulongsheng at huawei.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir][tensor] Fix a crash in `ExtractOp::fold` (#115001)
This PR fixes a crash when the tensor of `tensor.extract` is a dense
resource elements attribute.
Fixes #114728.
Co-authored-by: jinzhi <jinzhi6 at huawei.com>
Commit: 08411c855f77bd7416725c280ad3dccdc00b7dd6
https://github.com/llvm/llvm-project/commit/08411c855f77bd7416725c280ad3dccdc00b7dd6
Author: Gergely Futo <gergely.futo at hightec-rt.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/test/CodeGen/RISCV/copysign-casts.ll
Log Message:
-----------
[RISCV] Correct fcopysign pattern for zdinx (#114954)
Correcting the pattern fixes the following error:
fatal error: error in backend: Cannot select: t17: f64 = fcopysign t5,
t8
Commit: 69d0bab82689d470e3fd68f50ca8b8d28f3e2294
https://github.com/llvm/llvm-project/commit/69d0bab82689d470e3fd68f50ca8b8d28f3e2294
Author: BoyaoWang430 <wangboyao at bytedance.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
A llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
Log Message:
-----------
[RISCV] Add load/store clustering in post machine schedule (#111504)
#73789 added load clustering and #73796 tried to add store clustering.
If post machine schedule is used, previous cluster of load/store which
formed in machine schedule may break. In order to solve this, add
load/sotre clustering to post machine schedule.
Commit: c0a7b60fd1b244782032fefc261c4442c54c3935
https://github.com/llvm/llvm-project/commit/c0a7b60fd1b244782032fefc261c4442c54c3935
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private-ptr.mlir
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private.mlir
Log Message:
-----------
Revert "[flang][OpenMP] Add alias analysis for omp private" (#115135)
Reverts llvm/llvm-project#113566 (commit id: f3025c8b4fd797d99a8a8117254f93605ec46aa8 )
because of regression in Fujitsu compiler test suite.
Commit: 8431494094c8732d1426763d3e1aae322fa76830
https://github.com/llvm/llvm-project/commit/8431494094c8732d1426763d3e1aae322fa76830
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/lib/Basic/SourceManager.cpp
M clang/test/Lexer/SourceLocationsOverflow.c
M clang/test/Misc/sloc-usage.cpp
Log Message:
-----------
[clang] Make source locations space usage diagnostics numbers easier to read (#114999)
Instead of writing "12345678B", write "12345678B (12.34MB)".
Commit: 37ce18951fded6be1de319b05b968918cb45c00b
https://github.com/llvm/llvm-project/commit/37ce18951fded6be1de319b05b968918cb45c00b
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/misched-mem-clustering.mir
Log Message:
-----------
[RISCV] Add requirement of asserts
We forgot to add `REQUIRES: asserts` here.
Commit: 7be30fd5335ca7fe050ee1789ea2648f014daf1b
https://github.com/llvm/llvm-project/commit/7be30fd5335ca7fe050ee1789ea2648f014daf1b
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
A libclc/clc/include/clc/integer/clc_abs.h
A libclc/clc/include/clc/integer/clc_abs.inc
A libclc/clc/include/clc/integer/clc_abs_diff.h
A libclc/clc/include/clc/integer/clc_abs_diff.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_abs.cl
A libclc/clc/lib/generic/integer/clc_abs.inc
A libclc/clc/lib/generic/integer/clc_abs_diff.cl
A libclc/clc/lib/generic/integer/clc_abs_diff.inc
M libclc/generic/lib/integer/abs.cl
M libclc/generic/lib/integer/abs.inc
M libclc/generic/lib/integer/abs_diff.cl
M libclc/generic/lib/integer/abs_diff.inc
M libclc/generic/lib/math/clc_fma.cl
M libclc/generic/lib/math/clc_hypot.cl
Log Message:
-----------
[libclc] Move abs/abs_diff to CLC library
Commit: b4263ddbe7cbcc9e0b5b0ea07c252056355301d0
https://github.com/llvm/llvm-project/commit/b4263ddbe7cbcc9e0b5b0ea07c252056355301d0
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libclc/generic/lib/math/clc_fma.cl
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_remainder.cl
M libclc/generic/lib/math/clc_remquo.cl
M libclc/generic/lib/math/sincos_helpers.cl
Log Message:
-----------
[libclc] Use __clc_max in CLC functions
Commit: ed9dab67e2932baf11bfa514b07b159c3bffd518
https://github.com/llvm/llvm-project/commit/ed9dab67e2932baf11bfa514b07b159c3bffd518
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
Log Message:
-----------
[ARM] Add extra tests for CVE-2024-7883 with undef/poison
Commit: 8c565de5ec6d49143ba9ae7c73b188314d31e563
https://github.com/llvm/llvm-project/commit/8c565de5ec6d49143ba9ae7c73b188314d31e563
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
A llvm/test/CodeGen/LoongArch/double-lround.ll
A llvm/test/CodeGen/LoongArch/float-lround.ll
Log Message:
-----------
[LoongArch] Support llvm.lround intrinsics with i32 return type. (#114733)
This is needed by flang, similar to RISCV-64 in
https://reviews.llvm.org/D147195.
Commit: 5acc4a3dc0e2145d2bfef47f1543bb291c2b866a
https://github.com/llvm/llvm-project/commit/5acc4a3dc0e2145d2bfef47f1543bb291c2b866a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/include/__cstddef/nullptr_t.h
M libcxx/include/__cstddef/ptrdiff_t.h
M libcxx/include/__cstddef/size_t.h
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/hash.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/forward_list
M libcxx/include/new
M libcxx/include/string_view
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp
Log Message:
-----------
[libc++] Remove <stddef.h> includes from the granularized <cstddef> headers (#114788)
We can define some of these aliases without having to include the system
<stddef.h> and there doesn't seem to be much of a reason we shouldn't do
it this way.
Commit: c6f3b7bcd0596d30f8dabecdfb9e44f9a07b6e4c
https://github.com/llvm/llvm-project/commit/c6f3b7bcd0596d30f8dabecdfb9e44f9a07b6e4c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/docs/DesignDocs/ThreadingSupportAPI.rst
M libcxx/include/__algorithm/find.h
M libcxx/include/__algorithm/lexicographical_compare.h
M libcxx/include/__algorithm/sort.h
M libcxx/include/__atomic/aliases.h
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__atomic/cxx_atomic_impl.h
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/high_resolution_clock.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/parser_std_format_spec.h
M libcxx/include/__chrono/statically_widen.h
M libcxx/include/__chrono/steady_clock.h
M libcxx/include/__chrono/time_zone.h
M libcxx/include/__chrono/time_zone_link.h
M libcxx/include/__chrono/tzdb.h
M libcxx/include/__chrono/tzdb_list.h
M libcxx/include/__chrono/zoned_time.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__config_site.in
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__filesystem/directory_entry.h
M libcxx/include/__filesystem/directory_iterator.h
M libcxx/include/__filesystem/operations.h
M libcxx/include/__filesystem/path.h
M libcxx/include/__filesystem/recursive_directory_iterator.h
M libcxx/include/__format/concepts.h
M libcxx/include/__format/format_arg_store.h
M libcxx/include/__format/format_context.h
M libcxx/include/__format/format_functions.h
M libcxx/include/__format/format_parse_context.h
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_char.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/__format/formatter_string.h
M libcxx/include/__format/parser_std_format_spec.h
M libcxx/include/__format/unicode.h
M libcxx/include/__format/write_escaped.h
M libcxx/include/__functional/hash.h
M libcxx/include/__fwd/fstream.h
M libcxx/include/__fwd/ios.h
M libcxx/include/__fwd/istream.h
M libcxx/include/__fwd/ostream.h
M libcxx/include/__fwd/sstream.h
M libcxx/include/__fwd/streambuf.h
M libcxx/include/__fwd/string.h
M libcxx/include/__fwd/string_view.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__mbstate_t.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory_resource/synchronized_pool_resource.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__ostream/print.h
M libcxx/include/__random/random_device.h
M libcxx/include/__ranges/istream_view.h
M libcxx/include/__stop_token/atomic_unique_lock.h
M libcxx/include/__stop_token/stop_callback.h
M libcxx/include/__stop_token/stop_source.h
M libcxx/include/__stop_token/stop_state.h
M libcxx/include/__stop_token/stop_token.h
M libcxx/include/__string/char_traits.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/__thread/formatter.h
M libcxx/include/__thread/id.h
M libcxx/include/__thread/jthread.h
M libcxx/include/__thread/support.h
M libcxx/include/__thread/this_thread.h
M libcxx/include/__thread/thread.h
M libcxx/include/__thread/timed_backoff_policy.h
M libcxx/include/__type_traits/is_integral.h
M libcxx/include/__vector/vector.h
M libcxx/include/barrier
M libcxx/include/chrono
M libcxx/include/codecvt
M libcxx/include/complex
M libcxx/include/condition_variable
M libcxx/include/cstdlib
M libcxx/include/deque
M libcxx/include/format
M libcxx/include/fstream
M libcxx/include/future
M libcxx/include/iomanip
M libcxx/include/ios
M libcxx/include/iosfwd
M libcxx/include/iostream
M libcxx/include/istream
M libcxx/include/latch
M libcxx/include/list
M libcxx/include/locale
M libcxx/include/mutex
M libcxx/include/ostream
M libcxx/include/print
M libcxx/include/ranges
M libcxx/include/regex
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/sstream
M libcxx/include/stdatomic.h
M libcxx/include/stop_token
M libcxx/include/streambuf
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/syncstream
M libcxx/include/thread
M libcxx/include/vector
M libcxx/include/version
M libcxx/include/wchar.h
M libcxx/modules/std.compat.cppm.in
M libcxx/modules/std.compat/clocale.inc
M libcxx/modules/std.compat/cstdlib.inc
M libcxx/modules/std.compat/cwchar.inc
M libcxx/modules/std.compat/cwctype.inc
M libcxx/modules/std.cppm.in
M libcxx/modules/std/atomic.inc
M libcxx/modules/std/barrier.inc
M libcxx/modules/std/chrono.inc
M libcxx/modules/std/clocale.inc
M libcxx/modules/std/codecvt.inc
M libcxx/modules/std/complex.inc
M libcxx/modules/std/condition_variable.inc
M libcxx/modules/std/cstdlib.inc
M libcxx/modules/std/cwchar.inc
M libcxx/modules/std/cwctype.inc
M libcxx/modules/std/filesystem.inc
M libcxx/modules/std/format.inc
M libcxx/modules/std/fstream.inc
M libcxx/modules/std/future.inc
M libcxx/modules/std/iomanip.inc
M libcxx/modules/std/ios.inc
M libcxx/modules/std/iosfwd.inc
M libcxx/modules/std/iostream.inc
M libcxx/modules/std/istream.inc
M libcxx/modules/std/latch.inc
M libcxx/modules/std/locale.inc
M libcxx/modules/std/memory.inc
M libcxx/modules/std/mutex.inc
M libcxx/modules/std/ostream.inc
M libcxx/modules/std/print.inc
M libcxx/modules/std/random.inc
M libcxx/modules/std/ranges.inc
M libcxx/modules/std/regex.inc
M libcxx/modules/std/semaphore.inc
M libcxx/modules/std/shared_mutex.inc
M libcxx/modules/std/spanstream.inc
M libcxx/modules/std/sstream.inc
M libcxx/modules/std/stop_token.inc
M libcxx/modules/std/streambuf.inc
M libcxx/modules/std/string.inc
M libcxx/modules/std/string_view.inc
M libcxx/modules/std/strstream.inc
M libcxx/modules/std/syncstream.inc
M libcxx/modules/std/thread.inc
M libcxx/src/algorithm.cpp
M libcxx/src/call_once.cpp
M libcxx/src/chrono.cpp
M libcxx/src/experimental/include/tzdb/tzdb_list_private.h
M libcxx/src/filesystem/time_utils.h
M libcxx/src/include/atomic_support.h
M libcxx/src/include/config_elast.h
M libcxx/src/ios.cpp
M libcxx/src/ios.instantiations.cpp
M libcxx/src/iostream.cpp
M libcxx/src/locale.cpp
M libcxx/src/memory.cpp
M libcxx/src/memory_resource.cpp
M libcxx/src/ostream.cpp
M libcxx/src/print.cpp
M libcxx/src/random_shuffle.cpp
M libcxx/src/std_stream.h
M libcxx/src/string.cpp
M libcxx/src/system_error.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/libcxx/depr/depr.c.headers/extern_c.pass.cpp
M libcxx/test/libcxx/feature_test_macro/ftm_metadata.sh.py
M libcxx/test/libcxx/feature_test_macro/test_data.json
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/test/libcxx/feature_test_macro/version_header_implementation.sh.py
M libcxx/test/libcxx/include_as_c.sh.cpp
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.tests.h
M libcxx/test/std/language.support/support.limits/support.limits.general/barrier.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/latch.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/semaphore.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/stop_token.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
M libcxx/test/support/filesystem_test_helper.h
M libcxx/test/support/test_macros.h
M libcxx/test/tools/clang_tidy_checks/internal_ftm_use.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/header_information.py
M libcxx/utils/libcxx/test/dsl.py
M libcxx/utils/libcxx/test/features.py
M runtimes/cmake/Modules/HandleFlags.cmake
Log Message:
-----------
[libc++] Refactor the configuration macros to being always defined (#112094)
This is a follow-up to #89178. This updates the `<__config_site>`
macros.
Commit: e29d092af8b0ed2b15ce1dfd9fc4caef1976eef7
https://github.com/llvm/llvm-project/commit/e29d092af8b0ed2b15ce1dfd9fc4caef1976eef7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-pmuldq.ll
Log Message:
-----------
[X86] getFauxShuffleMask - add ISD::SHL/SRL handling
This is currently mostly the same as the VSHLI/VSRLI handling below, although I've kept them separate as I'm investigating adding non-uniform shift amount handling as a followup
Commit: 270bfb2f2abc48ec916fce7e677fe3cc6f2908d0
https://github.com/llvm/llvm-project/commit/270bfb2f2abc48ec916fce7e677fe3cc6f2908d0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
Log Message:
-----------
[X86] Add test coverage for #114959
Commit: 2f48765b45ba87d780caf7d058d416b5dda32d7e
https://github.com/llvm/llvm-project/commit/2f48765b45ba87d780caf7d058d416b5dda32d7e
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][bazel] Remove -mllvm --tail-merge-threshold=0 from Bazel. (#115061)
Follow-up on the `-mllvm --tail-merge-threshold=0` removal promised in
aeccc16497a84d61200f7ccfa3864096349260d3 (see
b2a9ea4420127d10b18ae648b16757665f8bbd7c commit message on why we don't
need this in Bazel, and will only keep in AArch64-specific compile flags
in CMake build).
Commit: 3d4d033ceaf9e72491a20e9210f396aa3ec52fa5
https://github.com/llvm/llvm-project/commit/3d4d033ceaf9e72491a20e9210f396aa3ec52fa5
Author: David Green <david.green at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/double_reduct.ll
M llvm/test/CodeGen/Thumb2/mve-doublereduct.ll
Log Message:
-----------
[AArch64][Arm] Add nested double reduction tests. NFC
Commit: ebfafa2511f92eed484895f3265ced40f4c1fc70
https://github.com/llvm/llvm-project/commit/ebfafa2511f92eed484895f3265ced40f4c1fc70
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
A llvm/test/CodeGen/SPIRV/pointers/composite-fun-fix-ptr-arg.ll
Log Message:
-----------
[SPIR-V] Fix OpFunctionParameter vs. OpTypeFunction types for pointer arguments when there are functions with aggregate arguments (#115044)
The goal of the PR is to ensure that if module contains functions with
mutated signature (due to preprocessing of aggregate types), functions
still are going through re-creating of function type to preserve pointee
type information for arguments.
This fixes a bug when a module with (1) a function having aggregate
arguments and/or return, and (2) at least two functions with signatures
different only wrt. pointee types is translated so that one of two
similar functions gets an incorrect OpFunctionParameter type that is
different from the corresponding OpTypeFunction definition.
A reproducer is attached as a new test case.
Commit: f363f9d61eaff7090a19d226ea8786b2987d4fcc
https://github.com/llvm/llvm-project/commit/f363f9d61eaff7090a19d226ea8786b2987d4fcc
Author: SahilPatidar <patidarsahil2001 at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M compiler-rt/lib/orc/dlfcn_wrapper.cpp
M compiler-rt/lib/orc/elfnix_platform.cpp
M compiler-rt/lib/orc/elfnix_platform.h
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC][Runtime] Add `dlupdate` for elf (#110406)
With the help of @lhames, This pull request introduces the dlupdate
function in the ORC runtime. dlupdate enables incremental execution of
new initializers introduced in the REPL environment. Unlike traditional
dlopen, which manages initializers, code mapping, and library reference
counts, dlupdate focuses exclusively on running new initializers.
Commit: d77a36e01b8fed496b29c3b2c12526f8dc380766
https://github.com/llvm/llvm-project/commit/d77a36e01b8fed496b29c3b2c12526f8dc380766
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LoopVectorize] Use new getUniqueLatchExitBlock routine (#108231)
With PR #88385 I am introducing support for vectorising more loops with
early exits that don't require a scalar epilogue. As such, if a loop
doesn't have a unique exit block it will not automatically imply we
require a scalar epilogue. Also, in all places in the code today where
we use the variable LoopExitBlock we actually mean the exit block from
the latch. Therefore, it seemed reasonable to add a new
getUniqueLatchExitBlock that allows the caller to determine the exit
block taken from the latch and use this instead of getUniqueExitBlock. I
also renamed LoopExitBlock to be LatchExitBlock. I feel this not only
better reflects how the variable is used today, but also prepares the
code for PR #88385.
While doing this I also noticed that one of the comments in
requiresScalarEpilogue is wrong when we require a scalar epilogue, i.e.
when we're not exiting from the latch block. This doesn't always imply
we have multiple exits, e.g. see the test in
Transforms/LoopVectorize/unroll_nonlatch.ll
where the latch unconditionally branches back to the only exiting block.
Commit: 2d56de9e7e4a3accde42b4d7d329acd007989df8
https://github.com/llvm/llvm-project/commit/2d56de9e7e4a3accde42b4d7d329acd007989df8
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
Log Message:
-----------
Revert "[ARM] Add extra tests for CVE-2024-7883 with undef/poison"
Reverting because this causes a test failure in the expensive-checks
buildbot.
This reverts commit ed9dab67e2932baf11bfa514b07b159c3bffd518.
Commit: 9f8c3d3796ebf7ddd4a85134ff109cf03a0b9b5e
https://github.com/llvm/llvm-project/commit/9f8c3d3796ebf7ddd4a85134ff109cf03a0b9b5e
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
R lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpoinsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpointsSameCUName.py
Log Message:
-----------
[lldb][test] Correct typo in breakpoint test file name
Added by https://github.com/llvm/llvm-project/pull/114896.
Commit: c75353313ed73c6dc04beb322954bb905906f4a1
https://github.com/llvm/llvm-project/commit/c75353313ed73c6dc04beb322954bb905906f4a1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
Log Message:
-----------
[X86] combineConcatVectorOps - add 256-bit concat(shuffle(),shuffle()) handling
Improve IsConcatFree detection to handle splat vector-loads (which can be folded as X86ISD::SUBV_BROADCAST_LOAD).
Fixes #114959
Commit: 5a16ed96c5362aa8e9610fa266d6f6202b19edc3
https://github.com/llvm/llvm-project/commit/5a16ed96c5362aa8e9610fa266d6f6202b19edc3
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add +unaligned-scalar-mem to spacemit-x60 (#115125)
I can't find any official documentation on this, but from other
discussions[^1] and my own testing the spacemit-x60 seems to support
unaligned scalar loads and stores.
They seem to be performant, and just from a quick test we get a 2.45%
speedup on 500.perlbench_r on the Banana Pi F3[^2].
This would allow it to take advantage of #107548.
[^1]:
https://github.com/llvm/llvm-project/issues/110454#issuecomment-2382199460
[^2]: https://lnt.lukelau.me/db_default/v4/nts/32
Commit: f87484d5910c1c708bfd93ef588d6ff8307e2477
https://github.com/llvm/llvm-project/commit/f87484d5910c1c708bfd93ef588d6ff8307e2477
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Target/LLVM/CMakeLists.txt
Log Message:
-----------
Fix libnvptxcompiler_static.a absolute path (#115015)
Now when building llvm-solid with `-DMLIR_ENABLE_NVPTXCOMPILER=ON`,
there will be an absolute path (`/path/to/libnvptxcompiler_static.a`) in
MLIRNVVMTarget dependencies (in
`/build/path/install/lib/cmake/mlir/MLIRTargets.cmake`). For example,
```cmake
set_target_properties(MLIRNVVMTarget PROPERTIES
INTERFACE_LINK_LIBRARIES "MLIRIR;MLIRExecutionEngineUtils;MLIRSupport;MLIRGPUDialect;MLIRTargetLLVM;MLIRNVVMToLLVMIRTranslation;LLVMSupport;/path/to/libnvptxcompiler_static.a"
)
```
If downstream project uses pre-built llvm and depends on MLIRNVVMTarget,
it may fail to build due to the absence of the
`libnvptxcompiler_static.a` absolute path.
After this commit, there will no absolute path in
`/build/path/install/lib/cmake/mlir/MLIRTargets.cmake`
```cmake
set_target_properties(MLIRNVVMTarget PROPERTIES
INTERFACE_LINK_LIBRARIES "MLIRIR;MLIRExecutionEngineUtils;MLIRSupport;MLIRGPUDialect;MLIRTargetLLVM;MLIRNVVMToLLVMIRTranslation;LLVMSupport;\$<LINK_ONLY:MLIR_NVPTXCOMPILER_LIB>"
)
```
Then downstream project can modify `libnvptxcompiler_static.a` path and
use cmake to build. For example,
```cmake
# find_library(...)
add_library(MLIR_NVPTXCOMPILER_LIB STATIC IMPORTED GLOBAL)
set_property(TARGET MLIR_NVPTXCOMPILER_LIB PROPERTY IMPORTED_LOCATION ${...})
```
Commit: 40556d08491f530e03746fb188b38e7f9cb272c7
https://github.com/llvm/llvm-project/commit/40556d08491f530e03746fb188b38e7f9cb272c7
Author: brod4910 <13954100+brod4910 at users.noreply.github.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Log Message:
-----------
[MLIR][Tensor] Fix out-of-bounds FoldEmptyTensorWithDimOp crash (#112196)
Fixes #111270
Commit: ea6b8fa4b9b48a11c2657bedf35ad5291b1e2b9c
https://github.com/llvm/llvm-project/commit/ea6b8fa4b9b48a11c2657bedf35ad5291b1e2b9c
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
Log Message:
-----------
[SDAG] Merge multiple-result libcall expansion into DAG.expandMultipleResultFPLibCall() (#114792)
This merges the logic for expanding both FFREXP and FSINCOS into one
method `DAG.expandMultipleResultFPLibCall()`. This reduces duplication
and also allows FFREXP to benefit from the stack slot elimination
implemented for FSINCOS. This method will also be used in future to
implement more multiple-result intrinsics (such as modf and sincospi).
Commit: 56077e5ac09eb2d6b7ca818abce2bbbcf179f529
https://github.com/llvm/llvm-project/commit/56077e5ac09eb2d6b7ca818abce2bbbcf179f529
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/COFF/SymbolTable.cpp
A lld/test/COFF/locally-imported-arm64ec.test
Log Message:
-----------
[LLD][COFF] Add support for locally imported EC symbols (#114985)
Allow imported symbols to be recognized in both mangled and demangled
forms. Support __imp_aux_ symbols in addition to __imp_ symbols.
Commit: eab7be5d42ad30c9992ff72c3be9298702001dc8
https://github.com/llvm/llvm-project/commit/eab7be5d42ad30c9992ff72c3be9298702001dc8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/include/__algorithm/adjacent_find.h
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/any_of.h
M libcxx/include/__algorithm/copy_if.h
M libcxx/include/__algorithm/count_if.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/ranges_adjacent_find.h
M libcxx/include/__algorithm/ranges_all_of.h
M libcxx/include/__algorithm/ranges_any_of.h
M libcxx/include/__algorithm/ranges_copy_if.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/ranges_count_if.h
M libcxx/include/__algorithm/ranges_fill_n.h
M libcxx/include/__algorithm/unique.h
Log Message:
-----------
[libc++] Forward more algorithms to the classic algorithms (#114674)
This partially addresses #105687.
Commit: 2bbb6c067020bef50435c2ba5addcd66d1b9a1dd
https://github.com/llvm/llvm-project/commit/2bbb6c067020bef50435c2ba5addcd66d1b9a1dd
Author: Chris Cotter <ccotter14 at bloomberg.net>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp
Log Message:
-----------
[clang][NFC] Spell out DynTypedNode instead of auto (#114427)
Commit: 3c4e6c17f066d9cf5a5b065a05bdff472f721bf6
https://github.com/llvm/llvm-project/commit/3c4e6c17f066d9cf5a5b065a05bdff472f721bf6
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M flang/test/Driver/arch-specific-libdir-rpath.f95
Log Message:
-----------
[flang][Driver] When linking with the Fortran runtime, the `addArchSpecificRPath()` should be called too (#114837)
When linking with other runtimes (OpenMP, sanitizers), the
addArchSpecificRPath() is being called. The same thing should happen
when linking with the Fortran runtime, this will improve user experience
massively.
Commit: d8354d63db66e5d67d74b24b1611b578700f1134
https://github.com/llvm/llvm-project/commit/d8354d63db66e5d67d74b24b1611b578700f1134
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/pr114901.ll
Log Message:
-----------
[VectorCombine] Extend test coverage for #114901 with commuted test case
Commit: cab606c30661a746b2513a8330e0c8eca771913e
https://github.com/llvm/llvm-project/commit/cab606c30661a746b2513a8330e0c8eca771913e
Author: hev <wangrui at loongson.cn>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
M llvm/test/CodeGen/LoongArch/merge-load-store.ll
Log Message:
-----------
[LoongArch] Enable alias analysis by default (#114980)
Enable use of alias analysis during code generation.
Commit: d8139ae50f72046a2fce36055d8dc936b50d20ef
https://github.com/llvm/llvm-project/commit/d8139ae50f72046a2fce36055d8dc936b50d20ef
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
Log Message:
-----------
[lldb][test] Use -gdwarf to fix same CU breakpoint test on Windows on Arm
clang when given -g on Windows produces a PDB file. For whatever reason,
the test doesn't work with that.
-gdwarf produces DWARF regardless of platform.
Fixes 803f957e87e4083f6d61c8991171eeeaf0e6bd61.
Commit: 5a062191f7b9467aaddb6fe4b84c16e60fe85cc8
https://github.com/llvm/llvm-project/commit/5a062191f7b9467aaddb6fe4b84c16e60fe85cc8
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
A llvm/test/CodeGen/SPIRV/pointers/OpExtInst-OpenCL_std-ptr-types.ll
Log Message:
-----------
[SPIR-V] Ensure correct pointee types of some OpenCL Extended Instructions' pointer arguments (#114846)
OpenCL Extended Instruction Set Specification defines relations between
return/operand types and pointee type of pointer arguments in case of
remquo, fract, frexp, lgamma_r, modf, sincos and prefetch instructions
(https://registry.khronos.org/SPIR-V/specs/unified1/OpenCL.ExtendedInstructionSet.100.html).
This PR ensures correct pointee types of those OpenCL Extended
Instructions' pointer arguments.
Commit: 38fffa630ee80163dc65e759392ad29798905679
https://github.com/llvm/llvm-project/commit/38fffa630ee80163dc65e759392ad29798905679
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/test/CodeGen/PowerPC/altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
M clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
M clang/test/CodeGen/PowerPC/ppc-emmintrin.c
M clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init-no-parentheses.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init.c
M clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/SystemZ/zvector2.c
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vbmi2-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/avx512vlvbmi2-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
M clang/test/CodeGen/X86/xop-builtins-cmp.c
M clang/test/CodeGen/X86/xop-builtins.c
M clang/test/CodeGen/aarch64-neon-3v.c
M clang/test/CodeGen/aarch64-neon-intrinsics.c
M clang/test/CodeGen/aarch64-neon-misc.c
M clang/test/CodeGen/aarch64-neon-shifts.c
M clang/test/CodeGen/aarch64-neon-tbl.c
M clang/test/CodeGen/aarch64-poly64.c
M clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c
M clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/arm-bf16-convert-intrinsics.c
M clang/test/CodeGen/arm-mve-intrinsics/absneg.c
M clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
M clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
M clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/vornq.c
M clang/test/CodeGen/arm-neon-shifts.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGen/builtinshufflevector2.c
M clang/test/CodeGen/const-init.c
M clang/test/CodeGen/matrix-type-operators.c
M clang/test/CodeGen/neon-immediate-ubsan.c
M clang/test/CodeGen/nofpclass.c
M clang/test/CodeGen/ppc-vec_ct-truncate.c
M clang/test/CodeGen/variadic-nvptx.c
M clang/test/CodeGen/vecshift.c
M clang/test/CodeGen/vector-scalar.c
M clang/test/CodeGenCXX/auto-var-init.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenCXX/ext-vector-type-conditional.cpp
M clang/test/CodeGenCXX/matrix-type-builtins.cpp
M clang/test/CodeGenCXX/matrix-type-operators.cpp
M clang/test/CodeGenCXX/vector-size-conditional.cpp
M clang/test/CodeGenCXX/vector-splat-conversion.cpp
M clang/test/CodeGenHLSL/BasicFeatures/standard_conversion_sequences.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenOpenCL/bool_cast.cl
M clang/test/CodeGenOpenCL/logical-ops.cl
M clang/test/CodeGenOpenCL/partial_initializer.cl
M clang/test/CodeGenOpenCL/shifts.cl
M clang/test/CodeGenOpenCL/vector_literals.cl
M clang/test/Headers/__clang_hip_math_deprecated.hip
M clang/test/Headers/wasm.c
M llvm/lib/IR/AsmWriter.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/logicalop.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/div.ll
M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
M llvm/test/Analysis/CostModel/AMDGPU/fneg.ll
M llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll
M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
M llvm/test/Analysis/CostModel/AMDGPU/rem.ll
M llvm/test/Analysis/CostModel/ARM/divrem.ll
M llvm/test/Analysis/CostModel/ARM/logicalop.ll
M llvm/test/Analysis/CostModel/PowerPC/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/arith-int.ll
M llvm/test/Analysis/CostModel/RISCV/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
M llvm/test/Analysis/CostModel/SystemZ/divrem-pow2.ll
M llvm/test/Analysis/CostModel/SystemZ/logicalop.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
M llvm/test/Analysis/CostModel/X86/div-codesize.ll
M llvm/test/Analysis/CostModel/X86/div-latency.ll
M llvm/test/Analysis/CostModel/X86/div-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/div.ll
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Analysis/CostModel/X86/logicalop.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul-codesize.ll
M llvm/test/Analysis/CostModel/X86/mul-latency.ll
M llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul.ll
M llvm/test/Analysis/CostModel/X86/rem-codesize.ll
M llvm/test/Analysis/CostModel/X86/rem-latency.ll
M llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
M llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll
M llvm/test/Analysis/CostModel/X86/vdiv-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
M llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
M llvm/test/Analysis/DemandedBits/vectors.ll
M llvm/test/Analysis/ValueTracking/known-bits.ll
M llvm/test/Analysis/ValueTracking/known-fpclass.ll
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
M llvm/test/Analysis/ValueTracking/knownbits-and-or-xor-lowbit.ll
M llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll
M llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
M llvm/test/Analysis/ValueTracking/knownzero-shift.ll
M llvm/test/Analysis/ValueTracking/numsignbits-shl.ll
M llvm/test/Assembler/ConstantExprFold.ll
M llvm/test/Assembler/constant-splat.ll
M llvm/test/Assembler/opaque-ptr.ll
M llvm/test/Bitcode/constantsTest.3.2.ll
M llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/CodeGen/ARM/vector-promotion.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll
M llvm/test/CodeGen/NVPTX/variadics-lowering.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll
M llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
M llvm/test/CodeGen/X86/codegen-prepare-extload.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_tbl.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/sse2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/sse41-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/sse41-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
M llvm/test/Instrumentation/MemorySanitizer/reduce.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-track-origins-neon.ll
M llvm/test/Instrumentation/MemorySanitizer/vector_arith.ll
M llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
M llvm/test/Transforms/AggressiveInstCombine/ARM/fptosisat.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/fptosisat.ll
M llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
M llvm/test/Transforms/AggressiveInstCombine/popcount.ll
M llvm/test/Transforms/AggressiveInstCombine/trunc_multi_uses.ll
M llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll
M llvm/test/Transforms/Attributor/nofpclass-powi.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info-vec.ll
M llvm/test/Transforms/BDCE/binops-multiuse.ll
M llvm/test/Transforms/BDCE/dead-uses.ll
M llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
M llvm/test/Transforms/BDCE/vectors.ll
M llvm/test/Transforms/CodeGenPrepare/X86/fold-loop-of-urem.ll
M llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
M llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll
M llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll
M llvm/test/Transforms/ConstraintElimination/geps-ptrvector.ll
M llvm/test/Transforms/ConstraintElimination/vector-compares.ll
M llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
M llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
M llvm/test/Transforms/DeadStoreElimination/X86/gather-null-pointer.ll
M llvm/test/Transforms/DeadStoreElimination/masked-dead-store.ll
M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
M llvm/test/Transforms/EarlyCSE/commute.ll
M llvm/test/Transforms/EarlyCSE/gep.ll
M llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll
M llvm/test/Transforms/GVN/non-integral-pointers.ll
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M llvm/test/Transforms/InstCombine/shift-sra.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/shl-bo.ll
M llvm/test/Transforms/InstCombine/shl-demand.ll
M llvm/test/Transforms/InstCombine/shl-sub.ll
M llvm/test/Transforms/InstCombine/shl-unsigned-cmp-const.ll
M llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
M llvm/test/Transforms/InstCombine/shuffle_select.ll
M llvm/test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/signed-mul-lack-of-overflow-check-via-mul-sdiv.ll
M llvm/test/Transforms/InstCombine/signed-truncation-check.ll
M llvm/test/Transforms/InstCombine/signext.ll
M llvm/test/Transforms/InstCombine/signmask-of-sext-vs-of-shl-of-zext.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
M llvm/test/Transforms/InstCombine/smin-icmp.ll
M llvm/test/Transforms/InstCombine/sqrt.ll
M llvm/test/Transforms/InstCombine/ssub-with-overflow.ll
M llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
M llvm/test/Transforms/InstCombine/sub-lshr-or-to-icmp-select.ll
M llvm/test/Transforms/InstCombine/sub-not.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
M llvm/test/Transforms/InstCombine/sub-xor.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/InstCombine/trunc-binop-ext.ll
M llvm/test/Transforms/InstCombine/trunc-demand.ll
M llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
M llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll
M llvm/test/Transforms/InstCombine/trunc.ll
M llvm/test/Transforms/InstCombine/truncating-saturate.ll
M llvm/test/Transforms/InstCombine/uadd-with-overflow.ll
M llvm/test/Transforms/InstCombine/uaddo.ll
M llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
M llvm/test/Transforms/InstCombine/umin_cttz_ctlz.ll
M llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll
M llvm/test/Transforms/InstCombine/unsigned-add-lack-of-overflow-check-via-xor.ll
M llvm/test/Transforms/InstCombine/unsigned-add-lack-of-overflow-check.ll
M llvm/test/Transforms/InstCombine/unsigned-add-overflow-check-via-xor.ll
M llvm/test/Transforms/InstCombine/unsigned-add-overflow-check.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-mul-udiv.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
M llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
M llvm/test/Transforms/InstCombine/variable-signext-of-variable-high-bit-extraction.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_phi_extract.ll
M llvm/test/Transforms/InstCombine/vec_sext.ll
M llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
M llvm/test/Transforms/InstCombine/vec_udiv_to_shift.ll
M llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vector-casts.ll
M llvm/test/Transforms/InstCombine/vector-mul.ll
M llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll
M llvm/test/Transforms/InstCombine/vector-trunc.ll
M llvm/test/Transforms/InstCombine/vector-udiv.ll
M llvm/test/Transforms/InstCombine/vector-urem.ll
M llvm/test/Transforms/InstCombine/vector-xor.ll
M llvm/test/Transforms/InstCombine/with_overflow.ll
M llvm/test/Transforms/InstCombine/xor-and-or.ll
M llvm/test/Transforms/InstCombine/xor-ashr.ll
M llvm/test/Transforms/InstCombine/xor-icmps.ll
M llvm/test/Transforms/InstCombine/xor-of-or.ll
M llvm/test/Transforms/InstCombine/xor.ll
M llvm/test/Transforms/InstCombine/xor2.ll
M llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
M llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
M llvm/test/Transforms/InstCombine/zext.ll
M llvm/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
M llvm/test/Transforms/InstSimplify/AndOrXor.ll
M llvm/test/Transforms/InstSimplify/ConstProp/ARM/mve-vctp.ll
M llvm/test/Transforms/InstSimplify/ConstProp/active-lane-mask.ll
M llvm/test/Transforms/InstSimplify/ConstProp/bitcast.ll
M llvm/test/Transforms/InstSimplify/ConstProp/cast.ll
M llvm/test/Transforms/InstSimplify/ConstProp/saturating-add-sub.ll
M llvm/test/Transforms/InstSimplify/ConstProp/vectorgep-crash.ll
M llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll
M llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector.ll
M llvm/test/Transforms/InstSimplify/abs_intrinsic.ll
M llvm/test/Transforms/InstSimplify/add_vp.ll
M llvm/test/Transforms/InstSimplify/addsub.ll
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
M llvm/test/Transforms/InstSimplify/bitreverse-fold.ll
M llvm/test/Transforms/InstSimplify/call.ll
M llvm/test/Transforms/InstSimplify/canonicalize.ll
M llvm/test/Transforms/InstSimplify/cast-unsigned-icmp-cmp-0.ll
M llvm/test/Transforms/InstSimplify/cmp-vec-fast-path.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/constantfold-add-nuw-allones-to-allones.ll
M llvm/test/Transforms/InstSimplify/constantfold-shl-nuw-C-to-C.ll
M llvm/test/Transforms/InstSimplify/ctpop-pow2.ll
M llvm/test/Transforms/InstSimplify/div.ll
M llvm/test/Transforms/InstSimplify/exp10.ll
M llvm/test/Transforms/InstSimplify/fast-math-strictfp.ll
M llvm/test/Transforms/InstSimplify/fast-math.ll
M llvm/test/Transforms/InstSimplify/fdiv.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic-strictfp.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
M llvm/test/Transforms/InstSimplify/floating-point-compare.ll
M llvm/test/Transforms/InstSimplify/fminmax-folds.ll
M llvm/test/Transforms/InstSimplify/fp-nan.ll
M llvm/test/Transforms/InstSimplify/fptoi-range.ll
M llvm/test/Transforms/InstSimplify/frexp.ll
M llvm/test/Transforms/InstSimplify/gep.ll
M llvm/test/Transforms/InstSimplify/icmp-bool-constant.ll
M llvm/test/Transforms/InstSimplify/icmp-constant.ll
M llvm/test/Transforms/InstSimplify/icmp-not-bool-constant.ll
M llvm/test/Transforms/InstSimplify/icmp.ll
M llvm/test/Transforms/InstSimplify/implies.ll
M llvm/test/Transforms/InstSimplify/insertelement.ll
M llvm/test/Transforms/InstSimplify/known-never-infinity.ll
M llvm/test/Transforms/InstSimplify/known-non-zero.ll
M llvm/test/Transforms/InstSimplify/maxmin_intrinsics.ll
M llvm/test/Transforms/InstSimplify/negate.ll
M llvm/test/Transforms/InstSimplify/or-icmps-same-ops.ll
M llvm/test/Transforms/InstSimplify/or.ll
M llvm/test/Transforms/InstSimplify/pr28725.ll
M llvm/test/Transforms/InstSimplify/ptrmask.ll
M llvm/test/Transforms/InstSimplify/rem.ll
M llvm/test/Transforms/InstSimplify/returned.ll
M llvm/test/Transforms/InstSimplify/saturating-add-sub.ll
M llvm/test/Transforms/InstSimplify/sdiv.ll
M llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
M llvm/test/Transforms/InstSimplify/select-logical.ll
M llvm/test/Transforms/InstSimplify/select.ll
M llvm/test/Transforms/InstSimplify/select_or_and.ll
M llvm/test/Transforms/InstSimplify/shift-knownbits.ll
M llvm/test/Transforms/InstSimplify/shift.ll
M llvm/test/Transforms/InstSimplify/shr-nop.ll
M llvm/test/Transforms/InstSimplify/shufflevector-inseltpoison.ll
M llvm/test/Transforms/InstSimplify/shufflevector.ll
M llvm/test/Transforms/InstSimplify/strictfp-fadd.ll
M llvm/test/Transforms/InstSimplify/uscmp.ll
M llvm/test/Transforms/InstSimplify/vec-cmp.ll
M llvm/test/Transforms/InstSimplify/vec-icmp-of-cast.ll
M llvm/test/Transforms/InstSimplify/vector_gep.ll
M llvm/test/Transforms/InstSimplify/xor.ll
M llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extract-shuffle-changes.ll
M llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
M llvm/test/Transforms/LoopLoadElim/type-mismatch.ll
M llvm/test/Transforms/LoopUnroll/ARM/mve-upperbound.ll
M llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
M llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/AArch64/streaming-compatible-sve-no-maximize-bandwidth.ll
M llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/gep-use-outside-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-sink-store-across-load.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/pr55096-scalarize-add.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
M llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-pr39099.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
M llvm/test/Transforms/LoopVectorize/assume.ll
M llvm/test/Transforms/LoopVectorize/blend-in-header.ll
M llvm/test/Transforms/LoopVectorize/bsd_regex.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/create-induction-resume.ll
M llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-trunc-induction-steps.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-multiply-recurrences.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
M llvm/test/Transforms/LoopVectorize/if-pred-not-when-safe.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/induction_plus.ll
M llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-3.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/loop-scalars.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr39417-optsize-scevchecks.ll
M llvm/test/Transforms/LoopVectorize/pr44488-predication.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/pr45525.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll
M llvm/test/Transforms/LoopVectorize/pr66616.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-min-max.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-order.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/reduction.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scalarize-masked-call.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-reduction-start-value-may-be-undef-or-poison.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-alloca-in-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
M llvm/test/Transforms/LoopVectorize/trunc-shifts.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
M llvm/test/Transforms/LoopVectorize/vector-intrinsic-call-cost.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
M llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int-row-major.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-add-sub-double-row-major.ll
M llvm/test/Transforms/MemCpyOpt/form-memset.ll
M llvm/test/Transforms/NewGVN/completeness.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/predicated-reduction.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
M llvm/test/Transforms/PhaseOrdering/X86/shuffle-inseltpoison.ll
M llvm/test/Transforms/PhaseOrdering/X86/shuffle.ll
M llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
M llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp-load-store.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp.ll
M llvm/test/Transforms/Reassociate/fast-ReassociateVector.ll
M llvm/test/Transforms/Reassociate/negation.ll
M llvm/test/Transforms/Reassociate/xor_reassoc.ll
M llvm/test/Transforms/RewriteStatepointsForGC/vector-nonlive-clobber.ll
M llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll
M llvm/test/Transforms/SCCP/intrinsics.ll
M llvm/test/Transforms/SCCP/ip-ranges-casts.ll
M llvm/test/Transforms/SCCP/overdefined-ext.ll
M llvm/test/Transforms/SCCP/trunc-nuw-nsw-flags.ll
M llvm/test/Transforms/SCCP/vector-bitcast.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/external-use-icmp.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec15-base.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-min-max.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/floating-point.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/getpointerschaincost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/load-store.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/minbw-with-and-and-scalar-trunc.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/phi-const.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduced-value-repeated-and-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-stores-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/trunc-to-large-than-bw.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec15-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-and-const-load.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-div.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
M llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
M llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
M llvm/test/Transforms/SLPVectorizer/X86/combined-stores-chains.ll
M llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
M llvm/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
M llvm/test/Transforms/SLPVectorizer/X86/cse.ll
M llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
M llvm/test/Transforms/SLPVectorizer/X86/different-vec-widths.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-used-across-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gep-nodes-with-non-gep-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/gep.ll
M llvm/test/Transforms/SLPVectorizer/X86/geps-non-pow-2.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
M llvm/test/Transforms/SLPVectorizer/X86/long_chains.ll
M llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
M llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
M llvm/test/Transforms/SLPVectorizer/X86/mul64.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
M llvm/test/Transforms/SLPVectorizer/X86/powof2div.ll
M llvm/test/Transforms/SLPVectorizer/X86/powof2mul.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr23510.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr48879-sroa.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr49933.ll
M llvm/test/Transforms/SLPVectorizer/X86/propagate_ir_flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-insertelement.ll
M llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-masked-gather.ll
M llvm/test/Transforms/SLPVectorizer/X86/resched.ll
M llvm/test/Transforms/SLPVectorizer/X86/reuse-extracts-in-wider-vect.ll
M llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
M llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
M llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll
M llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
M llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
M llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
M llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
M llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
M llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
M llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
M llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
M llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
M llvm/test/Transforms/SLPVectorizer/phi-node-bitwidt-op-not.ll
M llvm/test/Transforms/SLPVectorizer/reduction-whole-regs-loads.ll
M llvm/test/Transforms/SLPVectorizer/reduction_loads.ll
M llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
M llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
M llvm/test/Transforms/SLPVectorizer/revec-fix-109835.ll
M llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
M llvm/test/Transforms/SROA/tbaa-struct3.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-load.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-store.ll
M llvm/test/Transforms/Scalarizer/phi-unreachable-pred.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-select.ll
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
M llvm/test/Transforms/SimplifyCFG/preserve-store-alignment.ll
M llvm/test/Transforms/StraightLineStrengthReduce/slsr-add.ll
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
M llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization-shufflevector-splat.ll
M llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
M llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
M llvm/test/Transforms/VectorCombine/X86/scalarize-cmp.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle.ll
M llvm/test/tools/llvm-reduce/reduce-opcodes.ll
M llvm/test/tools/llvm-reduce/reduce-operands-fp.ll
M llvm/test/tools/llvm-reduce/reduce-operands-int.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)
Commit: e3a0775651190a23d8234615b9fdadd81c1c24bc
https://github.com/llvm/llvm-project/commit/e3a0775651190a23d8234615b9fdadd81c1c24bc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/extract-cmp-binop.ll
M llvm/test/Transforms/VectorCombine/X86/pr114901.ll
Log Message:
-----------
[VectorCombine] foldExtractedCmps - (re-)enable fold on non-commutative binops
#114901 exposed that foldExtractedCmps didn't account for non-commutative binops, and were disabled by 05e838f428555bcc4507bd37912da60ea9110ef6
This patch re-enables support for non-commutative binops by ensuring that the LHS/RHS arg order of the binop is retained.
Commit: f1f5220958eb02a7ca4aa21cb95df4746e91bc3b
https://github.com/llvm/llvm-project/commit/f1f5220958eb02a7ca4aa21cb95df4746e91bc3b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/include/clocale
M libcxx/include/cstdint
Log Message:
-----------
[libc++] Only include the system <stdint.h> and <locale.h> if they exist (#115017)
Prior to aa7f377c96, we only did an #include_next of those system
headers if they existed. After removing those headers from libc++, we
started assuming that the system provided the headers because we
unconditionally started including them. This patch fixes that.
Commit: 28452acac05de8dc64aa7ba76af70ac541667cdd
https://github.com/llvm/llvm-project/commit/28452acac05de8dc64aa7ba76af70ac541667cdd
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] delayed privatisation for TASK (#114785)
This uses essentially an identical implementation to that used for
ParallelOp. The private variable allocation and deallocation use shared
functions to avoid code duplication. FIRSTPRIVATE variable copying uses
duplicated code for now because I anticipate the implementation
diverging in the near future once I store data for firstprivate
variables in the task description structure.
After enabling delayed privatisation for TASK in flang, one more test in
the fujitsu test suite passes (I haven't looked into why).
Commit: 88e9b373c0d7184b08c755024cce0778d18f0306
https://github.com/llvm/llvm-project/commit/88e9b373c0d7184b08c755024cce0778d18f0306
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
A llvm/test/Transforms/FunctionSpecialization/solver-constants.ll
A llvm/test/Transforms/FunctionSpecialization/solver-dead-blocks.ll
Log Message:
-----------
[FuncSpec] Query SCCPSolver in more places (#114964)
When traversing the use-def chain of an Argument in a candidate
specialization, also query the SCCPSolver to see if a Value is constant.
This allows us to better estimate the codesize savings of a candidate in
the presence of instructions that are a user of the argument we are
estimating savings for which also use arguments that have been found
constant by IPSCCP.
Similarly when estimating the dead basic blocks from branch and switch
instructions which become constant, also query the SCCPSolver to see if
a predecessor is unreachable.
Commit: 246b57cb2086b22ad8b41051c77e86ef478053a1
https://github.com/llvm/llvm-project/commit/246b57cb2086b22ad8b41051c77e86ef478053a1
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/test/Lower/PowerPC/ppc-vec-cmp.f90
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-perm.f90
M flang/test/Lower/PowerPC/ppc-vec-sel.f90
M flang/test/Lower/PowerPC/ppc-vec-shift.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
Log Message:
-----------
Fix tests in flang/test/Lower/PowerPC after splat change.
Commit: 79f4d8f0145d72dff8c33745f35d45c74ecb3fdf
https://github.com/llvm/llvm-project/commit/79f4d8f0145d72dff8c33745f35d45c74ecb3fdf
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/ast-dump-decl.cpp
R clang/test/ASTMerge/class-template-spec/Inputs/class-template-spec.cpp
R clang/test/ASTMerge/class-template-spec/test.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
Log Message:
-----------
Revert "Reapply "[Clang][Sema] Always use latest redeclaration of primary template" (#114569)" (#115156)
This reverts commit b24650e814e55d90acfc40acf045456c98f32b9c.
Commit: 2904f809cd1bf2651d6eceb2ad86553f407bf530
https://github.com/llvm/llvm-project/commit/2904f809cd1bf2651d6eceb2ad86553f407bf530
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
Log Message:
-----------
Revert "[Clang][Sema] Use the correct injected template arguments for partial specializations when collecting multi-level template argument lists (#112381)" (#115157)
This reverts commit 9381c6fd04cc16a7606633f57c96c11e58181ddb.
Commit: fbd89bcc6647ed611e579d8f9c38c97b8e6f7936
https://github.com/llvm/llvm-project/commit/fbd89bcc6647ed611e579d8f9c38c97b8e6f7936
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-lto-defaults.ll
A llvm/test/Transforms/PhaseOrdering/lto-argpromotion-ipsccp.ll
Log Message:
-----------
Reland "[LTO] Run Argument Promotion before IPSCCP" (#111853)
Run ArgumentPromotion before IPSCCP in the LTO pipeline, to expose more
constants to be propagated. We also run PostOrderFunctionAttrs to
improve the information available to ArgumentPromotion's alias analysis,
and SROA to clean up allocas.
Relands #111163.
Commit: 44ab3805b5a4a1f37e186e79b83c5cdc838312ed
https://github.com/llvm/llvm-project/commit/44ab3805b5a4a1f37e186e79b83c5cdc838312ed
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
R clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
R clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/Modules/cxx-templates.cpp
Log Message:
-----------
Revert "Reapply "[Clang][Sema] Refactor collection of multi-level template argument lists (#106585, #111173)" (#111852)" (#115159)
This reverts commit 2bb3d3a3f32ffaef3d9b6a27db7f1941f0cb1136.
Commit: 2f743ac52e945e155ff3cb1f8ca5287b306b831e
https://github.com/llvm/llvm-project/commit/2f743ac52e945e155ff3cb1f8ca5287b306b831e
Author: Ilya Enkovich <ilya.enkovich at intel.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/AMX/AMX.td
M mlir/include/mlir/Dialect/AMX/AMXDialect.h
M mlir/include/mlir/Dialect/AMX/Transforms.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Dialect/AMX/IR/AMXDialect.cpp
M mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Target/LLVMIR/TypeFromLLVM.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/test/Dialect/AMX/invalid.mlir
M mlir/test/Dialect/AMX/legalize-for-llvm.mlir
M mlir/test/Dialect/AMX/roundtrip.mlir
Log Message:
-----------
[MLIR] [AMX] Utilize x86_amx type for AMX dialect in MLIR. (#111197)
This patch is intended to resolve #109481 and improve the usability of
the AMX dialect.
In LLVM IR, AMX intrinsics use `x86_amx` which is one of the primitive
types. This type is supposed to be used for AMX intrinsic calls and no
other operations. AMX dialect of MLIR uses regular 2D vector types,
which are then lowered to arrays of vectors in the LLVMIR dialect. This
creates an inconsistency in the types used in the LLVMIR dialect and
LLVMIR. Translation of AMX intrinsic calls to LLVM IR doesn't require
result types to match and that is where tile loads and mul operation
results get `x86_amx` type. This works in very simple cases when mul and
tile store operations directly consume the result of another AMX
intrinsic call, but it doesn't work when an argument is a block argument
(phi node).
In addition to translation problems, this inconsistency between types
used in MLIR and LLVM IR makes MLIR verification and transformation
quite problematic. Both `amx.tileload` and `vector::transfer_read` can
load values of the same type, but only one of them can be used in AMX
operations. In general, by looking at a type of value, we cannot
determine if it can only be used for AMX operations or contrary can be
used in other operations but AMX ones.
To remove this inconsistency and make AMX operations more explicit in
their limitations, I propose to add `LLVMX86AMXType` type to the LLVMIR
dialect to match `x86_amx` type in LLVM IR, and introduce
`amx::TileType` to be used by AMX operations in MLIR. This resolves
translation problems for AMX usage with phi nodes and provides proper
type verification in MLIR for AMX operations.
P.S. This patch also adds missing FP16 support. It's trivial but
unrelated to type system changes, so let me know if I should submit it
separately.
---------
Signed-off-by: Ilya Enkovich <ilya.enkovich at intel.com>
Commit: 9b016e3cb2859ef06f0301ebbc48df294b2356dc
https://github.com/llvm/llvm-project/commit/9b016e3cb2859ef06f0301ebbc48df294b2356dc
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/test/CodeGen/Thumb2/mve-vcmla.ll
Log Message:
-----------
[ARM] Add early-clobber to MVE VCMLA.f32 (#114995)
This instruction (but not the f16 variant) cannot us the same register
for the output as either of the inputs, so it needs to be marked as
early-clobber.
Commit: 5d8be4c036aa5ce4a94f1f37a9155d5c877e23db
https://github.com/llvm/llvm-project/commit/5d8be4c036aa5ce4a94f1f37a9155d5c877e23db
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/apple.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/__locale_dir/locale_base_api/freebsd.h
M libcxx/include/locale
M libcxx/src/iostream.cpp
M libcxx/src/locale.cpp
Log Message:
-----------
[libc++] Define an internal locale API as a shim on top of the current one (#114596)
Our current locale base API is a mix of non-reserved system names that
we incorrectly (re)define and internal functions and macros starting
with __libcpp. This patch introduces a function-based internal interface
to isolate the rest of the code base from that mess, so that we can work
on refactoring how each platform implements the base API in subsequent
patches. This makes it possible to refactor how each platform implements
the base localization API without impacting the rest of the code base.
Commit: 86e4beb702fde407a35938a1c37279a61c0291e7
https://github.com/llvm/llvm-project/commit/86e4beb702fde407a35938a1c37279a61c0291e7
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/Mips.h
M clang/test/CodeGen/target-data.c
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
A llvm/test/CodeGen/Mips/data-layout.ll
M llvm/test/CodeGen/Mips/implicit-sret.ll
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
Log Message:
-----------
[MIPS] LLVM data layout give i128 an alignment of 16 for mips64 (#112084)
Fix parts of #102783.
Commit: f61a8bc305d60f1ab04225e2b210d8b3d9c97eb8
https://github.com/llvm/llvm-project/commit/f61a8bc305d60f1ab04225e2b210d8b3d9c97eb8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/builtin_test_helpers.h
Log Message:
-----------
[clang][x86] Prevent signed/unsigned comparison warnings on constexpr m128i/m256i/m512i match helpers.
These matches are here to help match hex patterns so consistently match with unsigned uint64_t types
Commit: 7585e2fd3caee30d5332c93995b7a6f51ab06660
https://github.com/llvm/llvm-project/commit/7585e2fd3caee30d5332c93995b7a6f51ab06660
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_movepi64_pi64 and _mm_move_epi64
Commit: fb90733e196039b0a77f43af98c42c9267a31e07
https://github.com/llvm/llvm-project/commit/fb90733e196039b0a77f43af98c42c9267a31e07
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
A clang/test/SemaHLSL/BuiltIns/firstbithigh-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/firstbithigh.ll
A llvm/test/CodeGen/DirectX/firstbitshigh_error.ll
A llvm/test/CodeGen/DirectX/firstbituhigh_error.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/firstbithigh.ll
Log Message:
-----------
[HLSL] implement elementwise firstbithigh hlsl builtin (#111082)
Implements elementwise firstbithigh hlsl builtin.
Implements firstbituhigh intrinsic for spirv and directx, which handles
unsigned integers
Implements firstbitshigh intrinsic for spirv and directx, which handles
signed integers.
Fixes #113486
Closes #99115
Commit: b5d8a03de453b79ca3c0bf841931bcaacf2fc830
https://github.com/llvm/llvm-project/commit/b5d8a03de453b79ca3c0bf841931bcaacf2fc830
Author: Rin Dobrescu <irina.dobrescu at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
Log Message:
-----------
[AArch64] Add missing ASIMD FP convert instructions to scheduling model (#115146)
Some ASIMD FP convert instructions have incorrect scheduling
information. These instructions currently have latency 2, throughput 4
and utilise pipeline V. This patch corrects the scheduling models to
match the relevant Software Optimization Guide.
The V1 and V2 Software Optimization Guide show that ASIMD FP convert
instructions should all utilise pipelines V02. Their execution latency
and throughput should also differ depending on form. See section 3.17
"ASIMD floating-point instructions" in the Neoverse-V1 and Neoverse-V2
Software Optimization Guide for characteristics of instruction
performance.
Reference:
- V1 SOG: https://developer.arm.com/documentation/109897/latest/
- V2 SOG: https://developer.arm.com/documentation/109898/latest/
Commit: 8699f301ae70ce402618c061b6c45a99e31c5f5e
https://github.com/llvm/llvm-project/commit/8699f301ae70ce402618c061b6c45a99e31c5f5e
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan] Add more socket interceptors (#115020)
Adds getaddrinfo, getnameinfo, bind, listen, accept and connect
Commit: 76422385c3081475ed1bf0e23aa2f3913e66c5b8
https://github.com/llvm/llvm-project/commit/76422385c3081475ed1bf0e23aa2f3913e66c5b8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
Log Message:
-----------
[SLP]Support reordered buildvector nodes for better clustering
Patch adds reordering of the buildvector nodes for better clustering of
the compatible operations and future vectorization. Includes basic cost
estimation and if the transformation is not profitable - reverts it.
AVX512, -O3+LTO
Metric: size..text
Program size..text
results results0 diff
test-suite :: External/SPEC/CINT2006/401.bzip2/401.bzip2.test 74565.00 75701.00 1.5%
test-suite :: External/SPEC/CINT2017rate/541.leela_r/541.leela_r.test 75773.00 76397.00 0.8%
test-suite :: External/SPEC/CINT2017speed/641.leela_s/641.leela_s.test 75773.00 76397.00 0.8%
test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 2014462.00 2024494.00 0.5%
test-suite :: MultiSource/Applications/JM/ldecod/ldecod.test 395219.00 396979.00 0.4%
test-suite :: MultiSource/Applications/JM/lencod/lencod.test 857795.00 859667.00 0.2%
test-suite :: External/SPEC/CINT2006/464.h264ref/464.h264ref.test 800472.00 802440.00 0.2%
test-suite :: External/SPEC/CFP2006/447.dealII/447.dealII.test 590699.00 591403.00 0.1%
test-suite :: MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame.test 203006.00 203102.00 0.0%
test-suite :: MultiSource/Benchmarks/DOE-ProxyApps-C/miniGMG/miniGMG.test 42408.00 42424.00 0.0%
test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12451575.00 12451927.00 0.0%
test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 1396480.00 1396448.00 -0.0%
test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 1396480.00 1396448.00 -0.0%
test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 1047708.00 1047580.00 -0.0%
test-suite :: MultiSource/Benchmarks/MiBench/consumer-jpeg/consumer-jpeg.test 111344.00 111328.00 -0.0%
test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test 1087660.00 1087500.00 -0.0%
test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test 280664.00 280616.00 -0.0%
test-suite :: MultiSource/Applications/sqlite3/sqlite3.test 502646.00 502006.00 -0.1%
test-suite :: MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4.test 1033135.00 1031567.00 -0.2%
test-suite :: External/SPEC/CINT2017rate/500.perlbench_r/500.perlbench_r.test 2070917.00 2065845.00 -0.2%
test-suite :: External/SPEC/CINT2017speed/600.perlbench_s/600.perlbench_s.test 2070917.00 2065845.00 -0.2%
test-suite :: External/SPEC/CINT2006/473.astar/473.astar.test 33893.00 33797.00 -0.3%
test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 39677.00 39549.00 -0.3%
test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 39674.00 39546.00 -0.3%
test-suite :: MultiSource/Benchmarks/MiBench/security-blowfish/security-blowfish.test 11560.00 11512.00 -0.4%
test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 653867.00 649275.00 -0.7%
test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 653867.00 649275.00 -0.7%
CINT2006/401.bzip2 - extra code vectorized
CINT2017rate/541.leela_r
CINT2017speed/641.leela_s - function
_ZN9FastBoard25get_pattern3_augment_specEiib not inlined anymore, better
vectorization
CFP2017rate/510.parest_r - better vectorization
JM/ldecod - better vectorization
JM/lencod - same
CINT2006/464.h264ref - extra code vectorized
CFP2006/447.dealII - extra vector code
MiBench/consumer-lame - vectorized 2 loops previously scalar
DOE-ProxyApps-C/miniGMG - small changes
Benchmarks/7zip - extra code vectorized, better vectorization
CFP2017rate/526.blender_r - extra vectorization
CFP2017speed/638.imagick_s
CFP2017rate/538.imagick_r - extra vectorization
MiBench/consumer-jpeg - extra vectorization
CINT2006/400.perlbench - extra vectorization
Prolangs-C/TimberWolfMC - small variations
Applications/sqlite3 - extra function vectorized and inlined
Benchmarks/tramp3d-v4 - extra code vectorized
CINT2017rate/500.perlbench_r
CINT2017speed/600.perlbench_s - extra code vectorized, function digcpy gets
vectorized and inlined
CINT2006/473.astar - extra code vectorized
MiBench/telecomm-gsm - extra code vectorized, better vector code
mediabench/gsm - same
MiBench/security-blowfish - extra code vectorized
CINT2017speed/625.x264_s
CINT2017rate/525.x264_r - sub4x4_dct function vectorized and gets
inlined
RISCV-V, SiFive-p670, O3+LTO
CFP2017rate/510.parest_r - extra vectorization
CFP2017rate/526.blender_r - extra vectorization
MiBench/consumer-lame - extra vectorized code
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/114284
Commit: c10d4b492d981c96fa3269bc0fe0b3ea9b1ca486
https://github.com/llvm/llvm-project/commit/c10d4b492d981c96fa3269bc0fe0b3ea9b1ca486
Author: Dmitri Gribenko <gribozavr at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/AST/SYCLKernelInfo.h
Log Message:
-----------
[clang][SYCL] Add a missing include to make the header standalone
Commit: f548d39c3c751446d124c08769080214680d53ba
https://github.com/llvm/llvm-project/commit/f548d39c3c751446d124c08769080214680d53ba
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
Log Message:
-----------
[Clang][Test] Update test after #115159 (#115172)
After #111852 was reverted in #115159, two tests now fail because they
partially depend on its changes. This patch temporarily fixes the
failing cases by updating the expected output to match the actual
output. Once #111852 is relanded, this can be reverted.
Commit: 3aa2f63822c0d829c875aa41ca2fd0103939dfaf
https://github.com/llvm/llvm-project/commit/3aa2f63822c0d829c875aa41ca2fd0103939dfaf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_castps_pd/_mm_castps_si128/_mm_castsi128_pd/_mm_castsi128_ps intrinsics
Commit: f74aed793819bf9e0509e802f33c5e29c350540c
https://github.com/llvm/llvm-project/commit/f74aed793819bf9e0509e802f33c5e29c350540c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
A llvm/test/CodeGen/AArch64/trunc-nsw-nuw.ll
A llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
A llvm/test/CodeGen/X86/trunc-nsw-nuw.ll
Log Message:
-----------
[DAGCombiner] Add basic support for `trunc nsw/nuw` (#113808)
This patch adds basic support for `trunc nsw/nuw` in SDAG. It will allow
DAGCombiner to further eliminate in-reg `zext/sext` instructions.
Commit: 201d7607f87afff999b1257d27569a3053b85143
https://github.com/llvm/llvm-project/commit/201d7607f87afff999b1257d27569a3053b85143
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/Common/ErrorHandler.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Add context-aware diagnostic functions (#112319)
The current diagnostic functions log/warn/error/fatal lack a context
argument and call the global `lld::errorHandler()`, which prevents
multiple lld instances in one process.
This patch introduces context-aware replacements:
* log => Log(ctx)
* warn => Warn(ctx)
* errorOrWarn => Err(ctx)
* error => ErrAlways(ctx)
* fatal => Fatal(ctx)
Example: `errorOrWarn(toString(f) + "xxx")` => `Err(ctx) << f << "xxx"`.
(`toString(f)` is shortened to `f` as a bonus and may access `ctx`
without accessing the global variable (see `Target.cpp`)).
`ctx.e = &context->e;` can be replaced with a non-global Errorhandler
when `ctx` becomes a local variable.
(For the ELF port, the long term goal is to eliminate `error`. Most can
be straightforwardly converted to `Err(ctx)`.)
Commit: 83f92c33a4b4bd703882e7e9bb2c5efd15042b96
https://github.com/llvm/llvm-project/commit/83f92c33a4b4bd703882e7e9bb2c5efd15042b96
Author: dlav-sc <daniil.avdeev at syntacore.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
Log Message:
-----------
[RISCV] fix SP recovery in varargs functions (#114316)
This patch fixes sp recovery in the epilogue in varargs functions when
fp register is presented and second sp adjustment is applied.
Source of the issue: https://github.com/llvm/llvm-project/pull/110809
Commit: 9f3b6adb1508a714dc12aa020a20d813d9ab9f42
https://github.com/llvm/llvm-project/commit/9f3b6adb1508a714dc12aa020a20d813d9ab9f42
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Exit early if the graph is empty, NFC
No need to check anything if the graph is empty, just exit early.
Commit: 6219c8083904b49d09f466b703ca47891f978278
https://github.com/llvm/llvm-project/commit/6219c8083904b49d09f466b703ca47891f978278
Author: Duncan <duncpro at icloud.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/newhdrgen/yaml/unistd.yaml
M libc/spec/linux.td
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/pipe2.cpp
A libc/src/unistd/pipe2.h
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/pipe2_test.cpp
Log Message:
-----------
[libc] [unistd] implement pipe2 syscall wrapper (#114474)
Closes #85289
Co-authored-by: Michael Jones <michaelrj at google.com>
Commit: b7ee03ffb8696c4d81a5a97c61cb2149c17e6573
https://github.com/llvm/llvm-project/commit/b7ee03ffb8696c4d81a5a97c61cb2149c17e6573
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.h
Log Message:
-----------
[clang-include-fixer] Use heterogenous lookups with std::map (NFC) (#115113)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: c4dfa03f9f44fa183daabdd4e6d760a432ef6531
https://github.com/llvm/llvm-project/commit/c4dfa03f9f44fa183daabdd4e6d760a432ef6531
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/abseil/DurationRewriter.cpp
Log Message:
-----------
[clang-tidy] Call StringMap::find without constructing std::string (NFC) (#115114)
StringMap::find takes StringRef, so we don't need to allocate
temporary instances of std::string.
Commit: 18d2539ce674c1eabac187403257ae53ed2ee264
https://github.com/llvm/llvm-project/commit/18d2539ce674c1eabac187403257ae53ed2ee264
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp
Log Message:
-----------
[StaticAnalyzer] Simplify code with DenseMap::operator[] (NFC) (#115116)
Commit: 4d12a14357b136e996f8789786f1b76348b5582b
https://github.com/llvm/llvm-project/commit/4d12a14357b136e996f8789786f1b76348b5582b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
M llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/KCFI.cpp
M llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
Log Message:
-----------
[Instrumentation] Remove unused includes (NFC) (#115117)
Identified with misc-include-cleaner.
Commit: 57ab62a2aa80911391fd9ea49573b39e7e9aa0f0
https://github.com/llvm/llvm-project/commit/57ab62a2aa80911391fd9ea49573b39e7e9aa0f0
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
Log Message:
-----------
[flang] Add FIR AliasAnalysis alias() wrapper to allow external getSource() method (#115073)
Adding a wrapper around alias(mlir::Value lhs, mlir::Value rhs) to allow
user to provide Source objects.
Commit: efe87fbc9d52952dc7ee89579347cbf49ecfa609
https://github.com/llvm/llvm-project/commit/efe87fbc9d52952dc7ee89579347cbf49ecfa609
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
Log Message:
-----------
AMDGPU: Improve vector of pointer handling in amdgpu-promote-alloca (#114144)
Commit: 5dc8d61177225a86266beeedf09baa847f97edf0
https://github.com/llvm/llvm-project/commit/5dc8d61177225a86266beeedf09baa847f97edf0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Implement zexti32/zexti16 ComplexPatterns. (#115097)
Commit: 29e467fc78eb8b4308b57272ca4ad0d1f744f25f
https://github.com/llvm/llvm-project/commit/29e467fc78eb8b4308b57272ca4ad0d1f744f25f
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/Type.h
Log Message:
-----------
[llvm] Deprecate Type::getPointerTo() (#113331)
`llvm::Type::getPointerTo()` is no longer needed with opaque pointers in LLVM.
It may rather confuse new contributors to think that LLVM has typed pointers.
Commit: aa7941289ee5b7d9bdf47e1b0ebf2130a86d9522
https://github.com/llvm/llvm-project/commit/aa7941289ee5b7d9bdf47e1b0ebf2130a86d9522
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
A llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
Log Message:
-----------
AMDGPU: Fold copy of scalar add of frame index (#115058)
This is a pre-optimization to avoid a regression in a future
commit. Currently we almost always emit frame index with
a v_mov_b32 and use vector adds for the pointer operations. We
need to consider the users of the frame index (or rather, the
transitive users of derived pointer operations) to know whether
the value will be used in a vector or scalar context. This saves
an sgpr->vgpr copy.
This optimization could be more general for any opcode that's
trivially convertible from a scalar to vector form (although this
is a workaround for a proper regbankselect).
Commit: 3b0f506c87cf7cf32604c9592aeca3ede0e1f79e
https://github.com/llvm/llvm-project/commit/3b0f506c87cf7cf32604c9592aeca3ede0e1f79e
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
Log Message:
-----------
[AMDGPU] Support `nuw` and `nusw` in buffer fat pointer lowering (#115039)
This commit usis the `nuw` flag on `getelemnetptr` to set the `nuw` flag
on buffer offset additions, and also moves from `inbounds` to the looser
`nusw` for the existing case.
Commit: 270f7cf68ae64a42d7112c0319f33a1d913e6333
https://github.com/llvm/llvm-project/commit/270f7cf68ae64a42d7112c0319f33a1d913e6333
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP][Docs] Update OpenMP supported features table (#115106)
OpenMP features table: added 'allocator' modifier for 'allocate' clause
as a completed feature in OpenMP 5.1 Implementation Details.
Commit: 8dd9f206b518a97132f3e2489ccc93704e638353
https://github.com/llvm/llvm-project/commit/8dd9f206b518a97132f3e2489ccc93704e638353
Author: Pranav Kant <prka at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix mlir:VectorToSPIRV (#115188)
Commit: 4d4024e1edf354113e8d0d11661d466ae5b0bee7
https://github.com/llvm/llvm-project/commit/4d4024e1edf354113e8d0d11661d466ae5b0bee7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lldb/test/API/lit.cfg.py
M lldb/test/Shell/lit.cfg.py
M lldb/test/Unit/lit.cfg.py
M lldb/test/Unit/lit.site.cfg.py.in
Log Message:
-----------
[lldb] Set MallocNanoZone for all sanitizers when running tests
Disabling MallocNanoZone is necessary for both ASan and TSan.
Commit: 38cc03f78e3046837d8fc29d729bc2cee0c31e89
https://github.com/llvm/llvm-project/commit/38cc03f78e3046837d8fc29d729bc2cee0c31e89
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps5-linker.c
Log Message:
-----------
[PS5][Driver] Restore whole-archive state when `-fjmc` (#115181)
`--whole-archive` is passed to the linker to have it consume all objects
within the SIE Just My Code library, rather than just those that fulfil
outstanding references.
Prior to this change, `--no-whole-archive` was used to reset the
associated archive handling state in the linker, under the assumption
that `--whole-archive` wasn't already in effect. But that assumption may
be incorrect. So use `--push/pop-state` to restore the previous state,
whatever that may be.
Given the position of these switches on the link line, the problem
described with the outgoing code is unlikely to cause an issue in
practice. But push/pop protect against accidents due to future additions
to and reorderings of arguments.
PS5 only. The proprietary PS4 linker doesn't support `--push/pop-state`,
or an equivalent.
SIE tracker: TOOLCHAIN-16704.
Commit: 5a6cc509215b62e94de3b798ea26944a375ce6cb
https://github.com/llvm/llvm-project/commit/5a6cc509215b62e94de3b798ea26944a375ce6cb
Author: Jingyu Qiu <51221277+SoftJing1 at users.noreply.github.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/mremap.cpp
A libc/src/sys/mman/mremap.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/mremap_test.cpp
Log Message:
-----------
[libc] add mremap (#112804)
Commit: 39f2bae2407e08176a453c7c7e6f4888bbf28a4e
https://github.com/llvm/llvm-project/commit/39f2bae2407e08176a453c7c7e6f4888bbf28a4e
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
A clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/RasterizerOrderedStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
Log Message:
-----------
[HLSL] Add RasterizerOrderedStructuredBuffer definition to HLSLExternalSemaSource (#113648)
Adds `RasterizerOrderedStructuredBuffer` definition to
HLSLExternalSemaSource. Adds separate tests for the AST shape and
element types. Adds constructor/handle.fromBinding and subscript test
cases to shared test file for structured buffers. Additional methods
will be added later.
Fixes #112776
Commit: aae5a38e4e5121e340541794404eb62f26e66bf0
https://github.com/llvm/llvm-project/commit/aae5a38e4e5121e340541794404eb62f26e66bf0
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][bazel] Mark socket functions weak (#115088)
Downstream ther'es a user that needs the syscall wrappers to be weak. I
intend to set up a proper mechanism for just listing which functions
should be weak eventually, but for now this is necessary.
Commit: cb90d5b3ef463f0a471f9c6d39978c3764021dea
https://github.com/llvm/llvm-project/commit/cb90d5b3ef463f0a471f9c6d39978c3764021dea
Author: Evan Wilde <ewilde at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M cmake/Modules/CMakePolicy.cmake
Log Message:
-----------
[CMake] Enable CMP0156 if available (#115046)
Some linkers do not require that libraries are repeated on the command
line. The Apple linker emits warnings when duplicate libraries are
specified, resulting in a wall of warnings.
CMP0156 deduplicates libraries on the command line when the linker
doesn't require them.
This patch enables CMP0156 to quiet the warnings when using a version of
CMake that recognizes it (CMake 3.29 and newer).
Commit: 712c90e479f975f2e0c5ed4554dbf2f3a7a6d9d6
https://github.com/llvm/llvm-project/commit/712c90e479f975f2e0c5ed4554dbf2f3a7a6d9d6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_cvtsi64_sd
Commit: 6ccbf1da6c9225fddaf6911e7bb49ee011e845a6
https://github.com/llvm/llvm-project/commit/6ccbf1da6c9225fddaf6911e7bb49ee011e845a6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineSelect - use SelectableOp helper to match the zero operand as well as the target shuffle
For the "select(mask, extract_subvector(shuffle(x)), zero) --> extract_subvector(select(insert_subvector(mask), shuffle(x), zero))" fold, match the zero operand inside the SelectableOp helper.
Prep work for #113400 - we will be able to relax the zero operand requirement for some target shuffles.
Commit: ffc2233395f0b1a3a0c277d196bb0a0ccae84ab7
https://github.com/llvm/llvm-project/commit/ffc2233395f0b1a3a0c277d196bb0a0ccae84ab7
Author: Amara Emerson <amara at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
Log Message:
-----------
[AArch64][SVE2] Add pattern for constructive EXT instruction. (#115047)
rdar://137214338
Commit: 8c752900dda82115ebb8231e6d5ac703e703547e
https://github.com/llvm/llvm-project/commit/8c752900dda82115ebb8231e6d5ac703e703547e
Author: Gang Chen <gangc at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/Assembler/target-type-param-errors.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
A llvm/test/CodeGen/AMDGPU/s-barrier.ll
Log Message:
-----------
[AMDGPU] modify named barrier builtins and intrinsics (#114550)
Use a local pointer type to represent the named barrier in builtin and
intrinsic. This makes the definitions more user friendly
bacause they do not need to worry about the hardware ID assignment. Also
this approach is more like the other popular GPU programming language.
Named barriers should be represented as global variables of addrspace(3)
in LLVM-IR. Compiler assigns the special LDS offsets for those variables
during AMDGPULowerModuleLDS pass. Those addresses are converted to hw
barrier ID during instruction selection. The rest of the
instruction-selection changes are primarily due to the
intrinsic-definition changes.
Commit: cff2199e0f0e54177997ecf9571ba874231cefe4
https://github.com/llvm/llvm-project/commit/cff2199e0f0e54177997ecf9571ba874231cefe4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
Revert "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
This reverts commit 999dfb2067eb75609b735944af876279025ac171.
I received a report that his may have increased fallbacks on AArch64.
Commit: b231647475b7fa78ad9382a5505889f1167e9cea
https://github.com/llvm/llvm-project/commit/b231647475b7fa78ad9382a5505889f1167e9cea
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
A libclc/clc/include/clc/clc_as_type.h
M libclc/clc/include/clc/internal/clc.h
A libclc/clc/include/clc/relational/binary_decl.inc
A libclc/clc/include/clc/relational/clc_all.h
A libclc/clc/include/clc/relational/clc_any.h
A libclc/clc/include/clc/relational/clc_bitselect.h
A libclc/clc/include/clc/relational/clc_bitselect.inc
A libclc/clc/include/clc/relational/clc_isequal.h
A libclc/clc/include/clc/relational/clc_isfinite.h
A libclc/clc/include/clc/relational/clc_isgreater.h
A libclc/clc/include/clc/relational/clc_isgreaterequal.h
A libclc/clc/include/clc/relational/clc_isinf.h
A libclc/clc/include/clc/relational/clc_isless.h
A libclc/clc/include/clc/relational/clc_islessequal.h
A libclc/clc/include/clc/relational/clc_islessgreater.h
A libclc/clc/include/clc/relational/clc_isnan.h
A libclc/clc/include/clc/relational/clc_isnormal.h
A libclc/clc/include/clc/relational/clc_isnotequal.h
A libclc/clc/include/clc/relational/clc_isordered.h
A libclc/clc/include/clc/relational/clc_isunordered.h
A libclc/clc/include/clc/relational/clc_select.h
A libclc/clc/include/clc/relational/clc_select.inc
A libclc/clc/include/clc/relational/clc_signbit.h
A libclc/clc/include/clc/relational/floatn.inc
A libclc/clc/include/clc/relational/relational.h
A libclc/clc/include/clc/relational/unary_decl.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/relational/clc_all.cl
A libclc/clc/lib/generic/relational/clc_any.cl
A libclc/clc/lib/generic/relational/clc_bitselect.cl
A libclc/clc/lib/generic/relational/clc_bitselect.inc
A libclc/clc/lib/generic/relational/clc_isequal.cl
A libclc/clc/lib/generic/relational/clc_isfinite.cl
A libclc/clc/lib/generic/relational/clc_isgreater.cl
A libclc/clc/lib/generic/relational/clc_isgreaterequal.cl
A libclc/clc/lib/generic/relational/clc_isinf.cl
A libclc/clc/lib/generic/relational/clc_isless.cl
A libclc/clc/lib/generic/relational/clc_islessequal.cl
A libclc/clc/lib/generic/relational/clc_islessgreater.cl
A libclc/clc/lib/generic/relational/clc_isnan.cl
A libclc/clc/lib/generic/relational/clc_isnormal.cl
A libclc/clc/lib/generic/relational/clc_isnotequal.cl
A libclc/clc/lib/generic/relational/clc_isordered.cl
A libclc/clc/lib/generic/relational/clc_isunordered.cl
A libclc/clc/lib/generic/relational/clc_select.cl
A libclc/clc/lib/generic/relational/clc_select.inc
A libclc/clc/lib/generic/relational/clc_signbit.cl
M libclc/generic/include/clc/relational/any.h
R libclc/generic/include/clc/relational/binary_decl.inc
R libclc/generic/include/clc/relational/floatn.inc
R libclc/generic/include/clc/relational/unary_decl.inc
M libclc/generic/lib/math/clc_exp10.cl
M libclc/generic/lib/math/clc_fma.cl
M libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/clc_ldexp.cl
M libclc/generic/lib/math/clc_nextafter.cl
M libclc/generic/lib/math/clc_tan.cl
M libclc/generic/lib/relational/all.cl
M libclc/generic/lib/relational/any.cl
A libclc/generic/lib/relational/binary_def.inc
M libclc/generic/lib/relational/bitselect.cl
M libclc/generic/lib/relational/isequal.cl
M libclc/generic/lib/relational/isfinite.cl
M libclc/generic/lib/relational/isgreater.cl
M libclc/generic/lib/relational/isgreaterequal.cl
M libclc/generic/lib/relational/isinf.cl
M libclc/generic/lib/relational/isless.cl
M libclc/generic/lib/relational/islessequal.cl
M libclc/generic/lib/relational/islessgreater.cl
M libclc/generic/lib/relational/isnan.cl
M libclc/generic/lib/relational/isnormal.cl
M libclc/generic/lib/relational/isnotequal.cl
M libclc/generic/lib/relational/isordered.cl
M libclc/generic/lib/relational/isunordered.cl
R libclc/generic/lib/relational/relational.h
M libclc/generic/lib/relational/signbit.cl
A libclc/generic/lib/relational/unary_def.inc
Log Message:
-----------
[libclc] Move relational functions to the CLC library (#115171)
The OpenCL relational functions now call their CLC counterparts, and the
CLC relational functions are defined identically to how the OpenCL
functions were defined.
As usual, clspv and spir-v targets bypass these.
No observable changes to any libclc target (measured with llvm-diff).
Commit: 381156c130553179fe3499403cf530deb73f1a3f
https://github.com/llvm/llvm-project/commit/381156c130553179fe3499403cf530deb73f1a3f
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/test/CodeGen/DirectX/atan2.ll
M llvm/test/CodeGen/DirectX/exp-vec.ll
M llvm/test/CodeGen/DirectX/log-vec.ll
M llvm/test/CodeGen/DirectX/step.ll
Log Message:
-----------
[HLSL] Update tests to use splat for vector constants (#115198)
Fixes test failures after splat IR printer change: 38fffa630ee8.
Commit: 768b0b4eb83e8ca62cc504ba3f0f9a0c46eea7b6
https://github.com/llvm/llvm-project/commit/768b0b4eb83e8ca62cc504ba3f0f9a0c46eea7b6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rv64-double-convert-strict.ll
A llvm/test/CodeGen/RISCV/rv64-double-convert.ll
A llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll
A llvm/test/CodeGen/RISCV/rv64-float-convert.ll
A llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll
A llvm/test/CodeGen/RISCV/rv64-half-convert.ll
Log Message:
-----------
[RISCV] Add test cases for RV64 i128<->half/float/double (#115124)
These emit 'ti' libcalls.
Commit: 3ed4b0b0efca7a9467ce83fc62de9413da38006d
https://github.com/llvm/llvm-project/commit/3ed4b0b0efca7a9467ce83fc62de9413da38006d
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
Log Message:
-----------
[NVPTX] Emit prmt selection value in hex (#115049)
Commit: a1be09a0f3278ab198ba27c5fb171192758d20db
https://github.com/llvm/llvm-project/commit/a1be09a0f3278ab198ba27c5fb171192758d20db
Author: Javed Absar <106147771+javedabsar1 at users.noreply.github.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
Log Message:
-----------
[mlir][linalg] Fix isAllParallelLoops method implementation. (#115179)
Commit: e7bad34475e2fd72e8a9952ded4bfec68d2d0f5a
https://github.com/llvm/llvm-project/commit/e7bad34475e2fd72e8a9952ded4bfec68d2d0f5a
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Use installed libc++(abi) for tests instead of build tree
Using the build tree is somewhat fragile since the layout is not
guaranteed to be stable and means the tests are tightly coupled to the
libc++/libc++abi build tree layout. Instead update the ExternalProject
to install the library and headers and do not add the build tree to
the include/linker flags.
Pull Request: https://github.com/llvm/llvm-project/pull/115077
Commit: a036d18f1a1b74fb8c13ea5bc4b02ce4fe40c997
https://github.com/llvm/llvm-project/commit/a036d18f1a1b74fb8c13ea5bc4b02ce4fe40c997
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
Log Message:
-----------
[compiler-rt] Reduce build output for tests
Use CMAKE_INSTALL_MESSAGE=LAZY to only print the local libc++(abi)
installation messages for changed files instead of all files.
Pull Request: https://github.com/llvm/llvm-project/pull/115085
Commit: 5be02d7a03c6d40d4d71264936d4aab98e4186aa
https://github.com/llvm/llvm-project/commit/5be02d7a03c6d40d4d71264936d4aab98e4186aa
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
Log Message:
-----------
[libc++abi] Stop copying headers to the build directory
This was needed before https://github.com/llvm/llvm-project/pull/115077
since the compiler-rt test build made assumptions about the build
layout of libc++ and libc++abi, but now they link against a local
installation of these libraries so we no longer need this workaround.
Reviewed By: ldionne
Pull Request: https://github.com/llvm/llvm-project/pull/115086
Commit: ccf5d624f9a30911923b2cb3963cacb8076835d8
https://github.com/llvm/llvm-project/commit/ccf5d624f9a30911923b2cb3963cacb8076835d8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
Log Message:
-----------
[AMDGPU] Fix a warning
This patch fixes:
llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp:1031:17: error:
unused variable 'F' [-Werror,-Wunused-variable]
Commit: 375d1925dbd0c051fe2d4a86fe98ed08f4a502c5
https://github.com/llvm/llvm-project/commit/375d1925dbd0c051fe2d4a86fe98ed08f4a502c5
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
Log Message:
-----------
Revert "[NVPTX] Emit prmt selection value in hex" (#115204)
Reverts llvm/llvm-project#115049
Commit: b57cbbcb6a6b8f7134848c52dce4b6f64c02d149
https://github.com/llvm/llvm-project/commit/b57cbbcb6a6b8f7134848c52dce4b6f64c02d149
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv64-double-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/rv64-float-convert.ll
Log Message:
-----------
[RISCV][GISel] Improve fptos/ui and s/uitofp handling and testing.
Replace clampScalar of the integer type with minScalar. We can't
narrow the integer type, we can only make it larger. If the type
is larger than xLen we need to use a 2*xlen libcall. If it's larger
than 2*xlen we can't handle it at all.
Commit: bcb64e13172c9b894be03ccefcf967e99949b32a
https://github.com/llvm/llvm-project/commit/bcb64e13172c9b894be03ccefcf967e99949b32a
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
Log Message:
-----------
[clang][serialization] Reduce `ASTWriter::WriteSourceManagerBlock()` scope
Commit: 0276621f8f5ae489fbe9343cb4cca07579a244a4
https://github.com/llvm/llvm-project/commit/0276621f8f5ae489fbe9343cb4cca07579a244a4
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
Log Message:
-----------
[clang][serialization] Reduce `ASTWriter::WriteControlBlock()` scope
Commit: e9bafa35d27042f8e1daa4ccf4a30bddf31878e8
https://github.com/llvm/llvm-project/commit/e9bafa35d27042f8e1daa4ccf4a30bddf31878e8
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Utils/StaticValueUtils.cpp
M mlir/test/Dialect/Linalg/generalize-tensor-pack.mlir
Log Message:
-----------
[mlir][tensor] Generalize/restrict `GeneralizeOuterUnitDimsPackOpPattern` (#114315)
This PR *restricts* `GeneralizeOuterUnitDimsPackOpPattern` to follow its
intended purpose (as per the documentation), which is to:
> require all outer dimensions of tensor.pack to be 1.
There was one in-tree test that violated this assumption (and happened
to work) – see `@simple_KCRS_to_KRSCsr` in
"generalize-tensor-pack.mlir". That test has been updated to satisfy the
new requirements of the pattern.
By enforcing the pattern to follow its intended design (i.e., making it
stricter), the calculation of shapes and sizes for various Ops that the
pattern generates (PadOp, ExtractSliceOp, EmptyOp, TensorOp, and
InsertSliceOp) becomes much simpler and easier to document. This also
helped *generalize* the pattern to support cases like the one below:
```mlir
func.func @simple_pad_and_pack_dynamic_tile_cst(
%src: tensor<5x1xf32>,
%dest: tensor<1x1x?x2xf32>,
%pad: f32) -> tensor<1x1x?x2xf32> {
%tile_dim_0 = arith.constant 8 : index
%0 = tensor.pack %src
padding_value(%pad : f32)
inner_dims_pos = [0, 1]
inner_tiles = [%tile_dim_0, 2]
into %dest : tensor<5x1xf32> -> tensor<1x1x?x2xf32>
return %0 : tensor<1x1x?x2xf32>
}
```
Note that the inner tile slice is dynamic but compile-time constant.
`getPackOpSourceOrPaddedSource`, which is used to generate PadOp,
detects this and generates a PadOp with static shapes. This is a good
optimization, but it means that all shapes/sizes for Ops generated by
`GeneralizeOuterUnitDimsPackOpPattern` also need to be updated to be
constant/static. By restricting the pattern and simplifying the
size/shape calculation, supporting the case above becomes much easier.
Notable implementation changes:
* PadOp processes the original source (no change in dimensions/rank).
ExtractSliceOp extracts the tile to pack and may reduce the rank. All
following ops work on the tile extracted by ExtractSliceOp (possibly
rank-reduced).
* All shape/size calculations assume that trailing dimensions match
inner_tiles from tensor.pack. All leading dimensions (i.e., outer
dimensions) are assumed to be 1.
* Dynamic sizes for ops like ExtractSliceOp are taken from inner_tiles
rather than computed as, for example, tensor.dim %dest, 2. It’s the
responsibility of the "producers" of tensor.pack to ensure that
dimensions in %dest match the specified tile sizes.
Commit: 4a6d13bf4db63f4cd845d38128c79c17bbf8d99c
https://github.com/llvm/llvm-project/commit/4a6d13bf4db63f4cd845d38128c79c17bbf8d99c
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
Log Message:
-----------
Remove unused variable to fix '[AMDGPU] modify named barrier builtins and intrinsics (#114550)'
https://github.com/llvm/llvm-project/pull/114550 caused a buildbot breakage (https://lab.llvm.org/buildbot/#/builders/66/builds/5853) because of an unused variable. This patch attempts to fix forward:
/home/b/sanitizer-x86_64-linux/build/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp:106:24: error: variable 'TTy' set but not used [-Werror,-Wunused-but-set-variable]
106 | if (TargetExtType *TTy = AMDGPU::isNamedBarrier(GV)) {
| ^
Commit: 304c41217303ce613de8f4042e570ac6ca8757e8
https://github.com/llvm/llvm-project/commit/304c41217303ce613de8f4042e570ac6ca8757e8
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
Log Message:
-----------
[clang][serialization] Reduce `ASTWriter::writeUnhashedControlBlock()` scope
Commit: a878dc8fb37434c4b1897e28e72420f3fd043b3a
https://github.com/llvm/llvm-project/commit/a878dc8fb37434c4b1897e28e72420f3fd043b3a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/cuf03.cuf
Log Message:
-----------
[flang][cuda] Do not emit warning for SHARED variable in device subprogram (#115195)
SHARED attribute is explicitly meant to be used in device subprogram
(https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/index.html#cfpg-var-qual-attr-shared).
Do not emit warning.
Commit: 5942a99f8b7dd361c35eb1c9c32b2475dce2c0b2
https://github.com/llvm/llvm-project/commit/5942a99f8b7dd361c35eb1c9c32b2475dce2c0b2
Author: vporpo <vporpodas at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
Log Message:
-----------
[SandboxVec] Notify scheduler about new instructions (#115102)
This patch registers the "createInstr" callback that notifies the
scheduler about newly created instructions. This guarantees that all
newly created instructions have a corresponding DAG node associated with
them. Without this the pass crashes when the scheduler encounters the
newly created vector instructions.
This patch also changes the lifetime of the sandboxir Ctx variable in
the SandboxVectorizer pass. It needs to be destroyed after the passes
get destroyed. Without this change when components like the Scheduler
get destroyed Ctx will have already been freed, which is not legal.
Commit: ff533b94b7e503019e35fe58b9622b3f76265fcb
https://github.com/llvm/llvm-project/commit/ff533b94b7e503019e35fe58b9622b3f76265fcb
Author: Pranav Kant <prka at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add dep to BuiltinDialectTdFiles (#115217)
Commit: f85be26a67fa822806c9e5c4c26a4bf782898d5a
https://github.com/llvm/llvm-project/commit/f85be26a67fa822806c9e5c4c26a4bf782898d5a
Author: Gang Chen <gangc at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
Log Message:
-----------
[AMDGPU] fix build error unused-var (#115199)
Commit: 21ded66dba0adfd34250df93b5321709883f5e94
https://github.com/llvm/llvm-project/commit/21ded66dba0adfd34250df93b5321709883f5e94
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Add zexti8 ComplexPattern.
Commit: 87f4bc0acad65b1d20160d4160c7778b187125fc
https://github.com/llvm/llvm-project/commit/87f4bc0acad65b1d20160d4160c7778b187125fc
Author: Martin Storsjö <martin at martin.st>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
[compiler-rt] [fuzzer] Skip trying to set the thread name on MinGW (#115167)
Since b4130bee6bfd34d8045f02fc9f951bcb5db9d85c, we check for
_LIBCPP_HAS_THREAD_API_PTHREAD to decide between using
SetThreadDescription or pthread_setname_np for setting the thread name.
c6f3b7bcd0596d30f8dabecdfb9e44f9a07b6e4c changed how libcxx defines
their configuration macros - now they are always defined, but defined to
0 or 1, while they previously were either defined or undefined.
As these libcxx defines used to be defined to an empty string (rather
than expanding to 1) if enabled, we can't easily produce an expression
that works both with older and newer libcxx. Additionally, these defines
are libcxx internal config macros that aren't a detail that isn't
supported and isn't meant to be relied upon.
Simply skip trying to set thread name on MinGW as we can't easily know
which kind of thread native handle we have. Setting the thread name is
only a nice to have, quality of life improvement - things should work
the same even without it.
Additionally, libfuzzer isn't generally usable on MinGW targets yet
(Clang doesn't include it in the getSupportedSanitizers() method for the
MinGW target), so this shouldn't make any difference in practice anyway.
Commit: df0a56cdd9c77e5c10260f99f8afc313b20d6db1
https://github.com/llvm/llvm-project/commit/df0a56cdd9c77e5c10260f99f8afc313b20d6db1
Author: Pranav Kant <prka at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix AMXDialect (#115221)
Commit: a6637ae2cc9a0e7c9a37603b3d277d7ca642bc36
https://github.com/llvm/llvm-project/commit/a6637ae2cc9a0e7c9a37603b3d277d7ca642bc36
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
Log Message:
-----------
[clang][deps] Share `FileManager` between modules (#115065)
The `FileManager` sharing between module-building `CompilerInstance`s
was disabled a while ago due to `FileEntry::getName()` being unreliable.
Now that we use `FileEntryRef::getNameAsRequested()` in places where it
matters, re-enabling `FileManager` is sound and improves performance of
`clang-scan-deps` by ~6.2%.
Commit: 7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4
https://github.com/llvm/llvm-project/commit/7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
Log Message:
-----------
[RISCV] Refine vector division latencies in SiFive P600's scheduling model (#115038)
For both vector integer and floating point divisions.
Co-authored-by: Yeting Kuo <yeting.kuo at sifive.com>
Commit: d08772b1512f630240d8b7feaab749e659d3fce8
https://github.com/llvm/llvm-project/commit/d08772b1512f630240d8b7feaab749e659d3fce8
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
Log Message:
-----------
Revert "[libc++abi] Stop copying headers to the build directory" (#115232)
Reverts llvm/llvm-project#115086
2-stage sanitizer build is not happy:
https://lab.llvm.org/buildbot/#/builders/25/builds/3915
Commit: bd3a3959dc5b72ccbc83334132dece3f38957666
https://github.com/llvm/llvm-project/commit/bd3a3959dc5b72ccbc83334132dece3f38957666
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
Log Message:
-----------
[lldb] Fix deprecated defines in debugserver (XROS -> VISIONOS) (NFC)
Commit: f6617d65e496823c748236cdbe8e42bf4c8d8a55
https://github.com/llvm/llvm-project/commit/f6617d65e496823c748236cdbe8e42bf4c8d8a55
Author: Augusto Noronha <anoronha at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/test/Assembler/debug-info.ll
A llvm/test/DebugInfo/AArch64/num_extra_inhabitants.ll
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[DebugInfo] Add num_extra_inhabitants to debug info (#112590)
An extra inhabitant is a bit pattern that does not represent a valid
value for instances of a given type. The number of extra inhabitants is
the number of those bit configurations.
This is used by Swift to save space when composing types. For example,
because Bool only needs 2 bit patterns to represent all of its values
(true and false), an Optional<Bool> only occupies 1 byte in memory by
using a bit configuration that is unused by Bool. Which bit patterns are
unused are part of the ABI of the language.
Since Swift generics are not monomorphized, by using dynamic libraries
you can have generic types whose size, alignment, etc, are known only
at runtime (which is why this feature is needed).
This patch adds num_extra_inhabitants to LLVM-IR debug info and in DWARF
as an Apple extension.
Commit: cacbe71af7b1075f8ad1f84e002d1fcc83e85713
https://github.com/llvm/llvm-project/commit/cacbe71af7b1075f8ad1f84e002d1fcc83e85713
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/include/llvm/Analysis/LastRunTrackingAnalysis.h
M llvm/include/llvm/Transforms/InstCombine/InstCombine.h
M llvm/lib/Analysis/CMakeLists.txt
A llvm/lib/Analysis/LastRunTrackingAnalysis.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-lto-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/Transforms/Coroutines/coro-retcon-opaque-ptr.ll
M llvm/test/Transforms/Coroutines/coro-retcon.ll
M llvm/unittests/Analysis/CMakeLists.txt
A llvm/unittests/Analysis/LastRunTrackingAnalysisTest.cpp
M llvm/unittests/Target/X86/TernlogTest.cpp
Log Message:
-----------
[Analysis] Avoid running transform passes that have just been run (#112092)
This patch adds a new analysis pass to track a set of passes and their
parameters to see if we can avoid running transform passes that have
just been run. The current implementation only skips redundant
InstCombine runs. I will add support for other passes in follow-up
patches.
RFC link:
https://discourse.llvm.org/t/rfc-pipeline-avoid-running-transform-passes-that-have-just-been-run/82467
Compile time improvement:
http://llvm-compile-time-tracker.com/compare.php?from=76007138f4ffd4e0f510d12b5e8cad529c21f24d&to=64134cf07ea7eb39c60320087c0c5afdc16c3a2b&stat=instructions%3Au
Commit: bbc3af0577a05bf5c06f5c39d51b7d48bd63d65f
https://github.com/llvm/llvm-project/commit/bbc3af0577a05bf5c06f5c39d51b7d48bd63d65f
Author: Ryan Mansfield <ryan_mansfield at apple.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/tools/dsymutil/dsymutil.cpp
Log Message:
-----------
[dsymutil] Add missing newlines in error messages. (#115191)
Errors like "cannot create bundle: Not a directory" or "error:
a.out.dSYM: Is a directory" were being emitted without a newline.
Commit: 84745da74c8aa2749510c26cf0e3a35bececfa30
https://github.com/llvm/llvm-project/commit/84745da74c8aa2749510c26cf0e3a35bececfa30
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/unittests/Analysis/LastRunTrackingAnalysisTest.cpp
Log Message:
-----------
[Analysis] Fix a warning (NFC)
This patch fixes:
third-party/unittest/googletest/include/gtest/gtest.h:1379:11:
error: comparison of integers of different signs: 'const unsigned
int' and 'const int' [-Werror,-Wsign-compare]
Commit: 5348a30a580c280ad71198fee78e270de36628e7
https://github.com/llvm/llvm-project/commit/5348a30a580c280ad71198fee78e270de36628e7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
Log Message:
-----------
[ExecutionEngine] Simplify code with DenseMap::operator[] (NFC) (#115115)
Commit: cbfe87c2537d3bb16cb131078bc1251f68046971
https://github.com/llvm/llvm-project/commit/cbfe87c2537d3bb16cb131078bc1251f68046971
Author: Konstantin Schwarz <konstantin.schwarz at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/neon-perm.ll
Log Message:
-----------
[GlobalISel] Remove references to rhs of shufflevector if rhs is undef (#115076)
Commit: 7c8287586690650ee8bca2282b2a20cc7dc40bde
https://github.com/llvm/llvm-project/commit/7c8287586690650ee8bca2282b2a20cc7dc40bde
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
Log Message:
-----------
[GISel][RISCV][AMDGPU] Add G_SHL, G_LSHR, G_ASHR to binop_left_to_zero. (#115089)
Shifting 0 by any amount is still zero.
Commit: 29a5c054e6d56a912ed5ba3f84e8ca631872db8b
https://github.com/llvm/llvm-project/commit/29a5c054e6d56a912ed5ba3f84e8ca631872db8b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
Log Message:
-----------
ValueTracking: Allow getUnderlyingObject to look at vectors (#114311)
We can identify some easy vector of pointer cases, such as
a getelementptr with a scalar base.
Commit: 30d80009e5012eba5f2e026375038e81932d84f6
https://github.com/llvm/llvm-project/commit/30d80009e5012eba5f2e026375038e81932d84f6
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M flang/include/flang/Common/Fortran.h
M flang/lib/Common/Fortran.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Semantics/check-call.cpp
A flang/test/Semantics/cuf17.cuf
Log Message:
-----------
[flang][cuda] Allow SHARED actual to DEVICE dummy (#115215)
Update the compatibility rules to allow SHARED actual argument passed to
DEVICE dummy argument. Emit a warning in that case.
Commit: af5c471a4d9a9bff30b381d1fe2fe828672bb812
https://github.com/llvm/llvm-project/commit/af5c471a4d9a9bff30b381d1fe2fe828672bb812
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][Vector] Add vector.extract(vector.shuffle) folder (#115105)
This PR adds a folder for extracting an element from a vector shuffle.
It turns something like:
```
%shuffle = vector.shuffle %a, %b [0, 8, 7, 15]
: vector<8xf32>, vector<8xf32>
%extract = vector.extract %shuffle[3] : f32 from vector<4xf32>
```
into:
```
%extract = vector.extract %b[7] : f32 from vector<8xf32>
```
Commit: 7cb66772e23c2208bb920e826661af244790735f
https://github.com/llvm/llvm-project/commit/7cb66772e23c2208bb920e826661af244790735f
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
Log Message:
-----------
[RISCV] Rework fixed-length masked load/store tests. NFC
Pass in the mask and vector directly as arguments, and add tests for
zvfhmin and zvfbfmin.
Commit: 05f87b2d65a7049ff0f846151ada6c0bcbf154a8
https://github.com/llvm/llvm-project/commit/05f87b2d65a7049ff0f846151ada6c0bcbf154a8
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
Log Message:
-----------
[RISCV] Lower fixed-length mload/mstore for zvfhmin/zvfbfmin (#115145)
This is the same idea as #114945.
Commit: de18fa1ace1cd717da9482a09d0a0db8666f48b7
https://github.com/llvm/llvm-project/commit/de18fa1ace1cd717da9482a09d0a0db8666f48b7
Author: Richard Smith <richard at metafoo.co.uk>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/DynamicAllocator.h
M clang/lib/AST/ByteCode/Program.h
Log Message:
-----------
Don't redundantly specify the default template argument to `BumpPtrAllocatorImpl` (#114857)
Commit: 70bc12e77fe25cd933f8a9815646add6f1ea842f
https://github.com/llvm/llvm-project/commit/70bc12e77fe25cd933f8a9815646add6f1ea842f
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
Log Message:
-----------
[RISCV] Remove unnecessary scalar extensions from test. NFC
Now that f16 and bf16 aren't being scalarized we don't need
zfhmin/zfbfmin.
Commit: c6091cdbedd86cdab0a0d0f18569bf28e016ed9d
https://github.com/llvm/llvm-project/commit/c6091cdbedd86cdab0a0d0f18569bf28e016ed9d
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll
Log Message:
-----------
[SLP][REVEC] Make shufflevector can be vectorized with ReorderIndices and ReuseShuffleIndices. (#114965)
Commit: da032b7903da57eb87015369e5c4db521cb4dbac
https://github.com/llvm/llvm-project/commit/da032b7903da57eb87015369e5c4db521cb4dbac
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Use maskedValueIsZero in RISCVInstructionSelector::selectZExtBits. (#115244)
Commit: 3bdd71137eb6a54a3f8a45bdb33bfe15edc05f28
https://github.com/llvm/llvm-project/commit/3bdd71137eb6a54a3f8a45bdb33bfe15edc05f28
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Extract helper function for constraining operands (#115148)
As a side effect, this fixes COPY_TO_REGCLASS not being constrained
if it is not top-level (the reason for changes in tests).
Commit: 481ff22b8b81bb5e2d40101b36eca3e90a7d1a5d
https://github.com/llvm/llvm-project/commit/481ff22b8b81bb5e2d40101b36eca3e90a7d1a5d
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
Log Message:
-----------
[RISCV] Lower fixed-length vp_{gather,scatter} for zvfhmin/zvfbfmin (#115253)
This uses the same lowering as masked gathers and scatters.
Commit: f0e2301b7c3f2576a4fbc53441e9378b966e21ef
https://github.com/llvm/llvm-project/commit/f0e2301b7c3f2576a4fbc53441e9378b966e21ef
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
Log Message:
-----------
[RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal interleaved access (#115257)
This is another piece split off from the work to add zvfhmin/zvfbfmin to
isLegalElementTypeForRVV.
This is needed to get InterleavedAccessPass to lower [de]interleaves to
segment load/stores.
Commit: ae6dbed5943d76c61fe95107c15a46f915180772
https://github.com/llvm/llvm-project/commit/ae6dbed5943d76c61fe95107c15a46f915180772
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/idot4s.ll
Log Message:
-----------
[AMDGPU] Use correct DWord for v_dot4 S0 operand (#115224)
Fixes a copy-paste typo.
The typo resulted in producing bad v_perm based operands for the v_dot4
combine. When adding a corresponding byte pair to the v_dot byte pair
chains, we must take note of the byte position in the corresponding
source nodes. These byte positions are used to ensure we extract the
correct DWord from the ultimate source, and formulate a correct
perm_mask from the extracted DWord.
With the typo, we the S0 byte would used the DWord offset for the
corresponding S1 byte. If this offset was not the same as the true DWord
offset for the S0 byte, we would extract and use the wrong byte for S0
in the v_dot.
Fixes https://github.com/llvm/llvm-project/issues/112941
Commit: f7ef7b2ff700360c90d568622e3efd563d9eff05
https://github.com/llvm/llvm-project/commit/f7ef7b2ff700360c90d568622e3efd563d9eff05
Author: vporpo <vporpodas at google.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][Scheduler] Implement rescheduling (#115220)
This patch adds support for re-scheduling already scheduled
instructions. For now this will clear and rebuild the DAG, and will
reschedule the code using the new DAG.
Commit: 63c6fe4a0b18d5eaa50c002185cd270f20cf131b
https://github.com/llvm/llvm-project/commit/63c6fe4a0b18d5eaa50c002185cd270f20cf131b
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/EhFrame.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Thunks.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Replace fatal(...) with Fatal or Err
Commit: 09c2c5e1e9f3b3bb17f777f153407430f3cef15e
https://github.com/llvm/llvm-project/commit/09c2c5e1e9f3b3bb17f777f153407430f3cef15e
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/AVR.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/MSP430.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SPARCV9.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/CallGraphSort.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Replace error(...) with ErrAlways or Err
Most are migrated to ErrAlways mechanically.
In the future we should change most to Err.
Commit: f8bae3af74e7c60d996f0d331cad04f2eace7f8f
https://github.com/llvm/llvm-project/commit/f8bae3af74e7c60d996f0d331cad04f2eace7f8f
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Replace warn(...) with Warn
Commit: 9b058bb42d49afb61b07a7eeeea1ad3d1407f1c9
https://github.com/llvm/llvm-project/commit/9b058bb42d49afb61b07a7eeeea1ad3d1407f1c9
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Replace errorOrWarn(...) with Err
Commit: 343a810725f27bfe92fbd04a42d42aa9caaee7a6
https://github.com/llvm/llvm-project/commit/343a810725f27bfe92fbd04a42d42aa9caaee7a6
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
Log Message:
-----------
[RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal strided access (#115264)
This is also split off from the zvfhmin/zvfbfmin
isLegalElementTypeForRVV work.
Enabling this will cause SLP and RISCVGatherScatterLowering to emit
@llvm.experimental.vp.strided.{load,store} intrinsics, and codegen
support for this was added in #109387 and #114750.
Commit: 9f796159f28775b3f93d77e173c1fd3413c2e60e
https://github.com/llvm/llvm-project/commit/9f796159f28775b3f93d77e173c1fd3413c2e60e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLFunctionalExtras.h
Log Message:
-----------
Add clang::lifetimebound annotation to llvm::function_ref (#115019)
This helps catch dangling llvm::function_ref references, see #114950,
#114949, #114808, #114789
Commit: adb0d8ddceb143749c519d14b8b31b481071da77
https://github.com/llvm/llvm-project/commit/adb0d8ddceb143749c519d14b8b31b481071da77
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
Log Message:
-----------
[Clang] Distinguish expanding-pack-in-place cases for SubstTemplateTypeParmTypes (#114220)
In 50e5411e4, we preserved the pack substitution index within
SubstTemplateTypeParmType nodes and performed in-place expansions of
packs such that type constraints on a lambda that serve as a pattern of
a fold expression could be evaluated if the type constraints contain any
packs that are expanded by the fold expression.
However, we made an incorrect assumption of the condition under which
in-place expansion should occur. For example, a SizeOfPackExpr case
relies on SubstTemplateTypeParmType nodes being transformed to
SubstTemplateTypeParmPackTypes rather than expanding them immediately in
place.
This fixes that by adding a flag to SubstTemplateTypeParmType to
discriminate such in-place expansion situations.
Fixes https://github.com/llvm/llvm-project/issues/113518
Commit: 3850801ca57575640a6ad3a5a421a416dc5c6f12
https://github.com/llvm/llvm-project/commit/3850801ca57575640a6ad3a5a421a416dc5c6f12
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Log Message:
-----------
[RISCV] Add vcpop.m/vfirst.m to RISCVMaskedPseudosTable
We seem to forget these two instructions.
Reviewers: preames, frasercrmck, lukel97, topperc
Reviewed By: lukel97
Pull Request: https://github.com/llvm/llvm-project/pull/115162
Commit: 0b9f1cc024ca6c7e8d60524be07c0ddfcd08b23c
https://github.com/llvm/llvm-project/commit/0b9f1cc024ca6c7e8d60524be07c0ddfcd08b23c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/IndVarSimplify/invalidate-modified-lcssa-phi.ll
M llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
A llvm/test/Transforms/LoopUnroll/pr114879.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
M polly/test/CodeGen/OpenMP/floord-as-argument-to-subfunction.ll
M polly/test/CodeGen/inner_scev_sdiv_2.ll
M polly/test/CodeGen/inner_scev_sdiv_3.ll
M polly/test/CodeGen/non-affine-phi-node-expansion.ll
M polly/test/CodeGen/phi-defined-before-scop.ll
M polly/test/CodeGen/scop_expander_insert_point.ll
M polly/test/CodeGen/stack-overflow-in-load-hoisting.ll
M polly/test/ScopInfo/complex_domain_binary_condition.ll
M polly/test/ScopInfo/scev-div-with-evaluatable-divisor.ll
Log Message:
-----------
[SCEV] Disallow simplifying phi(undef, X) to X (#115109)
See the following case:
```
@GlobIntONE = global i32 0, align 4
define ptr @src() {
entry:
br label %for.body.peel.begin
for.body.peel.begin: ; preds = %entry
br label %for.body.peel
for.body.peel: ; preds = %for.body.peel.begin
br i1 true, label %cleanup.peel, label %cleanup.loopexit.peel
cleanup.loopexit.peel: ; preds = %for.body.peel
br label %cleanup.peel
cleanup.peel: ; preds = %cleanup.loopexit.peel, %for.body.peel
%retval.2.peel = phi ptr [ undef, %for.body.peel ], [ @GlobIntONE, %cleanup.loopexit.peel ]
br i1 true, label %for.body.peel.next, label %cleanup7
for.body.peel.next: ; preds = %cleanup.peel
br label %for.body.peel.next1
for.body.peel.next1: ; preds = %for.body.peel.next
br label %entry.peel.newph
entry.peel.newph: ; preds = %for.body.peel.next1
br label %for.body
for.body: ; preds = %cleanup, %entry.peel.newph
%retval.0 = phi ptr [ %retval.2.peel, %entry.peel.newph ], [ %retval.2, %cleanup ]
br i1 false, label %cleanup, label %cleanup.loopexit
cleanup.loopexit: ; preds = %for.body
br label %cleanup
cleanup: ; preds = %cleanup.loopexit, %for.body
%retval.2 = phi ptr [ %retval.0, %for.body ], [ @GlobIntONE, %cleanup.loopexit ]
br i1 false, label %for.body, label %cleanup7.loopexit
cleanup7.loopexit: ; preds = %cleanup
%retval.2.lcssa.ph = phi ptr [ %retval.2, %cleanup ]
br label %cleanup7
cleanup7: ; preds = %cleanup7.loopexit, %cleanup.peel
%retval.2.lcssa = phi ptr [ %retval.2.peel, %cleanup.peel ], [ %retval.2.lcssa.ph, %cleanup7.loopexit ]
ret ptr %retval.2.lcssa
}
define ptr @tgt() {
entry:
br label %for.body.peel.begin
for.body.peel.begin: ; preds = %entry
br label %for.body.peel
for.body.peel: ; preds = %for.body.peel.begin
br i1 true, label %cleanup.peel, label %cleanup.loopexit.peel
cleanup.loopexit.peel: ; preds = %for.body.peel
br label %cleanup.peel
cleanup.peel: ; preds = %cleanup.loopexit.peel, %for.body.peel
%retval.2.peel = phi ptr [ undef, %for.body.peel ], [ @GlobIntONE, %cleanup.loopexit.peel ]
br i1 true, label %for.body.peel.next, label %cleanup7
for.body.peel.next: ; preds = %cleanup.peel
br label %for.body.peel.next1
for.body.peel.next1: ; preds = %for.body.peel.next
br label %entry.peel.newph
entry.peel.newph: ; preds = %for.body.peel.next1
br label %for.body
for.body: ; preds = %cleanup, %entry.peel.newph
br i1 false, label %cleanup, label %cleanup.loopexit
cleanup.loopexit: ; preds = %for.body
br label %cleanup
cleanup: ; preds = %cleanup.loopexit, %for.body
br i1 false, label %for.body, label %cleanup7.loopexit
cleanup7.loopexit: ; preds = %cleanup
%retval.2.lcssa.ph = phi ptr [ %retval.2.peel, %cleanup ]
br label %cleanup7
cleanup7: ; preds = %cleanup7.loopexit, %cleanup.peel
%retval.2.lcssa = phi ptr [ %retval.2.peel, %cleanup.peel ], [ %retval.2.lcssa.ph, %cleanup7.loopexit ]
ret ptr %retval.2.lcssa
}
```
1. `simplifyInstruction(%retval.2.peel)` returns `@GlobIntONE`. Thus,
`ScalarEvolution::createNodeForPHI` returns SCEV expr `@GlobIntONE` for
`%retval.2.peel`.
2. `SimplifyIndvar::replaceIVUserWithLoopInvariant` tries to replace the
use of `%retval.2.peel` in `%retval.2.lcssa.ph` with `@GlobIntONE`.
3. `simplifyLoopAfterUnroll -> simplifyLoopIVs -> SCEVExpander::expand`
reuses `%retval.2.peel = phi ptr [ undef, %for.body.peel ], [
@GlobIntONE, %cleanup.loopexit.peel ]` to generate code for
`@GlobIntONE`. It is incorrect.
This patch disallows simplifying `phi(undef, X)` to `X` by setting
`CanUseUndef` to false.
Closes https://github.com/llvm/llvm-project/issues/114879.
Commit: ae5bfa0cef0873d30e7dd5cb20ff4437b244203e
https://github.com/llvm/llvm-project/commit/ae5bfa0cef0873d30e7dd5cb20ff4437b244203e
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
Log Message:
-----------
[clang] Output an error when [[lifetimebound]] attribute is applied on a function implicit object parameter while the function returns void (#114203)
Fixes: https://github.com/llvm/llvm-project/issues/107556
Commit: 1469d82e1cb3edc939d6b93089046edfef0cf36c
https://github.com/llvm/llvm-project/commit/1469d82e1cb3edc939d6b93089046edfef0cf36c
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/phi-values-usage.ll
M llvm/test/Analysis/BasicAA/underlying-value.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
M llvm/test/Analysis/BranchProbabilityInfo/loop.ll
M llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
M llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll
M llvm/test/Analysis/CycleInfo/basic.ll
M llvm/test/Analysis/CycleInfo/unreachable-predecessor.ll
M llvm/test/Analysis/Delinearization/type_mismatch.ll
M llvm/test/Analysis/Delinearization/undef.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
M llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll
M llvm/test/Analysis/Dominators/basic.ll
M llvm/test/Analysis/Dominators/print-dot-dom.ll
M llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll
M llvm/test/Analysis/MemorySSA/cyclicphi.ll
M llvm/test/Analysis/MemorySSA/debugvalue.ll
M llvm/test/Analysis/MemorySSA/debugvalue2.ll
M llvm/test/Analysis/MemorySSA/forward-unreachable.ll
M llvm/test/Analysis/MemorySSA/function-clobber.ll
M llvm/test/Analysis/MemorySSA/invariant-groups.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-simplified-clone.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll
M llvm/test/Analysis/MemorySSA/phi-translation.ll
M llvm/test/Analysis/MemorySSA/pr28880.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr41640.ll
M llvm/test/Analysis/MemorySSA/pr41853.ll
M llvm/test/Analysis/MemorySSA/pr42940.ll
M llvm/test/Analysis/MemorySSA/pr43317.ll
M llvm/test/Analysis/MemorySSA/pr43320.ll
M llvm/test/Analysis/MemorySSA/pr43427.ll
M llvm/test/Analysis/MemorySSA/pr43438.ll
M llvm/test/Analysis/MemorySSA/pr43493.ll
M llvm/test/Analysis/MemorySSA/pr43541.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr45976.ll
M llvm/test/Analysis/MemorySSA/reduce_clobber_limit.ll
M llvm/test/Analysis/MemorySSA/renamephis.ll
M llvm/test/Analysis/MemorySSA/unreachable.ll
M llvm/test/Analysis/MemorySSA/update_unroll.ll
M llvm/test/Analysis/PhiValues/basic.ll
M llvm/test/Analysis/PhiValues/long_phi_chain.ll
M llvm/test/Analysis/PostDominators/pr6047_a.ll
M llvm/test/Analysis/PostDominators/pr6047_b.ll
M llvm/test/Analysis/PostDominators/pr6047_c.ll
M llvm/test/Analysis/PostDominators/pr6047_d.ll
M llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
M llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
M llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll
M llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll
M llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
M llvm/test/Analysis/ScalarEvolution/pr22674.ll
M llvm/test/Analysis/ScalarEvolution/pr22856.ll
M llvm/test/Analysis/ScalarEvolution/pr25369.ll
M llvm/test/Analysis/ScalarEvolution/scev-aa.ll
M llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll
M llvm/test/Analysis/ScalarEvolution/scev-invalid.ll
M llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
M llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
M llvm/test/Assembler/atomicrmw.ll
M llvm/test/Assembler/convergence-control.ll
M llvm/test/Bitcode/convergence-control.ll
M llvm/test/DebugInfo/ARM/illegal-fragment.ll
M llvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
M llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
M llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
M llvm/test/DebugInfo/MIR/X86/machine-cse.mir
M llvm/test/DebugInfo/X86/dbg-merge-loc-entry.ll
M llvm/test/DebugInfo/X86/dbg-value-terminator.ll
M llvm/test/DebugInfo/X86/deleted-bit-piece.ll
M llvm/test/DebugInfo/X86/earlydup-crash.ll
M llvm/test/DebugInfo/X86/live-debug-values-constprop.mir
M llvm/test/DebugInfo/X86/mem2reg_fp80.ll
M llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
M llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg2-dead-block-order.ll
M llvm/test/Other/loop-pass-ordering.ll
M llvm/test/Other/loopnest-pass-ordering.ll
M llvm/test/Other/opt-bisect-new-pass-manager.ll
M llvm/test/SafepointIRVerifier/from-same-relocation-in-phi-nodes.ll
M llvm/test/SafepointIRVerifier/unrecorded-live-at-sp.ll
M llvm/test/SafepointIRVerifier/uses-in-phi-nodes.ll
M llvm/test/Verifier/tbaa-cyclic.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
Log Message:
-----------
Remove `br i1 undef` from some regression tests [NFC] (#115130)
As defined in LangRef, branching on `undef` is undefined behavior.
This PR aims to remove undefined behavior from tests. As UB tests break
Alive2 and may be the root cause of breaking future optimizations.
Here's an Alive2 proof for one of the examples:
https://alive2.llvm.org/ce/z/TncxhP
Commit: 9b909b8886e35cf5816f660092a2337f779e3e3d
https://github.com/llvm/llvm-project/commit/9b909b8886e35cf5816f660092a2337f779e3e3d
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
Log Message:
-----------
[AMDGPU][NFC] Precommit tests representing agpr spills. (#115270)
Presently we are only marking implicit-def for the
spilled AGPR tuple in the first spill instructions
and not implicit.
Commit: 5f342816efe1854333f2be41a03fdd25fa0db433
https://github.com/llvm/llvm-project/commit/5f342816efe1854333f2be41a03fdd25fa0db433
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp
A llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
Log Message:
-----------
[llvm] Use computeConstantRange to improve llvm.objectsize computation (#114673)
Using LazyValueInfo, it is possible to compute valuable information for
allocation functions, GEP and alloca, even in the presence of dynamic
information.
llvm.objectsize plays an important role in _FORTIFY_SOURCE definitions,
so improving its diagnostic in turns improves the security of compiled
application.
As a side note, as a result of recent optimization improvements, clang
no longer passes
https://github.com/serge-sans-paille/builtin_object_size-test-suite This
commit restores the situation and greatly improves the scope of code
handled by the static version of __builtin_object_size.
Commit: d2aff182d379c9b84cebe0fdf58907f4de768f1e
https://github.com/llvm/llvm-project/commit/d2aff182d379c9b84cebe0fdf58907f4de768f1e
Author: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/Transforms/Scalar.h
R llvm/include/llvm/Transforms/Scalar/TLSVariableHoist.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/Scalar.cpp
R llvm/lib/Transforms/Scalar/TLSVariableHoist.cpp
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
R llvm/test/CodeGen/X86/tls-loads-control.ll
R llvm/test/CodeGen/X86/tls-loads-control2.ll
R llvm/test/CodeGen/X86/tls-loads-control3.ll
M llvm/tools/llc/llc.cpp
Log Message:
-----------
Revert "TLS loads opimization (hoist)" (#114740)
This reverts commit c31014322c0b5ae596da129cbb844fb2198b4ef4.
Based on the discussions in #112772, this pass is not needed after the
introduction of `llvm.threadlocal.address` intrinsic.
Fixes https://github.com/llvm/llvm-project/issues/112771.
Commit: 2d7f34f2a5df9396a33a0ea044cfe3ddf33e1f5c
https://github.com/llvm/llvm-project/commit/2d7f34f2a5df9396a33a0ea044cfe3ddf33e1f5c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Don't special case depth for phi of select (#114996)
As discussed on
https://github.com/llvm/llvm-project/pull/114689#pullrequestreview-2411822612
and following, there is no principled reason why the phi of select case
should have a different recursion limit than the general case. There may
still be fan-out, and there may still be indirect recursion. Revert that
part of #113707.
Commit: 1b01064faad2cd93c516341cfaf047b7a0f8da42
https://github.com/llvm/llvm-project/commit/1b01064faad2cd93c516341cfaf047b7a0f8da42
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor copy intrinsics (#96083)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.S2G.1D -> 5D variants, supporting both Tile and
Im2Col modes. These intrinsics optionally support cache_hints as
indicated by the boolean flag argument.
* cp.async.bulk.tensor.G2S.1D -> 5D variants, with support for both Tile
and Im2Col modes. The Im2Col variants have an extra set of offsets as
parameters. These intrinsics optionally support multicast and cache_hints,
as indicated by the boolean arguments at the end of the intrinsics.
* The backend looks through these flag arguments and lowers to the
appropriate PTX instruction.
* Lit tests are added for all combinations of these intrinsics in
cp-async-bulk-tensor-g2s/s2g.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f9fecab1fd4e2aec74b864b1ee81679b14f13f5c
https://github.com/llvm/llvm-project/commit/f9fecab1fd4e2aec74b864b1ee81679b14f13f5c
Author: simpal01 <simi.pallipurath at arm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
Add -mno-unaligned-access and -mbig-endian to ARM and AArch64 multilib flags (#114782)
This adds -mno-unaligned-access and -mbig-endian command line
options to the set of flags used by the multilib selection for ARM and
AArch64 targets.
Commit: 490e58a98e0518542c87aa16e326fcb446d7b1cc
https://github.com/llvm/llvm-project/commit/490e58a98e0518542c87aa16e326fcb446d7b1cc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
Log Message:
-----------
Fix MSVC "not all control paths return a value" warning. NFC
Commit: 6720ce75f61a306a3ed26b2205f09a7099e978e7
https://github.com/llvm/llvm-project/commit/6720ce75f61a306a3ed26b2205f09a7099e978e7
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/tools/llvm-exegesis/README.md
Log Message:
-----------
[Docs][llvm-exegesis] Clarify AArch64 support (#114989)
Claiming AArch64 support for llvm-exegesis is a bit of a stretch in my
opinion as only a couple of opcodes with GPR64 operands will work for
snippet benchmarking, so I propose to clarify that AArch64 support is
very experimental. Also added some clarifications about its libpfm4
dependency.
Commit: 0c0d7a6ec7ece55d4516d7b902d488b42c850e16
https://github.com/llvm/llvm-project/commit/0c0d7a6ec7ece55d4516d7b902d488b42c850e16
Author: JoelWee <32009741+JoelWee at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[MLIR] Fix bazel after 2f743ac
Commit: 1361c19c04d0b3d9156fe0c5393d158cf69c14e7
https://github.com/llvm/llvm-project/commit/1361c19c04d0b3d9156fe0c5393d158cf69c14e7
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lang/cpp/const_static_integral_member/main.cpp
Log Message:
-----------
[lldb] Index static const members of classes, structs and unions as global variables in DWARF 4 and earlier (#111859)
In DWARF 4 and earlier `static const` members of structs, classes and
unions have an entry tag `DW_TAG_member`, and are also tagged as
`DW_AT_declaration`, but otherwise follow the same rules as
`DW_TAG_variable`.
Commit: dd98ae358b187be32a2e255eba5f91568524b86a
https://github.com/llvm/llvm-project/commit/dd98ae358b187be32a2e255eba5f91568524b86a
Author: JaydeepChauhan14 <167076022+JaydeepChauhan14 at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/TableGen/x86-instr-mapping.inc
A llvm/test/TableGen/x86-instr-mapping.td
Log Message:
-----------
Test added for x86-instr-mapping (#115170)
Commit: 9f02950a1589ebfc542f4f5a2475c2cc03e4e2e9
https://github.com/llvm/llvm-project/commit/9f02950a1589ebfc542f4f5a2475c2cc03e4e2e9
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
A llvm/test/CodeGen/Thumb2/mve-vadc-vsbc-spill.ll
Log Message:
-----------
[ARM] Allow spilling FPSCR for MVE adc/sbc intrinsics (#115174)
The MVE VADC and VSBC instructions read and write a carry bit in FPSCR,
which is exposed through the intrinsics. This makes it possible to write
code which has the FPSCR live across a function call, or which uses the
same value twice, so it needs to be possible to spill and reload it.
There is a missed optimisation in one of the test cases, where we reload
the FPSCR from the stack despite it still being live, I've not found a
simple way to prevent the register allocator from doing this.
Commit: 4fa1e8f970235918da8e7c467cdcd227c2f87536
https://github.com/llvm/llvm-project/commit/4fa1e8f970235918da8e7c467cdcd227c2f87536
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/tools/gold/X86/opt-level.ll
Log Message:
-----------
[gold] Fix test after pipeline change
After fbd89bcc6647ed611e579d8f9c38c97b8e6f7936 we're not running
FunctionAttrs at O1, so adjust the test expectation accordingly.
Commit: f43ef53dd20b83ea0db6fdba69025c9a76a1de08
https://github.com/llvm/llvm-project/commit/f43ef53dd20b83ea0db6fdba69025c9a76a1de08
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll
Log Message:
-----------
[Mem2Reg] Regenerate test checks (NFC)
Switch to FileCheck and use UTC.
Commit: d87dbcbf137ab1c6b6c2db1fd3fe7d91a3142fa1
https://github.com/llvm/llvm-project/commit/d87dbcbf137ab1c6b6c2db1fd3fe7d91a3142fa1
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
Log Message:
-----------
[LoongArch] Reuse GPRRegisterClass to shorten some code in LoongArchRegisterInfo.td. NFC
Commit: abe0cd4621ccee26196ceb7506e908d4134f630e
https://github.com/llvm/llvm-project/commit/abe0cd4621ccee26196ceb7506e908d4134f630e
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll
Log Message:
-----------
ValueTracking: pre-commit udiv/urem recurrence tests (#109198)
Commit: fef6613e9fc05bca8e315c65e8f8da796860a3cf
https://github.com/llvm/llvm-project/commit/fef6613e9fc05bca8e315c65e8f8da796860a3cf
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll
Log Message:
-----------
ValueTracking: simplify udiv/urem recurrences (#108973)
A urem recurrence has the property that the result can never exceed the
start value. A udiv recurrence has the property that the result can
never exceed either the start value or the numerator, whichever is
greater. Implement a simplification based on these properties.
Commit: dafbc97594c26da67e34ba0301a6126419ae4604
https://github.com/llvm/llvm-project/commit/dafbc97594c26da67e34ba0301a6126419ae4604
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/test/COFF/arm64ec-altnames.s
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-delayimport.test
M lld/test/COFF/arm64ec-export-thunks.test
M lld/test/COFF/arm64ec-import.test
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-loadcfg.s
M lld/test/COFF/arm64ec-range-thunks.s
M lld/test/COFF/locally-imported-arm64ec.test
Log Message:
-----------
[LLD][COFF] Append a terminator entry to redirection metadata (#115202)
For MSVC compatibility.
Commit: 9470945b6695cf526df9249c3787d225f95eaf03
https://github.com/llvm/llvm-project/commit/9470945b6695cf526df9249c3787d225f95eaf03
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/CalcSpillWeights.cpp
Log Message:
-----------
[CalcSpillWeights] Simplify copy hint register collection. NFC. (#114236)
CopyHints set has been collecting duplicates of a register with
increasing weight and then deduplicated with HintedRegs set. Let's stop
collecting duplicates at the first place.
Commit: 3d0b283dcd6d9fbe41618fd476c14bc00b62b3e5
https://github.com/llvm/llvm-project/commit/3d0b283dcd6d9fbe41618fd476c14bc00b62b3e5
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseStmt.cpp
A clang/test/C/C2y/n3370.c
M clang/test/Sema/gnu-flags.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage for WG14 N3370 (#115054)
This paper added case ranges in switch statements, which is a GNU
extension Clang has supported since at least Clang 3.0.
It updates the diagnostics to no longer call this a GNU extension except
in C++ mode.
Commit: 16cd5cdf4d6387e34d2bb723bc26c331c8d89d75
https://github.com/llvm/llvm-project/commit/16cd5cdf4d6387e34d2bb723bc26c331c8d89d75
Author: Jacob Bramley <jacob.bramley at arm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/Inputs/spurious-marker-symbol.yaml
A bolt/test/AArch64/spurious-marker-symbol.test
M llvm/include/llvm/Object/ObjectFile.h
Log Message:
-----------
[BOLT] Ignore AArch64 markers outside their sections. (#74106)
AArch64 uses $d and $x symbols to delimit data embedded in code.
However, sometimes we see $d symbols, typically in .eh_frame, with
addresses that belong to different sections. These occasionally fall
inside .text functions and cause BOLT to stop disassembling, which in
turn causes DWARF CFA processing to fail.
As a workaround, we just ignore symbols with addresses outside the
section they belong to. This behaviour is consistent with objdump and
similar tools.
Commit: e40a31b7baef8c39b9e03ebf94ddfefdba52601e
https://github.com/llvm/llvm-project/commit/e40a31b7baef8c39b9e03ebf94ddfefdba52601e
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/TraversalChecker.cpp
R clang/test/Analysis/traversal-algorithm.mm
Log Message:
-----------
[analyzer][NFC] Remove check::BranchCondition from debug.DumpTraversal (#113906)
This commit removes the `check::BranchCondition` callback of the debug
checker `debug.DumpTraversal` (in `TraversalChecker.cpp`) and the single
broken testcase that was referring to it.
The testcase `traversal-algorithm.mm` was added in 2012 to verify that
we're using DFS traversal -- however it failed to detect that we're no
longer using DFS traversal and in fact it continues to pass even if I
remove large random portions of its code.
This change was motivated by the plan discussed at
https://discourse.llvm.org/t/fixing-or-removing-check-branchcondition/82738
I also added some TODO notes to mark the rest of `TraversalChecker.cpp`
for removal in follow-up commits.
Commit: b358f218a114c1495cfb356b1b95c866c32f72c4
https://github.com/llvm/llvm-project/commit/b358f218a114c1495cfb356b1b95c866c32f72c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
Log Message:
-----------
[X86] visitSelect - widen select(cond,extract_subvector(shuffle(vec0)),vec1) if it will create a mask instruction (#115223)
This patch extends the existing fold "select(mask, extract_subvector(shuffle(x)), zero) --> extract_subvector(select(insert_subvector(mask), shuffle(x), zero))", to also handle the non-zero case.
I've put in a restriction for VPERMV3 3 vector operands shuffles to only work with the zero select as in most circumstances we are not selecting with either of the source vectors (the only case the mask instructions match).
We should be able to generalize this in the future to work with other maskable instructions, but this is a good initial improvement.
Fixes #113400
Commit: 8269c400b430e4beb9fdb51b94dbc79b84c37f70
https://github.com/llvm/llvm-project/commit/8269c400b430e4beb9fdb51b94dbc79b84c37f70
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir][OpenMP][NFC] delayed privatisation cleanup (#115298)
Upstreaming some code cleanups ahead of supporting delayed task
execution.
- Make allocatePrivateVars not need to be a template (it will need to
operate separately on firstprivate and private variables for delayed
task execution so it can't index into lists of all variables in the
operation).
- Use llvm::SmallVectorImpl for function arguments
- collectPrivatizationDecls already reserves size for privateDecls so we
don't need to do that in callers
- Use llvm::zip_equal instead of C-style array indexing
Commit: 9123dc6abfa76c90c04caf1a58574eff417a2aed
https://github.com/llvm/llvm-project/commit/9123dc6abfa76c90c04caf1a58574eff417a2aed
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Log Message:
-----------
[AArch64] AArch64ISelDAGToDAG.cpp - disable inlining on MSVC release builds (#115292)
Similar to #110986 - disabling inlining on MSVC release builds avoids an excessive build time issue affecting all recent versions of CL.EXE
Fixes #114425
Commit: f5e4ffaa49254706ad6fa209de8aec28e20f0041
https://github.com/llvm/llvm-project/commit/f5e4ffaa49254706ad6fa209de8aec28e20f0041
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp
R llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
Log Message:
-----------
Revert "[llvm] Use computeConstantRange to improve llvm.objectsize computation (#114673)"
This reverts commit 5f342816efe1854333f2be41a03fdd25fa0db433.
This seems to break various builders, such as
https://lab.llvm.org/buildbot/#/builders/41/builds/3259
https://lab.llvm.org/buildbot/#/builders/76/builds/4298
Commit: 4fb953ac348d888541efe515439e0d844cdd7fbf
https://github.com/llvm/llvm-project/commit/4fb953ac348d888541efe515439e0d844cdd7fbf
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Driver/amdgpu-macros.cl
Log Message:
-----------
[AMDGPU] Make `__GCC_DESTRUCTIVE_SIZE` 128 on AMDGPU (#115241)
Summary:
The cache line size on AMDGPU varies between 64 and 128 (The lowest L2
cache also goes to 256 on some architectures.) This macro is intended to
present a size that will not cause destructive interference, so we
choose the larger of those values.
Commit: dd116369f646d023a2e7e5c145a1bed5dcf9a45c
https://github.com/llvm/llvm-project/commit/dd116369f646d023a2e7e5c145a1bed5dcf9a45c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/CodeGen/AArch64/convertphitype.ll
M llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
M llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
M llvm/test/CodeGen/Hexagon/trunc-mpy.ll
M llvm/test/CodeGen/PowerPC/sms-phi-5.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstSimplify/phi.ll
M llvm/test/Transforms/LoopDeletion/pr53969.ll
M llvm/test/Transforms/LoopVectorize/pr31190.ll
M llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll
M llvm/test/Transforms/Mem2Reg/single-store.ll
Log Message:
-----------
[InstSimplify] Fix incorrect poison propagation when folding phi (#96631)
We can only replace phi(X, undef) with X, if X is known not to be
poison. Otherwise, the result may be more poisonous on the undef branch.
Fixes https://github.com/llvm/llvm-project/issues/68683.
Commit: a9cd941f392dbf99ddfcde9721bd5c485823bdf0
https://github.com/llvm/llvm-project/commit/a9cd941f392dbf99ddfcde9721bd5c485823bdf0
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxx/include/print
Log Message:
-----------
[libcxx] Fix inverted `has_terminal` condition
Summary:
This used to indicate "has no terminal" and now it indicates "has
terminal" but the check was not changed.
Commit: 4f24d0355a70374bf072585281583553113bf5da
https://github.com/llvm/llvm-project/commit/4f24d0355a70374bf072585281583553113bf5da
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Use explicit ExtractElementInst getVectorOperand/getIndexOperand accessors. NFC.
Commit: e236a52a88956968f318fb908c584e5cb80b5b03
https://github.com/llvm/llvm-project/commit/e236a52a88956968f318fb908c584e5cb80b5b03
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M libcxx/CMakeLists.txt
M libcxx/docs/TestingLibcxx.rst
M libcxx/docs/VendorDocumentation.rst
M libcxx/test/CMakeLists.txt
M libcxx/test/benchmarks/CMakeLists.txt
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/atomic_wait_vs_mutex_lock.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lit.cfg.py.in
R libcxx/test/benchmarks/lit.site.cfg.py.in
M libcxx/test/benchmarks/util_smartptr.bench.cpp
M libcxx/test/configs/cmake-bridge.cfg.in
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/libcxx/test/config.py
M libcxx/utils/libcxx/test/format.py
R libcxx/utils/libcxx/test/googlebenchmark.py
M libcxx/utils/libcxx/test/params.py
M libcxxabi/test/configs/cmake-bridge.cfg.in
M libunwind/test/configs/cmake-bridge.cfg.in
Log Message:
-----------
[libc++] Unify the benchmarks with the test suite (#101399)
Instead of building the benchmarks separately via CMake and running them
separately from the test suite, this patch merges the benchmarks into
the test suite and handles both uniformly.
As a result:
- It is now possible to run individual benchmarks like we run tests
(e.g. using libcxx-lit), which is a huge quality-of-life improvement.
- The benchmarks will be run under exactly the same configuration as
the rest of the tests, which is a nice simplification. This does
mean that one has to be careful to enable the desired optimization
flags when running benchmarks, but that is easy with e.g.
`libcxx-lit <...> --param optimization=speed`.
- Benchmarks can use the same annotations as the rest of the test
suite, such as `// UNSUPPORTED` & friends.
When running the tests via `check-cxx`, we only compile the benchmarks
because running them would be too time consuming. This introduces a bit
of complexity in the testing setup, and instead it would be better to
allow passing a --dry-run flag to GoogleBenchmark executables, which is
the topic of https://github.com/google/benchmark/issues/1827.
I am not really satisfied with the layering violation of adding the
%{benchmark_flags} substitution to cmake-bridge, however I believe
this can be improved in the future.
Commit: 427a5cf105c409993c812f4fb1868bac96fce0c5
https://github.com/llvm/llvm-project/commit/427a5cf105c409993c812f4fb1868bac96fce0c5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxx/cmake/caches/Generic-hardening-mode-fast-with-abi-breaks.cmake
M libcxx/docs/Hardening.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__configuration/abi.h
M libcxx/include/__iterator/bounded_iter.h
A libcxx/include/__iterator/static_bounded_iter.h
M libcxx/include/array
M libcxx/include/module.modulemap
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.back.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.front.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.subscript.pass.cpp
M libcxx/test/libcxx/input.output/iostream.format/print.fun/transcoding.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.back.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.front.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.indexing.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.iterators.pass.cpp
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++] Add support for bounded iterators in std::array (#110729)
This patch introduces a new kind of bounded iterator that knows the size
of its valid range at compile-time, as in std::array. This allows computing
the end of the range from the start of the range and the size, which requires
storing only the start of the range in the iterator instead of both the start
and the size (or start and end). The iterator wrapper is otherwise identical
in design to the existing __bounded_iter.
Since this requires changing the type of the iterators returned by
std::array, this new bounded iterator is controlled by an ABI flag.
As a drive-by, centralize the tests for std::array::operator[] and add
missing tests for OOB operator[] on non-empty arrays.
Fixes #70864
Commit: 21835ee28d47037137ea5a73ba466211b3e1a2d1
https://github.com/llvm/llvm-project/commit/21835ee28d47037137ea5a73ba466211b3e1a2d1
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
A llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll
Log Message:
-----------
[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)
Commit: 3ad0148020ca91cc288bffd8ad36e25f7555a3bb
https://github.com/llvm/llvm-project/commit/3ad0148020ca91cc288bffd8ad36e25f7555a3bb
Author: Md Asghar Ahmad Shahid <md.asghar.ahmad.shahid at intel.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/TransposeMatmul.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/generalize-named-ops.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/python/dialects/linalg/ops.py
M mlir/test/python/integration/dialects/linalg/opsrun.py
M mlir/test/python/integration/dialects/transform.py
M mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
Log Message:
-----------
[MLIR][Linalg] Re-land linalg.matmul move to ODS. + Remove/update failing obsolete OpDSL tests. (#115319)
The earlier PR(https://github.com/llvm/llvm-project/pull/104783) which
introduces
transpose and broadcast semantic to linalg.matmul was reverted due to
two failing
OpDSL test for linalg.matmul.
Since linalg.matmul is now defined using TableGen ODS instead of
Python-based OpDSL,
these test started failing and needs to be removed/updated.
This commit removes/updates the failing obsolete tests from below files.
All other files
were part of earlier PR and just cherry picked.
"mlir/test/python/integration/dialects/linalg/opsrun.py"
"mlir/test/python/integration/dialects/transform.py"
---------
Co-authored-by: Renato Golin <rengolin at systemcall.eu>
Commit: c8a7f14b276fcea68c50ee6b9007680867d2393e
https://github.com/llvm/llvm-project/commit/c8a7f14b276fcea68c50ee6b9007680867d2393e
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
Log Message:
-----------
[Backend] Add clearSubtargetMap API for TargetMachine. (#112383)
- [x] Add `clearSubtargetInfo` API to TargetMachine and each backend to
make it possible to release memory used in each backend's
`SubtargetInfo` map if needed. Keep this API as `protected` so that it
will be used with precautions.
Commit: 79fd61575977cb792af66b442fc2c6fbe837ebe4
https://github.com/llvm/llvm-project/commit/79fd61575977cb792af66b442fc2c6fbe837ebe4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/segmented-stores.ll
Log Message:
-----------
[SLP][NFC]Add a test with the segmented loads, NFC
Commit: c87d198cd964f37343083848f8fdd58bb0b00156
https://github.com/llvm/llvm-project/commit/c87d198cd964f37343083848f8fdd58bb0b00156
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.cpp
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
Log Message:
-----------
[ORC] Switch to new visibility macros for JIT debug symbols (#113848)
Use LLVM_ALWAYS_EXPORT for __jit_debug_descriptor and
__jit_debug_register_code so there exported even if LLVM is not built as
a shared library.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
windows #109483.
Commit: c3e9f4845452f7e752014773425745c9fb5558d1
https://github.com/llvm/llvm-project/commit/c3e9f4845452f7e752014773425745c9fb5558d1
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn] port 4d4024e1edf3
Commit: ec05b883653ba1bb9e92399f78b99a9d9342efc0
https://github.com/llvm/llvm-project/commit/ec05b883653ba1bb9e92399f78b99a9d9342efc0
Author: Devajith <devajith.valaparambil.sreeramaswamy at cern.ch>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/LineEditor/LineEditor.h
M llvm/lib/LineEditor/LineEditor.cpp
Log Message:
-----------
[lineeditor] Add `setHistorySize()` method for adjusting history size (#110092)
This patch adds a `setHistorySize` method to `LineEditor`.
This is particularly useful for tools like `clang-repl`, `clang-query`,
`mlir-query`, and other REPL interfaces, where managing history size
might be needed.
Commit: 7aa02f9e3f90b13371e34f65f2828f534f935607
https://github.com/llvm/llvm-project/commit/7aa02f9e3f90b13371e34f65f2828f534f935607
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port c6f3b7bcd0596d3 (libc++ __config_site HAS_NO -> HAS)
Commit: 85eec89600085a054650585d3a3287a6e0a93a50
https://github.com/llvm/llvm-project/commit/85eec89600085a054650585d3a3287a6e0a93a50
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] Disable new dwarf5 integral member tests on Windows
Added by https://github.com/llvm/llvm-project/pull/111859
Due to:
https://lab.llvm.org/buildbot/#/builders/141/builds/3691
This is not uncommon with DWARF testing on Windows. We may be
discarding the required information during linking.
I will look into it next week.
Commit: 24e2e259a06d9aa67dc278ac24dcb98da9dd63f6
https://github.com/llvm/llvm-project/commit/24e2e259a06d9aa67dc278ac24dcb98da9dd63f6
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
A clang/test/C/C2y/n3344.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Implement WG14 N3344 (#115313)
https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3344.pdf
This paper disallows a single `void` parameter from having qualifiers or
storage class specifiers. Clang has diagnosed most of these as an error
for a long time, but `register void` was previously accepted in all C
language modes and is now being rejected in all C language modes.
Commit: d74b1f029dcb7a89820cc5163925a113b10e64e2
https://github.com/llvm/llvm-project/commit/d74b1f029dcb7a89820cc5163925a113b10e64e2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
A llvm/test/Transforms/FunctionAttrs/vector-of-pointers-getunderlyingobject-crash.ll
Log Message:
-----------
ValueTracking: Do not return nullptr from getUnderlyingObject (#115258)
Fixup for 29a5c054e6d56a912ed5ba3f84e8ca631872db8b. The failure case
should return the last value found.
Commit: 9a0e0f543e6d491beaf9d64751be21d9afb4c7bb
https://github.com/llvm/llvm-project/commit/9a0e0f543e6d491beaf9d64751be21d9afb4c7bb
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3344.c
Log Message:
-----------
Fix failing test bot
This addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11070
Commit: 76a52db1edbd681058c291da0314af24b42925a3
https://github.com/llvm/llvm-project/commit/76a52db1edbd681058c291da0314af24b42925a3
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/test/Transforms/OpenMP/add_attributes.ll
Log Message:
-----------
[OpenMP] Add missing SExt attributes on i32 args. (#115242)
__kmpc_omp_taskwait_deps_51 arguments fixed.
Commit: e373ba46bb42790dc7aba4c1d7ba0c1590d5e7f4
https://github.com/llvm/llvm-project/commit/e373ba46bb42790dc7aba4c1d7ba0c1590d5e7f4
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/tools/llvm-objdump/XCOFF/private-header-auxiliary.test
M llvm/tools/llvm-objdump/XCOFFDump.cpp
Log Message:
-----------
[llvm-objdump] Implement decoding auxiliary header for xcoff with llvm-objdump --private-headers (#105682)
Implement decoding auxiliary header of XCOFF object file with
llvm-objdump --private-headers
Commit: 8449bf3d2137c467cd57a3a80663a9714dd57652
https://github.com/llvm/llvm-project/commit/8449bf3d2137c467cd57a3a80663a9714dd57652
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
Add release note for WG14 N3298
Commit: 03baa0ad6140789fc2851f655a4b88c938ec5e14
https://github.com/llvm/llvm-project/commit/03baa0ad6140789fc2851f655a4b88c938ec5e14
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Headers/avxintrin.h
M clang/test/CodeGen/X86/avx-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm256_set_pd/_mm256_set_ps/_mm256_set1_pd/_mm256_set1_ps/_mm256_setr_pd/_mm256_setr_ps
Commit: 39e6dc09d2fe824647bc168fbe96f1fc57cb0998
https://github.com/llvm/llvm-project/commit/39e6dc09d2fe824647bc168fbe96f1fc57cb0998
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/avx-builtins.c
Log Message:
-----------
[clang][x86] avx-builtins.c - reorder tests to keep alpha sorting order. NFC.
Commit: 522880cb99b0573d8689eee083b28af18ff3f9c2
https://github.com/llvm/llvm-project/commit/522880cb99b0573d8689eee083b28af18ff3f9c2
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv.c
Log Message:
-----------
[compiler-rt][RISCV] Avoid using __init_riscv_feature_bits as a direc… (#115316)
…t constructor
`__init_riscv_feature_bits` takes an argument that can be
platform-specific, potentially pointing to the VDSO address of the
hwprobe system call for Linux. However, marking it as a constructor does
not guarantee that 0/NULL will always be passed to this argument, which
may result in treating an uninitialized or garbage value as a pointer to
hwprobe, leading to a crash.
The simplest solution is to introduce a small constructor function to
ensure that the platform-specific argument is set to 0/NULL.
Commit: 392807ec3e7243fee98bec5d59ea8ea58ad022cd
https://github.com/llvm/llvm-project/commit/392807ec3e7243fee98bec5d59ea8ea58ad022cd
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
Log Message:
-----------
[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)
This patch follows https://github.com/llvm/llvm-project/pull/112477.
Previously `-fsanitize=shadow-call-stack` (which get transform to
`Attribute::ShadowCallStack`) is used for enable both hardware and
software shadow stack, and another option `-force-sw-shadow-stack` is
needed if the user wants to use the software shadow stack where hardware
software shadow stack could be supported. It decouples both by using the
string attribute `hw-shadow-stack` to distinguish from the software
shadow stack attribute.
Commit: 5a8956ea8b8ac1ef7b6c4e42553a55063ab699ea
https://github.com/llvm/llvm-project/commit/5a8956ea8b8ac1ef7b6c4e42553a55063ab699ea
Author: Keith Packard <keithp at keithp.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
M compiler-rt/lib/builtins/aarch64/sme-libc-routines.c
M libunwind/src/UnwindRegistersRestore.S
M libunwind/src/UnwindRegistersSave.S
Log Message:
-----------
[compiler-rt][libunwind] Support aarch64 without FPU (#111235)
These two libraries don't build for `-march=armv8-a+nofp
-mabi=aapcs-soft` as a couple of uses of floating point instructions and
registers have crept in.
In libunwind, skip save/restore of FPU registers on targets without them.
In compiler-rt, fall back to the old C implementation of __arm_sc_memset when
the target doesn't have an FPU.
---------
Signed-off-by: Keith Packard <keithp at keithp.com>
Commit: ef353b02b0728f2328c3494c70dc426d58d23508
https://github.com/llvm/llvm-project/commit/ef353b02b0728f2328c3494c70dc426d58d23508
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
A clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
R clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-return-value.cpp
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
Introduce a new WebKit checker for a unchecked call arguments (#113708) (#114522)
This PR introduces alpha.webkit.UncheckedCallArgsChecker which detects a
function argument which is a raw reference or a raw pointer to a
CheckedPtr capable object.
Commit: 9fd3c4115cf2cd3da1405e1f2c38d53582b5dc81
https://github.com/llvm/llvm-project/commit/9fd3c4115cf2cd3da1405e1f2c38d53582b5dc81
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxx/include/__expected/unexpected.h
M libcxx/test/std/utilities/expected/expected.unexpected/equality.pass.cpp
Log Message:
-----------
[libc++] Fix `unexpected` heterogeneous comparison (#115249)
Currently, libc++ incorrectly rejects heterogeneous comparison of
`unexpected`, because the `operator==` is only a hidden friend of
`unexpected<_Err>` but not of `unexpected<_Err2>`. We need to call the
`error()` member function on `__y`.
Fixes #115326
Commit: f58757b8dc167809b69ec00f9b5ab59281df0902
https://github.com/llvm/llvm-project/commit/f58757b8dc167809b69ec00f9b5ab59281df0902
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Make GetMinMaxCost support FixedVectorType when REVEC is enabled. (#114946)
Commit: c1ead03e01e47c797e32a3f981ace5ef21eebd18
https://github.com/llvm/llvm-project/commit/c1ead03e01e47c797e32a3f981ace5ef21eebd18
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/test/C/C2y/n3364.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add conformance test for WG14 N3364 (#115332)
This paper is defining the translation-time behavior of initialization
with a signaling NaN. Clang has always supported the correct behavior.
Commit: ed6c106e6a9e4855f9bf328674be3d3c6ceb9586
https://github.com/llvm/llvm-project/commit/ed6c106e6a9e4855f9bf328674be3d3c6ceb9586
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Replace errorCount with errCount(ctx)
to reduce reliance on the global context.
Commit: 9501af5f92bb31fa9527d12a4b17b88d9fd651c4
https://github.com/llvm/llvm-project/commit/9501af5f92bb31fa9527d12a4b17b88d9fd651c4
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/LineEditor/LineEditor.h
M llvm/lib/LineEditor/LineEditor.cpp
Log Message:
-----------
Revert "[lineeditor] Add `setHistorySize()` method for adjusting history size (#110092)"
This reverts commit ec05b883653ba1bb9e92399f78b99a9d9342efc0.
Reason: buildbot breakage (https://lab.llvm.org/buildbot/#/builders/66/builds/5904)
/home/b/sanitizer-x86_64-linux/build/llvm-project/llvm/lib/LineEditor/LineEditor.cpp:23:15: error: unused variable 'DefaultHistorySize' [-Werror,-Wunused-const-variable]
23 | constexpr int DefaultHistorySize = 800;
| ^~~~~~~~~~~~~~~~~~
1 error generated.
Commit: c980cc086989a5910c4e6321063e805f767a3b90
https://github.com/llvm/llvm-project/commit/c980cc086989a5910c4e6321063e805f767a3b90
Author: Job Henandez Lara <jobhdezlara93 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libc/hdr/func/CMakeLists.txt
R libc/hdr/func/_Exit.h
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/at_quick_exit_test.cpp
M libc/test/src/stdlib/atexit_test.cpp
Log Message:
-----------
[libc] Remove _Exit proxy func header and use LIBC_NAMESPACE::_Exit in tests (#114904)
This improves/fixes this pr
https://github.com/llvm/llvm-project/pull/114718. In this PR we removed
the _Exit proxy func because it was not needed. Instead we used
`LIBC_NAMESPACE::_Exit`
Commit: f8b96160feb99b3fc37b1857caf2abcfea7e5a06
https://github.com/llvm/llvm-project/commit/f8b96160feb99b3fc37b1857caf2abcfea7e5a06
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CXX/temp/temp.res/p4.cpp
Log Message:
-----------
[Clang] skip default argument instantiation for non-defining friend declarations (#113777)
This fixes a crash when instantiating default arguments for templated
friend function declarations which lack a definition.
There are implementation limits which prevents us from finding the
pattern for such functions, and this causes difficulties
setting up the instantiation scope for the function parameters.
This patch skips instantiating the default argument in these cases,
which causes a minor regression in error recovery, but otherwise avoids
the crash.
Fixes #113324
Commit: e8b7d8bfb5692d73df3d8e728925f62fb3bd9ec5
https://github.com/llvm/llvm-project/commit/e8b7d8bfb5692d73df3d8e728925f62fb3bd9ec5
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/attr-target-clones-aarch64.c
M clang/test/SemaCXX/attr-target-version.cpp
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/lib/Target/AArch64/AArch64FMV.td
Log Message:
-----------
[FMV][AArch64] Remove features which expose non exploitable runtime behavior. (#114387)
Features ebf16, memtag3, and rpres allow existing instructions to behave
differently depending on the value of certain control registers. FMV
does not read the content of control registers making these features
unsuitable for runtime dispatch. See the ACLE patch for more info:
https://github.com/ARM-software/acle/pull/355
Commit: 7c63b10fce562ce2c0caa436fd163ad57e011bf6
https://github.com/llvm/llvm-project/commit/7c63b10fce562ce2c0caa436fd163ad57e011bf6
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
[NFC][AMDGPU] Guard FP8 related instructions properly (#115211)
Currently `fp8-insts` is used in the front end to guard builtins, but the
corresponding feature is never used in tablegen files to guard those
instructions. Intead, it uses `isGFX940Plus`. The `gfx9-4-generic target` doesn't
support those instructions, thus we need to update the guard properly.
Commit: ef8d88ca1af0a8348bc616e93d50919462224d9b
https://github.com/llvm/llvm-project/commit/ef8d88ca1af0a8348bc616e93d50919462224d9b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Support scalar to array data transfer (#115273)
Do it via descriptor assignment until we have a more efficient way.
Commit: c13258ac495af2cca829752405123b5c9b70fa80
https://github.com/llvm/llvm-project/commit/c13258ac495af2cca829752405123b5c9b70fa80
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/SyntheticSections.cpp
M lld/test/ELF/arm-fix-cortex-a8-blx.s
M lld/test/ELF/arm-fix-cortex-a8-recognize.s
Log Message:
-----------
[ELF] Replace log with Log(ctx)
Commit: 9a43ae5514d7fa306b58a221fe80e1f87259e7b8
https://github.com/llvm/llvm-project/commit/9a43ae5514d7fa306b58a221fe80e1f87259e7b8
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
[AMDGPU] Introduce a "new" target feature `xf32-insts` (#115214)
The feature itself is not new. Just to use it to guard corresponding instructions. No test is needed, like its parent PR.
Commit: 6ca50a2593641f45b5310d907e6323f5eb367dfa
https://github.com/llvm/llvm-project/commit/6ca50a2593641f45b5310d907e6323f5eb367dfa
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libclc/generic/lib/relational/binary_def.inc
M libclc/generic/lib/relational/unary_def.inc
Log Message:
-----------
[libclc] Correct use of CLC macro on two definitions
_CLC_DECL is for declarations and _CLC_DEF for definitions, as the names
imply.
No change to any bitcode module.
Commit: 5f4e3a3ced525c84a5268e51a56fe47b5456fd81
https://github.com/llvm/llvm-project/commit/5f4e3a3ced525c84a5268e51a56fe47b5456fd81
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/APINotes/Types.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesTypes.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/test/APINotes/Inputs/Headers/Lifetimebound.apinotes
M clang/test/APINotes/Inputs/Headers/Lifetimebound.h
M clang/test/APINotes/lifetimebound.cpp
Log Message:
-----------
[clang] Support 'this' position for lifetimebound attribute (#115021)
This patch makes the position -1 interpreted as the position for 'this'.
Adds some basic infrastructure and support for lifetimebound attribute.
Commit: bc7e099aa82d44b5682ec3dbd1322ccc5000a50d
https://github.com/llvm/llvm-project/commit/bc7e099aa82d44b5682ec3dbd1322ccc5000a50d
Author: dyung <douglas.yung at sony.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
R llvm/test/CodeGen/MIR/AMDGPU/num-phys-vgpr-spill-lanes.ll
Log Message:
-----------
Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)
Reverts llvm/llvm-project#115291
Reverting due to test failures on many bots including
https://lab.llvm.org/buildbot/#/builders/174/builds/8049
Commit: 7760ae7b608193a410b71df7ae7daccf2a6b09c1
https://github.com/llvm/llvm-project/commit/7760ae7b608193a410b71df7ae7daccf2a6b09c1
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
Log Message:
-----------
[X86] Switch to the new symbol visibility macros (#109982)
Switch LLVMInitialize* functions to new the symbol visibility macros
that will work for windows.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
windows.
Commit: bf30b6c33c17d43402d23f8cade450437fcff800
https://github.com/llvm/llvm-project/commit/bf30b6c33c17d43402d23f8cade450437fcff800
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/CodeGenHLSL/builtins/dot4add_u8packed.hlsl
A clang/test/SemaHLSL/BuiltIns/dot4add_u8packed-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/dot4add_u8packed.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
Log Message:
-----------
[HLSL][SPIRV][DXIL] Implement `dot4add_u8packed` intrinsic (#115068)
```- create a clang built-in in Builtins.td
- link dot4add_u8packed in hlsl_intrinsics.h
- add lowering to spirv backend through expansion of operation as OpUDot is missing up to SPIRV 1.6 in SPIRVInstructionSelector.cpp
- add lowering to spirv backend using OpUDot if applicable SPIRV version or SPV_KHR_integer_dot_product is enabled
- add dot4add_u8packed intrinsic to IntrinsicsDirectX.td and mapping to DXIL.td op Dot4AddU8Packed
- add tests for HLSL intrinsic lowering to dx/spv intrinsic in dot4add_u8packed.hlsl
- add tests for sema checks in dot4add_u8packed-errors.hlsl
- add test of spir-v lowering in SPIRV/dot4add_u8packed.ll
- add test to dxil lowering in DirectX/dot4add_u8packed.ll
```
Resolves #99219
Commit: e8b70e97447dc0d93a277b0373345d3a1bae1aa9
https://github.com/llvm/llvm-project/commit/e8b70e97447dc0d93a277b0373345d3a1bae1aa9
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/Record.cpp
M llvm/test/TableGen/true-false.td
Log Message:
-----------
[TableGen] Make `!and` and `!or` short-circuit (#113963)
The idea is that by preemptively simplifying the result of `!and` and `!or`, we can fold
some of the conditional operators, like `!if` or `!cond`, as early as
possible.
Commit: 7f60f1312ae007d645fc96618db1238baea088b9
https://github.com/llvm/llvm-project/commit/7f60f1312ae007d645fc96618db1238baea088b9
Author: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
A llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll
Log Message:
-----------
[AMDGPU] Fix resource usage information for unnamed functions (#115320)
Resource usage information would try to overwrite unnamed functions if
there are multiple within the same compilation unit. This aims to either
use the `MCSymbol` assigned to the unnamed function (i.e.,
`CurrentFnSym`), or, rematerialize the `MCSymbol` for the unnamed
function.
Commit: b970a78335a3d46a6dbdaa762e7285e9a90c969c
https://github.com/llvm/llvm-project/commit/b970a78335a3d46a6dbdaa762e7285e9a90c969c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
I've added 2 custom nodes for CTZW and CLZW to match SelectionDAG. For
cpopw we pattern match G_AND+G_CTPOP in isel.
Commit: 22b4b1ab1050b4210f3c5dae54c0503ef7ad85f3
https://github.com/llvm/llvm-project/commit/22b4b1ab1050b4210f3c5dae54c0503ef7ad85f3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
Revert "[SLP][REVEC] Make GetMinMaxCost support FixedVectorType when REVEC is enabled. (#114946)"
This reverts commit f58757b8dc167809b69ec00f9b5ab59281df0902.
Failing buildbots:
https://lab.llvm.org/buildbot/#/builders/174/builds/8058
https://lab.llvm.org/buildbot/#/builders/127/builds/1357
Commit: ef73533f36d5f2132630e88899b5e64999cb8364
https://github.com/llvm/llvm-project/commit/ef73533f36d5f2132630e88899b5e64999cb8364
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxx/include/__utility/small_buffer.h
Log Message:
-----------
[z/OS][libc++] Remove `align_val_t` dependency in small_buffer.h (#114396)
Rewriting `__alloc()` and `__dealloc()` template functions to avoid errors when `small_buffer.h` is
included in the modules LIT tests. For example:
```
test-suite-install/include/c++/v1/__utility/small_buffer.h:69:81: error: use of undeclared identifier 'align_val_t'
# | 69 | byte* __allocation = static_cast<byte*>(::operator new[](sizeof(_Stored), align_val_t{alignof(_Stored)}));
# | | ^
```
Commit: 7bd9be2e0a74e6d17ec3f95ff364a4461dec4dbe
https://github.com/llvm/llvm-project/commit/7bd9be2e0a74e6d17ec3f95ff364a4461dec4dbe
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/HIPUtility.cpp
Log Message:
-----------
[Driver] Use heterogenous lookups with std::set (NFC) (#115259)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: c714f928b2f9ab3dd481f272a2aa72b83fd0562e
https://github.com/llvm/llvm-project/commit/c714f928b2f9ab3dd481f272a2aa72b83fd0562e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/InstallAPI/Frontend.cpp
Log Message:
-----------
[InstallAPI] Call DenseMap::find without constructing std::string (NFC) (#115260)
KnownIncludes is of DenseMap<StringRef, HeaderType>, so we don't need
to allocate a temporary instance of std::string.
Commit: 937e5069a740837ea3cb466df8e75a53f6d48254
https://github.com/llvm/llvm-project/commit/937e5069a740837ea3cb466df8e75a53f6d48254
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/Internalize.cpp
Log Message:
-----------
[IPO] Simplify code with DenseMap::operator[] (NFC) (#115261)
Commit: 1ae5ecca4afb5134899d79e446afd0296d1ed5ef
https://github.com/llvm/llvm-project/commit/1ae5ecca4afb5134899d79e446afd0296d1ed5ef
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[Utils] Avoid repeated hash lookups (NFC) (#115262)
Commit: b02e5bc5b1be9d94689ebe1cf1244b7da540fb19
https://github.com/llvm/llvm-project/commit/b02e5bc5b1be9d94689ebe1cf1244b7da540fb19
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/ObjCARC/ProvenanceAnalysis.cpp
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/LoopPredication.cpp
M llvm/lib/Transforms/Scalar/LowerWidenableCondition.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
Log Message:
-----------
[Transforms] Remove unused includes (NFC) (#115263)
Identified with misc-include-cleaner.
Commit: 4ac891cdd286b251a445c1e3a77d56f55a29858b
https://github.com/llvm/llvm-project/commit/4ac891cdd286b251a445c1e3a77d56f55a29858b
Author: Job Henandez Lara <jobhdezlara93 at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libc/test/src/stdlib/at_quick_exit_test.cpp
M libc/test/src/stdlib/atexit_test.cpp
Log Message:
-----------
[libc] Add the `src/stdlib/_Exit.h` header to `at_quick_exit_test.cpp` and `atexit_test.cpp` (#115351)
Hello, I merged this https://github.com/llvm/llvm-project/pull/114904 a
few mins ago and the tests failed because i did not add the header
`src/stdlib/_Exit.h` in `at_quick_exit_test.cpp` and `atexit_test.cpp`.
I ran both builds/tests and everything was good. thanks
Commit: b7a8f5f4c978856852bc39dc3d29265756e37cfe
https://github.com/llvm/llvm-project/commit/b7a8f5f4c978856852bc39dc3d29265756e37cfe
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Exit early from attempt-to-reorder, if it is useless
Adds early exits, which just save compile time. It can exit earl, if the
total number of scalars is 2, or all scalars are constant, or the opcode
is the same and not alternate. In this case reordering will not happen
and compiler can exit early to save compile time
Commit: 200afcf6128911892d61c2a331186fe9a4da2a3e
https://github.com/llvm/llvm-project/commit/200afcf6128911892d61c2a331186fe9a4da2a3e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV] Add combines_for_extload to RISCVPostLegalizerCombiner.
Commit: 60e3a81c4299baf80e7b80db9cb8368223ee9546
https://github.com/llvm/llvm-project/commit/60e3a81c4299baf80e7b80db9cb8368223ee9546
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/test/API/functionalities/abbreviation/TestAbbreviations.py
Log Message:
-----------
[lldb] Add builtin e alias for expression (#115359)
The changes in 461f859a72 (llvm/llvm-project#65974) resulted in a change
in behavior not just for completion, but also for selection of inexect
commands.
Since many use `e` to mean `expression`, this change adds an alias for
`e`. Note that the referenced change similarly aliases `h` to `help`.
Commit: 3f4df523152054224709ba88e9afd4efa22021c9
https://github.com/llvm/llvm-project/commit/3f4df523152054224709ba88e9afd4efa22021c9
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 427a5cf105c4
Commit: e9cb9285ced8d914048e0ccaf1900ffc75bdeee4
https://github.com/llvm/llvm-project/commit/e9cb9285ced8d914048e0ccaf1900ffc75bdeee4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
Log Message:
-----------
[gn build] Port cacbe71af7b1
Commit: 64c921875a833136e7417c9077f55cc0c37773b7
https://github.com/llvm/llvm-project/commit/64c921875a833136e7417c9077f55cc0c37773b7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
Log Message:
-----------
[gn build] Port d2aff182d379
Commit: 3deee235986802694175259e078dfad0edcb40ed
https://github.com/llvm/llvm-project/commit/3deee235986802694175259e078dfad0edcb40ed
Author: Ian Wood <75152913+IanWood1 at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
Log Message:
-----------
[mlir] IntegerRangeAnalysis: don't loop over splat attr (#115229)
If the `DenseIntElementsAttr` is a splat value, there is no need to loop
over the entire attr. Instead, just update with the splat value.
Commit: 1fef4ad188dfad0e39f93e4b0330780118f27305
https://github.com/llvm/llvm-project/commit/1fef4ad188dfad0e39f93e4b0330780118f27305
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
R llvm/test/MC/Disassembler/AMDGPU/vinterp-fake16.txt
A llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
Log Message:
-----------
[AMDGPU][True16][MC] update true16 flag on vinterp test (#115356)
A non-funcitonal change.
update true16 flag on vinterp dasm test
Commit: 09fb01a5e564a0cb7c121e1cc529e9aa30d95108
https://github.com/llvm/llvm-project/commit/09fb01a5e564a0cb7c121e1cc529e9aa30d95108
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
Log Message:
-----------
[gn build] Enable hwasan for aarch64 Android (#115219)
Commit: 15d1560ea4047a2b4b14c826767089f538ddda70
https://github.com/llvm/llvm-project/commit/15d1560ea4047a2b4b14c826767089f538ddda70
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttributeCommonInfo.h
M clang/lib/Basic/Attributes.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[Clang] Improve EmitClangAttrSpellingListIndex (#114899)
`EmitClangAttrSpellingListIndex()` performs a lot of unnecessary string
comparisons which is wasteful in time and stack space. This commit
attempts to refactor this method to be more performant.
Commit: dd1c99bac4dc1d5ceeadc79dd31fa12f3e615f18
https://github.com/llvm/llvm-project/commit/dd1c99bac4dc1d5ceeadc79dd31fa12f3e615f18
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[TableGen] Fix a warning
This patch fixes:
clang/utils/TableGen/ClangAttrEmitter.cpp:3869:51: error: captured
structured bindings are a C++20 extension
[-Werror,-Wc++20-extensions]
Commit: 1f2509993e6e0717b547b5214b06550af4f3008f
https://github.com/llvm/llvm-project/commit/1f2509993e6e0717b547b5214b06550af4f3008f
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/updateCounter.ll
Log Message:
-----------
[DirectX] introducing lowering for `bufferUpdateCounter` (#115041)
- Adding custom lowering for `bufferUpdateCounter`
- introduces llvm intrinsic `int_dx_updateCounter`
- adds tests
Closes #92147
---------
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Commit: 87feafc391ab1e35997994ad378af727e4947c67
https://github.com/llvm/llvm-project/commit/87feafc391ab1e35997994ad378af727e4947c67
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
Log Message:
-----------
[RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
RORW/ROLW target opcodes are added to match SelectionDAG.
The regression in rv64zbb-zbkb.ll requires factoring
isSExtCheaperThanZExt into the G_ANYEXT constant folder. That requires
some interface changes so I didn't do it in this patch.
Commit: de41b137ddb68b5172f1ab042b0b0b495afbb490
https://github.com/llvm/llvm-project/commit/de41b137ddb68b5172f1ab042b0b0b495afbb490
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A offload/cmake/caches/Offload.cmake
M openmp/docs/SupportAndFAQ.rst
Log Message:
-----------
[Offload] Provide a CMake cache file to easily build offloading (#115074)
Summary:
This patch adds a cache file that will automatically enable openpm,
offload, and all the fancy GPU libraries.
Commit: e109c493210572535de25950e7b83f74b8d11a6a
https://github.com/llvm/llvm-project/commit/e109c493210572535de25950e7b83f74b8d11a6a
Author: Pranav Kant <prka at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLFunctionalExtras.h
Log Message:
-----------
Revert "Add clang::lifetimebound annotation to llvm::function_ref (#1… (#115376)
…15019)"
This reverts commit 9f796159f28775b3f93d77e173c1fd3413c2e60e.
This is breaking compiler-rt/lib/sanitizer_common/...
Author knows about the breakage.
Commit: dec38399795a7f238508ee100e5b057165724a60
https://github.com/llvm/llvm-project/commit/dec38399795a7f238508ee100e5b057165724a60
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP][NFC]Add a test with the missed vectorization opportunity for stores with same address
Commit: ae9d0623ad65d84022bb4ed8446b6491451ae575
https://github.com/llvm/llvm-project/commit/ae9d0623ad65d84022bb4ed8446b6491451ae575
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as
fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as
fcvt.s.wu. There are still some regressions that suggest we should match
g_zero_extend in zexti32.
Commit: 7475156d49406785a974b1205d11fe3de9c1553e
https://github.com/llvm/llvm-project/commit/7475156d49406785a974b1205d11fe3de9c1553e
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
A clang/test/CodeGen/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
Log Message:
-----------
[Clang] Add __builtin_counted_by_ref builtin (#114495)
The __builtin_counted_by_ref builtin is used on a flexible array
pointer and returns a pointer to the "counted_by" attribute's COUNT
argument, which is a field in the same non-anonymous struct as the
flexible array member. This is useful for automatically setting the
count field without needing the programmer's intervention. Otherwise
it's possible to get this anti-pattern:
ptr = alloc(<ty>, ..., COUNT);
ptr->FAM[9] = 42; /* <<< Sanitizer will complain */
ptr->count = COUNT;
To prevent this anti-pattern, the user can create an allocator that
automatically performs the assignment:
#define alloc(TY, FAM, COUNT) ({ \
TY __p = alloc(get_size(TY, COUNT)); \
if (__builtin_counted_by_ref(__p->FAM)) \
*__builtin_counted_by_ref(__p->FAM) = COUNT; \
__p; \
})
The builtin's behavior is heavily dependent upon the "counted_by"
attribute existing. It's main utility is during allocation to avoid
the above anti-pattern. If the flexible array member doesn't have that
attribute, the builtin becomes a no-op. Therefore, if the flexible
array member has a "count" field not referenced by "counted_by", it
must be set explicitly after the allocation as this builtin will
return a "nullptr" and the assignment will most likely be elided.
---------
Co-authored-by: Bill Wendling <isanbard at gmail.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
https://github.com/llvm/llvm-project/commit/bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)
Enable pattern matching from "x<<32-y>>32-y" to "bfe x, 0, y" when we
know y is in [0,31].
This is the follow-up for the PR:
https://github.com/llvm/llvm-project/pull/114279 to fix the issue:
https://github.com/llvm/llvm-project/issues/114282
Commit: 62db1c8a076c7167e404412182f4a8915f4ff6ee
https://github.com/llvm/llvm-project/commit/62db1c8a076c7167e404412182f4a8915f4ff6ee
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP]Better decision making on whether to try stores packs for vectorization
Since the stores are sorted by distance, comparing the indices in the
original array and early exit, if the index is less than the index of
the last store, not always the best strategy. Better to remove such
stores explicitly to try better to check for the vectorization
opportunity.
Fixes #115008
Commit: c02da382471fd0b338af76ce220e9567e3cb854a
https://github.com/llvm/llvm-project/commit/c02da382471fd0b338af76ce220e9567e3cb854a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
Log Message:
-----------
[RISCV] Add tests for deinterleave(2-8) shuffles
Commit: 02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
https://github.com/llvm/llvm-project/commit/02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Match single source deinterleave shuffles for vnsrl (#114878)
We had previously only been matching the two source case where both
sources came from a wider source type. We can also match the single
source case - provided the result is m4 or smaller because we will need
a wider type to represent the source.
The main goal of this to ensure that vnsrl matching is robust to a
possible change in canonicalization for length changing shuffles that
I'm considering, but it has the nice effect of picking up a few cases we
missed along the way.
Commit: e189d61924ba0165b3a344c3d945b3e2aa373485
https://github.com/llvm/llvm-project/commit/e189d61924ba0165b3a344c3d945b3e2aa373485
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
A llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Add extractCallsFromIR (#115218)
This patch adds extractCallsFromIR, a function to extract calls from
the IR, which will be used to undrift call site locations in the
MemProf profile.
In a nutshell, the MemProf undrifting works as follows:
- Extract call site locations from the IR.
- Extract call site locations from the MemProf profile.
- Undrift the call site locations with longestCommonSequence.
This patch implements the first bullet point above. Specifically,
given the IR, the new function returns a map from caller GUIDs to
lists of corresponding call sites. For example:
Given:
foo() {
f1();
f2(); f3();
}
extractCallsFromIR returns:
Caller: foo ->
{{(Line 1, Column 3), Callee: f1},
{(Line 2, Column 3), Callee: f2},
{(Line 2, Column 9), Callee: f3}}
where the line numbers, relative to the beginning of the caller, and
column numbers are sorted in the ascending order. The value side of
the map -- the list of call sites -- can be directly passed to
longestCommonSequence.
To facilitate the review process, I've only implemented basic features
in extractCallsFromIR in this patch.
- The new function extracts calls from the LLVM "call" instructions
only. It does not look into the inline stack.
- It does not recognize or treat heap allocation functions in any
special way.
I will address these missing features in subsequent patches.
Commit: 53e49f15ab0b9b03e5671faea6f7870914b8f0ea
https://github.com/llvm/llvm-project/commit/53e49f15ab0b9b03e5671faea6f7870914b8f0ea
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
Log Message:
-----------
[clang][serialization] Pass `ASTContext` explicitly (#115235)
This patch removes `ASTWriter::Context` and starts passing `ASTContext
&` explicitly to functions that actually need it. This is a
non-functional change with the end-goal of being able to write
lightweight PCM files with no `ASTContext` at all.
Commit: fd799add2186356dc19e81106a1428a2edf7c20b
https://github.com/llvm/llvm-project/commit/fd799add2186356dc19e81106a1428a2edf7c20b
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
Log Message:
-----------
Reapply "[libc++abi] Stop copying headers to the build directory"
This was needed before https://github.com/llvm/llvm-project/pull/115077
since the compiler-rt test build made assumptions about the build
layout of libc++ and libc++abi, but now they link against a local
installation of these libraries so we no longer need this workaround.
The last attempt at landing this was reverted due to buildbot failures
which should be fixed by https://github.com/llvm/llvm-zorg/pull/299.
Pull Request: https://github.com/llvm/llvm-project/pull/115379
Commit: 3b1b1271fb552c996d9fdfa9a997f33013dd275f
https://github.com/llvm/llvm-project/commit/3b1b1271fb552c996d9fdfa9a997f33013dd275f
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
A llvm/test/CodeGen/Xtensa/branch-relaxation.ll
M llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
Log Message:
-----------
[Xtensa] Implement support for the BranchRelaxation. (#113450)
Commit: 49ee6069db372ce326bc36678e745459868c3771
https://github.com/llvm/llvm-project/commit/49ee6069db372ce326bc36678e745459868c3771
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/FunctionLayout.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/lib/Core/FunctionLayout.cpp
M bolt/lib/Passes/LongJmp.cpp
A bolt/test/AArch64/compact-code-model.s
Log Message:
-----------
[BOLT][AArch64] Add support for compact code model (#112110)
Add `--compact-code-model` option that executes alternative branch
relaxation with an assumption that the resulting binary has less than
128MB of code. The relaxation is done in `relaxLocalBranches()`, which
operates on a function level and executes on multiple functions in
parallel.
Running the new option on AArch64 Clang binary produces slightly smaller
code and the relaxation finishes in about 1/10th of the time.
Note that the new `.text` has to be smaller than 128MB, *and* `.plt` has
to be closer than 128MB to `.text`.
Commit: faefedf7f8d520035a7c699baa12d5bb9bb93f49
https://github.com/llvm/llvm-project/commit/faefedf7f8d520035a7c699baa12d5bb9bb93f49
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/exp10m1f.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/exp10m1f.cpp
M libc/src/math/generic/explogxf.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/exp10m1f_test.cpp
A libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10m1f_test.cpp
Log Message:
-----------
[libc][math][c23] Add exp10m1f C23 math function (#87992)
Fixes #86503.
Commit: accd8f98be29fb086d83cd318eeba8e491fcb799
https://github.com/llvm/llvm-project/commit/accd8f98be29fb086d83cd318eeba8e491fcb799
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
Log Message:
-----------
[BOLT] Fix a warning
This patch:
bolt/lib/Passes/LongJmp.cpp:830:14: error: variable 'NumIterations'
set but not used [-Werror,-Wunused-but-set-variable]
Commit: 1cb119b168a6d24f32b05de7f22c7a06a0f0c407
https://github.com/llvm/llvm-project/commit/1cb119b168a6d24f32b05de7f22c7a06a0f0c407
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Instrumentation/BUILD.gn
Log Message:
-----------
[gn build] Port e189d61924ba
Commit: d4525b016f5a1ab2852acb2108742b2f9d0bd3bd
https://github.com/llvm/llvm-project/commit/d4525b016f5a1ab2852acb2108742b2f9d0bd3bd
Author: Egor Zhdan <e_zhdan at apple.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/AST/TemplateArgumentVisitor.h
Log Message:
-----------
[Clang] Dispatch default overloads of `TemplateArgumentVisitor` to the implementation
This fixes an issue where overriding
`clang::ConstTemplateArgumentVisitor::VisitTemplateArgument` in an
implementation visitor class did not have the desired effect: the
overload was not invoked when one of the visitor methods (e.g.
`VisitDeclarationArgument`) is not implemented, instead it dispatched to
`clang::ConstTemplateArgumentVisitor::VisitTemplateArgument` itself and
always returned a default-initialized result.
This makes `TemplateArgumentVisitor` and `ConstTemplateArgumentVisitor`
follow the implicit convention that is followed elsewhere in Clang AST,
in `RecursiveASTVisitor` and `TypeVisitor`.
Commit: cd022b7b2aa9e4a5762c4e82e24b228114956e3b
https://github.com/llvm/llvm-project/commit/cd022b7b2aa9e4a5762c4e82e24b228114956e3b
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
Log Message:
-----------
Revert "[mlir] IntegerRangeAnalysis: don't loop over splat..." (#115388)
Hitting assertion in IREE
https://github.com/iree-org/iree/actions/runs/11732283897/job/32684201665?pr=19066
```
iree-compile: /__w/iree/iree/third_party/llvm-project/mlir/include/mlir/IR/BuiltinAttributes.h:423: auto mlir::DenseElementsAttr::getValues() const [T = llvm::APInt]: Assertion `succeeded(range) && "element type cannot be iterated"' failed.
```
Reverts llvm/llvm-project#115229
Commit: 5b697ef5dd6b3e29e257e6099014bf8d8e77ac9a
https://github.com/llvm/llvm-project/commit/5b697ef5dd6b3e29e257e6099014bf8d8e77ac9a
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir] Update CODEOWNERS file for vector dialect (#115398)
Adding myself to stay updated on patches since I have been reviewing /
upstreaming things related to vector dialect.
Commit: 74e6478f81b646f4bcaf6236161e54c7cb239874
https://github.com/llvm/llvm-project/commit/74e6478f81b646f4bcaf6236161e54c7cb239874
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/callcont-fallthru.s
Log Message:
-----------
[BOLT] Set call to continuation count in pre-aggregated profile
#109683 identified an issue with pre-aggregated profile where a call to
continuation fallthrough edge count is missing (profile discontinuity).
This issue only affects pre-aggregated profile but not perf data since
LBR stack has the necessary information to determine if the trace (fall-
through) starts at call continuation, whereas pre-aggregated fallthrough
lacks this information.
The solution is to look at branch records in pre-aggregated profiles
that correspond to returns and assign counts to call to continuation
fallthrough:
- BranchFrom is in another function or DSO,
- BranchTo may be a call continuation site:
- not an entry point/landing pad.
Note that we can't directly check if BranchFrom corresponds to a return
instruction if it's in external DSO.
Keep call continuation handling for perf data (`getFallthroughsInTrace`)
[1] as-is due to marginally better performance. The difference is that
return-converted call to continuation fallthrough is slightly more
frequent than other fallthroughs since the former only requires one LBR
address while the latter need two that belong to the profiled binary.
Hence return-converted fallthroughs have larger "weight" which affects
code layout.
[1] `DataAggregator::getFallthroughsInTrace`
https://github.com/llvm/llvm-project/blob/fea18afeed39fe4435d67eee1834f0f34b23013d/bolt/lib/Profile/DataAggregator.cpp#L906-L915
Test Plan: added callcont-fallthru.s
Reviewers: maksfb, ayermolo, ShatianWang, dcci
Reviewed By: maksfb, ShatianWang
Pull Request: https://github.com/llvm/llvm-project/pull/109486
Commit: 1ced07e06e23659a96dbf6d53cd68d3bbbe3d792
https://github.com/llvm/llvm-project/commit/1ced07e06e23659a96dbf6d53cd68d3bbbe3d792
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: XFAIL DWARFv4 variant on Darwin (#115401)
https://github.com/llvm/llvm-project/pull/111859 fixed these tests for
DWARFv4 on Linux by adjusting the manual index. As part of the change we
unXFAILed these tests for DWARFv4 on all platforms. However, the manual
index isn't used on macOS so they're still broken. This patch reverts
the XFAIL on Darwin for DWARFv4.
Example CI failure:
```
FAIL: test_inline_static_members_dwarf4_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 153, in test_inline_static_members_dwarf4
self.check_inline_static_members("-gdwarf-4")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
```
Commit: 74deb661dfa9301ec6fed46114e59317b1503ded
https://github.com/llvm/llvm-project/commit/74deb661dfa9301ec6fed46114e59317b1503ded
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CXX/temp/temp.res/p4.cpp
Log Message:
-----------
Revert "[Clang] skip default argument instantiation for non-defining friend declarations without specialization info to meet [dcl.fct.default] p4" (#115404)
Reverts llvm/llvm-project#113777
Reverted due to regression reported here:
https://github.com/llvm/llvm-project/pull/113777#issuecomment-2463465741
Commit: 037f8044f69f88101620707af1db948e6804e080
https://github.com/llvm/llvm-project/commit/037f8044f69f88101620707af1db948e6804e080
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
Log Message:
-----------
[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)
fcopysign takes two operands, one for the magnitude and exponent and the
other for the sign. The result type is determined by the magnitude and
exponent operand. The sign operand does not need to be the same type.
Note, in IR all 3 types must match.
We have isel patterns for all possible combinations of types and the
legalizer thinks they are all legal, but we had no tests for it. I was
unable to find any combiner rules that would create an instruction with
mismatch types.
Commit: d3177d8b902bb2dc4a8d61cd51e2662e605d7515
https://github.com/llvm/llvm-project/commit/d3177d8b902bb2dc4a8d61cd51e2662e605d7515
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
Log Message:
-----------
[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
Commit: 1febd71b4dcff17130d3a605eda880de046bbd0f
https://github.com/llvm/llvm-project/commit/1febd71b4dcff17130d3a605eda880de046bbd0f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
A llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
Log Message:
-----------
[NVPTX] Add TTI support for folding isspacep in InferAS (#114486)
This change enables constant folding of '`@llvm.nvvm.isspacep.*`'
intrinsics if the address space can be propagated in InferAdressSpace.
Commit: 36d757f8406a00539228e15b44bb850936871421
https://github.com/llvm/llvm-project/commit/36d757f8406a00539228e15b44bb850936871421
Author: Adam Yang <hanbyang at microsoft.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
R llvm/test/CodeGen/DirectX/clamp-vec.ll
M llvm/test/CodeGen/DirectX/clamp.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
A llvm/test/CodeGen/SPIRV/opencl/clamp.ll
Log Message:
-----------
[HLSL][SPIRV] Added clamp intrinsic (#113394)
Fixes #88052
- Added the following intrinsics:
- `int_spv_uclamp`
- `int_spv_sclamp`
- `int_spv_fclamp`
- Updated DirectX counterparts to have the same three clamp intrinsics.
- Update the clamp.hlsl unit tests to include SPIRV
- Added the SPIRV specific tests
Commit: 4e668d5b27a339918bee4d994fca31d962519e80
https://github.com/llvm/llvm-project/commit/4e668d5b27a339918bee4d994fca31d962519e80
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/ELF_LoongArch_relocations.s
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/lit.local.cfg
Log Message:
-----------
[RuntimeDyld] Add LoongArch support
This is necessary for supporting function calls in LLDB expressions for
LoongArch.
This patch is inspired by #99336 and simply extracts the parts related
to RuntimeDyld.
Reviewed By: lhames
Pull Request: https://github.com/llvm/llvm-project/pull/114741
Commit: 1c8fca82a0f4ac6df5db539e96adcad143f5ebe7
https://github.com/llvm/llvm-project/commit/1c8fca82a0f4ac6df5db539e96adcad143f5ebe7
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/source/Plugins/ABI/CMakeLists.txt
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
A lldb/source/Plugins/ABI/LoongArch/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Log Message:
-----------
[lldb][LoongArch] Function calls support in lldb expressions
This patch adds desired feature flags in JIT compiler to enable
hard-float instructions if target supports them and allows to use floats
and doubles in lldb expressions.
Fited tests:
lldb-shell :: Expr/TestAnonNamespaceParamFunc.cpp
lldb-shell :: Expr/TestIRMemoryMap.test
lldb-shell :: Expr/TestStringLiteralExpr.test
lldb-shell :: SymbolFile/DWARF/debug-types-expressions.test
Similar as #99336
Depens on: https://github.com/llvm/llvm-project/pull/114741
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/114742
Commit: 889d67785905ea85cdb17b2bf2b4b6f010b641f5
https://github.com/llvm/llvm-project/commit/889d67785905ea85cdb17b2bf2b4b6f010b641f5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
Log Message:
-----------
clang/AMDGPU: Restore O3 checks in default-attributes.hip (#115238)
These were dropped in b1bcb7ca460fcd317bbc8309e14c8761bf8394e0 to
avoid some bot failures.
Commit: 4fb43c47ddf0138bf5cb64ec64dfb530bc7db051
https://github.com/llvm/llvm-project/commit/4fb43c47ddf0138bf5cb64ec64dfb530bc7db051
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
Log Message:
-----------
AMDGPU: Fold more scalar operations on frame index to VALU (#115059)
Further extend workaround for the lack of proper regbankselect
for frame indexes.
Commit: e520b28397fa7ad39a9934df65f45cbdf5514a84
https://github.com/llvm/llvm-project/commit/e520b28397fa7ad39a9934df65f45cbdf5514a84
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
A clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/WaveActiveCountBits.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveCountBits.ll
Log Message:
-----------
[DXIL][SPIRV] Lower `WaveActiveCountBits` intrinsic (#113382)
```
- add codegen for llvm builtin to spirv/directx intrinsic in CGBuiltin.cpp
- add lowering of spirv intrinsic to spirv backend in SPIRVInstructionSelector.cpp
- add lowering of directx intrinsic to dxil op in DXIL.td
- add test cases to illustrate passes
- add test case for semantic analysis
```
Resolves #80176
Commit: 8440ced89f232f71ad28a91cd88965548b3095b0
https://github.com/llvm/llvm-project/commit/8440ced89f232f71ad28a91cd88965548b3095b0
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lld/ELF/Thunks.cpp
Log Message:
-----------
[ELF] Change a Fatal to assert in addThunkAArch64. NFC
Commit: ee1608dd8e6d06d5aa6e62d7bbb6d60bae7bb5a5
https://github.com/llvm/llvm-project/commit/ee1608dd8e6d06d5aa6e62d7bbb6d60bae7bb5a5
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MISched] Set DumpDirection after initPolicy (#115112)
Previously we set the dump direction according to command line
options, but we may override the scheduling direction in `initPolicy`
and this results in mismatch between dump and actual policy.
Here we simply set the dump direction after initializing the policy.
Commit: 50e73aeea2a7e2cbaeb66252aadea9a6144937df
https://github.com/llvm/llvm-project/commit/50e73aeea2a7e2cbaeb66252aadea9a6144937df
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/target-loop-unparse.f90
A flang/test/Semantics/OpenMP/loop-bind.f90
M flang/test/Semantics/OpenMP/nested-distribute.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Parse `bind` clause for `loop` direcitve. (#113662)
Adds parsing for the `bind` clause. The clause was already part of the
`loop` direcitve's definition but parsing was still missing.
Commit: bfa3ffb1e2d7c976c4db10dbdd8f5d09976c63be
https://github.com/llvm/llvm-project/commit/bfa3ffb1e2d7c976c4db10dbdd8f5d09976c63be
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
Log Message:
-----------
[FIX] Add missing component introduced in #115218
That causes link error:
```
ld.lld: error: undefined symbol: llvm::memprof::IndexedMemProfRecord::getGUID(llvm::StringRef)
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced 1 more times
```
Commit: 594e11ce4247feb3197dc3cf0da331e96f9a098b
https://github.com/llvm/llvm-project/commit/594e11ce4247feb3197dc3cf0da331e96f9a098b
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Avoid incorrect ICP symtab canonicalization (#115419)
ICP builds a symtab from the symbols in the module allowing mapping from
the VP metadata GUIDs to the Function. MemProf uses this same symtab
handling for its ICP during cloning. When symbols are added to the
symtab, the handling adds both a GUID computed from the function name,
or from the attached PGOFuncName metadata for locals, as well as a GUID
computed from the "canonicalized" name, which strips all "." suffixes
other than ".__uniq". This was originally meant to remove the ".llvm.*"
suffix added to promoted locals (done earlier in the ThinLTO backend).
In theory, it should no longer be needed as locals should have
PGOFuncName metadata.
However, this was causing a linker unsat, in code that used coroutines.
For an original coroutine function, there were several additional
functions created that had the same name, but different "." suffixes.
Therefore the canonical name for these additional functions had the same
GUID as that of the original function, leading to extra entries in the
symtab, and to selecting the wrong function for promotion. For regular
ICP this can happen, but is just a performance issue. However, for
memprof the promoted direct call calls a memprof clone, and because we
called the wrong function, in this case it didn't have a memprof clone
and we got a linker unsat.
We may be able to remove the canonical name handling for ICP in general,
but for now disable it for MemProf. At worst this could lead to not
finding a GUID in the symtab and not performing an ICP, so should be
conservatively correct.
Commit: ae509a085836079585228aede8a5017ad80e1aa9
https://github.com/llvm/llvm-project/commit/ae509a085836079585228aede8a5017ad80e1aa9
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
Log Message:
-----------
[RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (#115269)
Commit: 694719a4801179198489d8dc492341b0ef0e59fa
https://github.com/llvm/llvm-project/commit/694719a4801179198489d8dc492341b0ef0e59fa
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
Log Message:
-----------
[RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. (#115391)
Commit: b613a54075c6e704dcaa15a676bf732955eb4352
https://github.com/llvm/llvm-project/commit/b613a54075c6e704dcaa15a676bf732955eb4352
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Utils/FoldUtils.cpp
Log Message:
-----------
[mlir][IR][NFC] Cleanup insertion point API usage (#115415)
Use `setInsertionPointToStart` / `setInsertionPointToEnd` when possible.
Commit: 3ad640357744890a20494a4943d9a8a94c5b3776
https://github.com/llvm/llvm-project/commit/3ad640357744890a20494a4943d9a8a94c5b3776
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ShadowCallStack.rst
M clang/include/clang/Driver/Options.td
M clang/test/Driver/riscv-features.c
Log Message:
-----------
[Clang][RISCV] Remove forced-sw-shadow-stack (#115355)
This option was used to override the behavior of
`-fsanitize=shadowcallstack` on RISC-V backend, which by default use a
hardware implementation if possible, to use the software implementation
instead. After #112477 and #112478, now two implementation
is represented by independent options and we no longer need it.
Commit: 2f40e3e713efb550c05ff5f911ab4ce2e4a8dddf
https://github.com/llvm/llvm-project/commit/2f40e3e713efb550c05ff5f911ab4ce2e4a8dddf
Author: Janis Heims <janis.heims at undertheprinter.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kSubtarget.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
A llvm/test/CodeGen/M68k/CodeModel/large-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/large-static.ll
Log Message:
-----------
[M68k] implement large code model (#106381)
Fixes #106208.
Commit: 37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
https://github.com/llvm/llvm-project/commit/37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
[Clang] Remove the wrong assumption when rebuilding SizeOfPackExprs for constraint normalization (#115120)
In 463a4f150, we assumed that all the template argument packs are of
size 1 when normalizing a constraint expression because I mistakenly
thought those packs were obtained from their injected template
parameters. This was wrong because we might be checking constraints when
instantiating a friend declaration within a class template
specialization, where the parent class template is specialized with
non-dependent template arguments.
In that sense, we shouldn't assume any pack size nor expand anything in
such a scenario. Moreover, there are no intermediate (substituted but
unexpanded) AST nodes for template template parameters, so we have to
special-case their transformations by looking into the instantiation
scope instead of extracting anything from template arguments.
Fixes #115098
Commit: c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
https://github.com/llvm/llvm-project/commit/c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
Log Message:
-----------
[Coroutines] Inline the `.noalloc` ramp function marked coro_safe_elide (#114004)
Commit: d233fedfb0de882353c348cd1ac57dab619efa6d
https://github.com/llvm/llvm-project/commit/d233fedfb0de882353c348cd1ac57dab619efa6d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
Log Message:
-----------
[Coroutines] Respect noinline attributes when eliding heap allocation (#115384)
Commit: 9061e6e58a78046963f0eb5991e98346e01a0bf7
https://github.com/llvm/llvm-project/commit/9061e6e58a78046963f0eb5991e98346e01a0bf7
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
Log Message:
-----------
[GlobalISel][AArch64] Legalize G_EXTRACT_VECTOR_ELT for SVE (#115161)
AArch64InstrGISel.td defines:
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
There are many patterns for SVE. Let's exploit that fact.
Commit: c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
https://github.com/llvm/llvm-project/commit/c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
Author: T-Tie <t_tttie at 163.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)
Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
Commit: 1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
https://github.com/llvm/llvm-project/commit/1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
Author: Sebastian Kreutzer <SebastianKreutzer at gmx.net>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M clang/test/Driver/XRay/xray-shared.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
Log Message:
-----------
Reapply "[XRay][AArch64] Support -fxray-shared (#114431)" (#115300)
This patch implements support for `-fxray-shared` on AArch64 and fixes a
remaining issue in the previous PR #114431.
A bug in the XRay `CMakeLists.txt` caused the XRay assembly sources to
be built for every architecture in `XRAY_DSO_SUPPORTED_ARCH` on Apple.
This led to the compiler trying to compile AArch64 assembly for X86
targets and vice versa.
This is addressed here by ensuring that assembly sources are only built
for the matching architecture (see fixup commit).
**Original PR description:**
This patch adds support for `-fxray-shared` on AArch64. This feature,
introduced in #113548 for x86_64, enables the instrumentation of shared
libraries with XRay.
Changes:
- Adds AArch64 to the list of targets supporting `-fxray-shared`
- Introduces PIC versions of the AArch64 XRay trampolines
- Adjusts relevant XRay tests
Commit: a25d91a164b0a283dd809cf9b4d9442d24173fb7
https://github.com/llvm/llvm-project/commit/a25d91a164b0a283dd809cf9b4d9442d24173fb7
Author: Gergely Futo <gergely.futo at hightec-rt.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
Log Message:
-----------
[RISCV] Skip DAG combine for bitcast fabs/fneg (#115325)
Disable the DAG combine for bitcast fabs/fneg in case of the zdinx
extension.
The combine folds the fabs/fneg nodes in some cases. This might result
in suboptimal code if compiled with the zdinx extension. In case of the
zdinx extension, there is no need to load the double value from an x
register to an f register, so the combine can be skipped.
Commit: 984bca9d1faaa1fa5c694f8f2a5524b2374d204a
https://github.com/llvm/llvm-project/commit/984bca9d1faaa1fa5c694f8f2a5524b2374d204a
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
Log Message:
-----------
[GVN][NewGVN] Take call attributes into account in expressions (#114545)
Drop `canBeReplacedBy` and take call attributes into account in
expressions.
Address comment
https://github.com/llvm/llvm-project/pull/114011#pullrequestreview-2409772313.
Commit: f02b1cc99e12ac0147d5c334f130a305d85e477a
https://github.com/llvm/llvm-project/commit/f02b1cc99e12ac0147d5c334f130a305d85e477a
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
Log Message:
-----------
[ASTWriter] Detect more non-affecting FileIDs to reduce source location duplication (#112015)
Currently, any FileID that references a module map file that was
required for a compilation is considered as affecting. This misses an
important opportunity to reduce the source location space taken by the
resulting PCM.
In particular, consider the situation where the same module map file is
passed multiple times in the dependency chain:
```shell
$ clang -fmodule-map-file=foo.modulemap ... -o mod1.pcm
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod1.pcm ... -o mod2.pcm
...
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod$((N-1)).pcm ... -o mod$N.pcm
```
Because `foo.modulemap` is read before reading any of the `.pcm` files,
we have to create a unique `FileID` for it when creating each module.
However, when reading the `.pcm` files, we will reuse the `FileID`
loaded from it for the same module map file and the `FileID` we created
can never be used again, but we will still mark it as affecting and it
will take the source location space in the output PCM.
For a chain of N dependencies, this results in the file taking `N *
(size of file)` source location space, which could be significant. For
examples, we observer internally that some targets that run out of 2GB
of source location space end up wasting up to 20% of that space in
module maps as described above.
I take extra care to still write the InputFile entries for those files that occupied
source location space before. It is required for correctness of clang-scan-deps.
Commit: d6d73ec89e493c69cf24dc3a710d861e2ce08acb
https://github.com/llvm/llvm-project/commit/d6d73ec89e493c69cf24dc3a710d861e2ce08acb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable vector.flat_transpose for scalable vectors (#115338)
Disables `vector.flat_transpose` for scalable vectors. As per the docs:
> This is the counterpart of llvm.matrix.transpose in MLIR
I'm not aware of any use of any matrix-multiply intrinsics in the
context of scalable vectors, hence disabling.
Note, this is a follow-on for #102573 in which I disabled
`vector.matrix_multiply`.
Commit: ff07df6620c32571c7e13ff96ec7976c63ed0ab8
https://github.com/llvm/llvm-project/commit/ff07df6620c32571c7e13ff96ec7976c63ed0ab8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
Log Message:
-----------
[InstCombine] Drop nsw in negation of select (#112893)
Closes https://github.com/llvm/llvm-project/issues/112666 and
https://github.com/llvm/llvm-project/issues/114181.
Commit: b9dd60228cbb2a173380a450f0f71ca43e917783
https://github.com/llvm/llvm-project/commit/b9dd60228cbb2a173380a450f0f71ca43e917783
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/sve-hadd.ll
Log Message:
-----------
[DAGCombiner] Remove a hasOneUse check in visitAND (#115142)
For some reason there was a hasOneUse check on the splat for the
second operand and it's not obvious to me why. The check blocks
optimisations for lowering of nodes like AVGFLOORU and AVGCEILU.
In a follow-on patch I also plan to improve the generated code
for AVGCEILU further by teaching computeKnownBits about
zero-extending masked loads.
Commit: 58a17e1bbc54357385d0b89cfc5635e402c31ef6
https://github.com/llvm/llvm-project/commit/58a17e1bbc54357385d0b89cfc5635e402c31ef6
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-AVX512 (#114070)
Commit: 4f3bf1c62ceb85d2e33857ada26b565822e65600
https://github.com/llvm/llvm-project/commit/4f3bf1c62ceb85d2e33857ada26b565822e65600
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 58a17e1bbc54
Commit: d74127e78aa7f8ab07b0926d25920444dde6c73c
https://github.com/llvm/llvm-project/commit/d74127e78aa7f8ab07b0926d25920444dde6c73c
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[flang][OpenMP][MLIR] Add MLIR op for loop directive (#113911)
Adds MLIR op that corresponds to the `loop` directive.
Commit: 546066e4f74d50c974248b0ed247f65ebf24b75c
https://github.com/llvm/llvm-project/commit/546066e4f74d50c974248b0ed247f65ebf24b75c
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/DIBuilder.cpp
Log Message:
-----------
Fix DIBuilder::createVariantPart after f6617d65e496
which ended up passing 0 for the Discriminator arg, Discriminator for
the DataLocation arg, etc.
The DICompositeType::get's new NumExtraInhabitants parameter is at the
end, and has a default value, so no change in the caller is necessary.
See comment on https://github.com/llvm/llvm-project/pull/112590
Commit: ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
https://github.com/llvm/llvm-project/commit/ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/PDB.cpp
A lld/test/COFF/arm64ec-pdb.test
Log Message:
-----------
[LLD][COFF] Use correct machine types in PDB records on ARM64EC (#115309)
Commit: 799e520c51f47c54769e5bd8ce6ce2d2d3931445
https://github.com/llvm/llvm-project/commit/799e520c51f47c54769e5bd8ce6ce2d2d3931445
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/attr-target-clones-aarch64.c
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/lib/Target/AArch64/AArch64FMV.td
Log Message:
-----------
[FMV] Remove feature dgh. (#115363)
It belongs to the HINT space so it can be executed as NOP if the
hardware doesn't support it.
Reviewed in ACLE -> https://github.com/ARM-software/acle/pull/357
Commit: 4bcd4d843f660c1a435159a2964f0c4cf4564ab1
https://github.com/llvm/llvm-project/commit/4bcd4d843f660c1a435159a2964f0c4cf4564ab1
Author: Weaver <Tom.Weaver at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
Log Message:
-----------
Revert "clang/AMDGPU: Restore O3 checks in default-attributes.hip (#115238)"
This reverts commit 889d67785905ea85cdb17b2bf2b4b6f010b641f5.
Caused the following build bot failures, author has failed to address:
https://lab.llvm.org/buildbot/#/builders/144/builds/11132
https://lab.llvm.org/buildbot/#/builders/46/builds/7541
https://lab.llvm.org/buildbot/#/builders/190/builds/9077
Please fix before recommitting.
Commit: 2c49301d91d743c4424997c5f670a453439b4b86
https://github.com/llvm/llvm-project/commit/2c49301d91d743c4424997c5f670a453439b4b86
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
Log Message:
-----------
[IR] Remove variadic overload of StructType::setBody. NFC. (#114421)
This is unused in-tree.
Commit: 31af00fda73df8e85e30c71f66e096d486ec8c8b
https://github.com/llvm/llvm-project/commit/31af00fda73df8e85e30c71f66e096d486ec8c8b
Author: amilendra <amilendra.kodithuwakku at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/test/MC/AArch64/spe.s
Log Message:
-----------
[AArch64][v8.7-A] Fix inconsistency in SPE_EEF feature (#115296)
The `SPE-EEF` system-register only feature introduced in Armv8.7-a adds
support for an extra system register (`PMSNEVFR_EL1`) to the Statistical
Profiling extension.
However, `SPE-EEF` is gated even for Armv8.7-a and the `spe-eef`
subtarget-feature is needed to enable it.
This behavior is inconsistent with the implementation for other
system-register only features as they can be used ungated under
supported architectures.
(e.g. HCX : Enable Armv8.7-A `HCRX_EL2` system register).
GCC/Binutils too do not add command line flags for features that only
enable system registers.
Fix by enabling `SPE-EEF` unconditionally under v8.7-A and above.
Commit: 0a7e5e34569737447e9e3e08b5f87883300061e5
https://github.com/llvm/llvm-project/commit/0a7e5e34569737447e9e3e08b5f87883300061e5
Author: Alona Enraght-Moony <code at alona.page>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/docs/UserDocumentation.rst
Log Message:
-----------
[libc++][docs] Document _LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION (#115405)
This was added in 681cde7dd8b5613dbafc9ca54e0288477f946be3, but isn't
currently documented.
Commit: df3f18b071d853896318d2d37186fc6289ffdb2b
https://github.com/llvm/llvm-project/commit/df3f18b071d853896318d2d37186fc6289ffdb2b
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of Windows host (#115337)
Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of
Windows host.
Commit: 39bce77bd6cdb334810ed95249683484e44c1165
https://github.com/llvm/llvm-project/commit/39bce77bd6cdb334810ed95249683484e44c1165
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: XFAIL on Darwin for older compiler verions
Follow-up to https://github.com/llvm/llvm-project/pull/111859. Prior
to this PR we would never run these tests with DWARFv5 on older Clang
versions (since default wasn't DWARFv5 on macOS until recently). The
patch explicitly started running some of these tests with DWARFv5.
These were failing on the macOS matrix bot (with Clang-15/Clang-17).
```
======================================================================
FAIL: test_inline_static_members_dwarf5_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 150, in test_inline_static_members_dwarf5
self.check_inline_static_members("-gdwarf-5")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
```
Commit: 34bf9dd6d39cb2bf75731cea7a26c3563720cb67
https://github.com/llvm/llvm-project/commit/34bf9dd6d39cb2bf75731cea7a26c3563720cb67
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: fix XFAIL decorators
The `compiler` parameter is not supported in the `expectedFailureDarwin`
decorator.
Change the decorator to `expectedFailureAll`, which is fine because
this only affects the `dsym` variant (which is only a macOS variant).
Commit: 3797daa5448f3471c0d7d1c67838922a83a06fa1
https://github.com/llvm/llvm-project/commit/3797daa5448f3471c0d7d1c67838922a83a06fa1
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
Log Message:
-----------
[AArch64] Create set.fpmr intrinsic and assembly lowering (#114248)
This patch introduces new llvm.set.fpmr intrinsics for setting value in
FPMR register and adds its lowering to series of read-compare-write
instructions. This intrinsic will be generated during lowering of FP8 C
intrinsics into LLVM-IR introduced in later patch.
***This is an experimental implementation of handling fp8 intriniscs and
is likely to change in the future.***
Commit: 6e4cd463e580046feb66597a61db352c63fd783b
https://github.com/llvm/llvm-project/commit/6e4cd463e580046feb66597a61db352c63fd783b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
Log Message:
-----------
[lldb] s/assertEquals/assertEqual TestDAP_sendEvent
New unittest versions don't have the "s" version.
Commit: e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
https://github.com/llvm/llvm-project/commit/e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Remove forced-sw-shadow-stack in RISCVFeatures.td (#115447)
This patch removes forced-sw-shadow-stack related statements in
RISCVFeatures.td, which was missed in the last patch
https://github.com/llvm/llvm-project/pull/115355
Commit: 0daca808ce111f21db8c0ee9ea5d2509d6034557
https://github.com/llvm/llvm-project/commit/0daca808ce111f21db8c0ee9ea5d2509d6034557
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/C/C2y/n3344.c
Log Message:
-----------
Fix issues with WG14 N3344 changes
This amends 24e2e259a06d9aa67dc278ac24dcb98da9dd63f6 with a fix for
'register void *', which is still okay as a function parameter.
Commit: 724b432410fd59c63cc313d41824eda5ec84052f
https://github.com/llvm/llvm-project/commit/724b432410fd59c63cc313d41824eda5ec84052f
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/stdalign.h
Log Message:
-----------
[z/OS] Make sure __alignas_is_defined and __alignof_is_defined are defined on z/OS. (#115368)
Commit: afa178d36017ab565c33a8639be16355a054b95b
https://github.com/llvm/llvm-project/commit/afa178d36017ab565c33a8639be16355a054b95b
Author: lfrenot <leon.frenot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
Log Message:
-----------
[mlir][LLVM] Add exact flag (#115327)
The implementation is mostly based on the one existing for the nsw and
nuw flags.
If the exact flag is present, the corresponding operation returns a
poison value when the result is not exact. (For a division, if rounding
happens; for a right shift, if a non-zero bit is shifted out.)
Commit: 5fbe9b958dc3035480406c2cd4524e4827d2dfaf
https://github.com/llvm/llvm-project/commit/5fbe9b958dc3035480406c2cd4524e4827d2dfaf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/cfguard-off-instrumented.s
Log Message:
-----------
[LLD][COFF] Set __guard_flags to CF_INSTRUMENTED if any object is instrumented (#115374)
Commit: 0e39b1348e5fcadb129a6f113e5d708a526d8faa
https://github.com/llvm/llvm-project/commit/0e39b1348e5fcadb129a6f113e5d708a526d8faa
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/test/CMakeLists.txt
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
[mlir] Remove the mlir-spirv-cpu-runner (move to mlir-cpu-runner) (#114563)
This commit builds on and completes the work done in
9f6c632ecda08bfff76b798c46d5d7cfde57b5e9 to eliminate the need for a
separate mlir-spirv-cpu-runner binary. Since the MLIR processing is
already done outside this runner, the only real difference between it
and the mlir-cpu-runner is the final linking step between the nested
LLVM IR modules. By moving this step into mlir-cpu-runner behind a new
command-line flag (`--link-nested-modules`), this commit is able to
completely remove the runner component of the mlir-spirv-cpu-runner.
The runtime libraries and the tests are moved and renamed to fit into
the Execution Engine and Integration tests, following the model of the
similar migration done for the CUDA Runner in D97463.
Commit: 231e03ba7e82896847dbc27d457dbb208f04699c
https://github.com/llvm/llvm-project/commit/231e03ba7e82896847dbc27d457dbb208f04699c
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[AArch64] Add select-opt test with select transformed to cast.
Add tests with add and sub binops with zext i1 operands.
Commit: e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
https://github.com/llvm/llvm-project/commit/e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
A clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros (#112849)
So far, these macros can be used in contexts where no meaningful
wavefront size is available. We therefore deprecate these macros, to
replace them with a more resilient interface to access wavefront size
information where it is available.
For SWDEV-491529.
Commit: 32c744ae339dc356060636bcdf75a5e2a67fca00
https://github.com/llvm/llvm-project/commit/32c744ae339dc356060636bcdf75a5e2a67fca00
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator (#115480)
It is broken after #115337
https://lab.llvm.org/buildbot/#/builders/195/builds/794
Commit: b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
https://github.com/llvm/llvm-project/commit/b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ast-print-openacc-loop-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
Log Message:
-----------
[OpenACC] Implement `loop` restrictions on `for` loops. (#115370)
OpenACC restricts the contents of a 'for' loop affected by a 'loop'
construct without a 'seq'. The loop variable must be integer, pointer,
or random-access-iterator, it must monotonically increase/decrease, and
the trip count must be computable at runtime before the function.
This patch tries to implement some of these limitations to the best of
our ability, though it causes us to be perhaps overly restrictive at the
moment. I expect we'll revisit some of these rules/add additional
supported forms of loop-variable and 'monotonically increasing' here,
but the currently enforced rules are heavily inspired by the OMP
implementation here.
Commit: 844fe8f662de6d1a51f4a04b37fadb96b2009bd0
https://github.com/llvm/llvm-project/commit/844fe8f662de6d1a51f4a04b37fadb96b2009bd0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][nfc] Rename @genbool_* as @constant_mask_* (#115335)
Renames `@genbool_*` tests as `@constant_mask_*`. That's to better
highlight which Op is tested and for better consistency with other test.
In addition,`@genbool_2d` is moved _above_ it's counterparts with
scalable vectors (again, for consistency).
Commit: d5677b630d0faf38e2e92797415ff80676f86063
https://github.com/llvm/llvm-project/commit/d5677b630d0faf38e2e92797415ff80676f86063
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/commands/target/basic/TestTargetCommand.py
Log Message:
-----------
[lldb] Fixed TestTargetCommand.py in case of Windows host and Linux target (#115470)
Fixed TestTargetCommand.py in case of Windows host and Linux target.
Commit: 107af4a62ee9afb4be2cba1bc7c12afb677445ef
https://github.com/llvm/llvm-project/commit/107af4a62ee9afb4be2cba1bc7c12afb677445ef
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Introduce struct PredInfo. NFC. (#115457)
This just provides a neater encapsulation of the info about the
predicate for an edge, rather than ValueWeightPair aka std::pair.
Commit: 644a9a4327af4fb4f7b09832cafe3c82843231b5
https://github.com/llvm/llvm-project/commit/644a9a4327af4fb4f7b09832cafe3c82843231b5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
Log Message:
-----------
[CodeExtractor][NFC] Refactor-out applyFirstDebugLoc. (#115358)
Split-off from #114419
Commit: ab9178e3e73dc715463e1019ed2cd449dc18bb18
https://github.com/llvm/llvm-project/commit/ab9178e3e73dc715463e1019ed2cd449dc18bb18
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
Log Message:
-----------
[ARM] Add a couple of new MVE reduction tests. NFC
Nowadays we generate add(zext(mul(sext, sext)) with nneg zext and the multi-use
test is awkward to get right. This should help our test coverage with the vplan
cost transition.
Commit: 3c3f19ca5ea03428edacbd5d087b991c447c47dc
https://github.com/llvm/llvm-project/commit/3c3f19ca5ea03428edacbd5d087b991c447c47dc
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/Intrinsics.cpp
Log Message:
-----------
Revert "[NFC][LLVM] Use namespace `Intrinsic` in `Intrinsics.cpp` (#114822)"
This reverts commit c2b61fcb3cd4ffa286b24437b7b6d66f0dee6c25.
Intrinsic namespace contains memcpy which is a naming conflict with
memcpy from string.h header.
Commit: 53e6f627d7e81633b2e159675884bfcce11bdc00
https://github.com/llvm/llvm-project/commit/53e6f627d7e81633b2e159675884bfcce11bdc00
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] _mm_movpi64_epi64 - convert to shufflevector pattern instead of bitcasting to i64
Don't bitcast a v1i64 to i64 as constant expressions will struggle to handle this - convert to a shufflevector concat pattern like _mm_move_epi64 instead
Commit: 0f040433d325aa68ec6840aa179f3f314c26153a
https://github.com/llvm/llvm-project/commit/0f040433d325aa68ec6840aa179f3f314c26153a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Update MMX intrinsic tests for both C/C++
Requires update to movmsk call to handle additional markers
Commit: 77bec78878762e34150fe23734fa43df796c873c
https://github.com/llvm/llvm-project/commit/77bec78878762e34150fe23734fa43df796c873c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Do not look for last instruction in schedule block for buildvectors
If looking for the insertion point for the node and the node is
a buildvector node, the compiler should not use scheduling info for such
nodes, they may contain only partial info, which is not fully correct
and may cause compiler crash.
Fixes #114082
Commit: f7bb12901e2955b972273a06dd028ab4b2822b44
https://github.com/llvm/llvm-project/commit/f7bb12901e2955b972273a06dd028ab4b2822b44
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Add tanpif16 function (#115183)
- Implementation of `tan` for 16-bit floating point inputs scaled by pi.
i.e,. `tanpif16()`
- Implementation of Tanpi in MPFRWrapper for MPFR versions < 4.2
- Exhaustive tests for `tanpif16()`
Commit: 1645d99bc9c16b1f9e2f08e36d67054498d8751e
https://github.com/llvm/llvm-project/commit/1645d99bc9c16b1f9e2f08e36d67054498d8751e
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
Log Message:
-----------
[libc++][hardening] Use `static_assert` for `__(static_)bounded_iter` (#115304)
We can't `static_assert` `__libcpp_is_contiguous_iterator` for
`__wrap_iter` currently because `__wrap_iter` is also used for wrapping
user-defined fancy pointers.
Fixes #115002.
Commit: 9aea6671085f02e6127750103ca48ae6a09ceeb8
https://github.com/llvm/llvm-project/commit/9aea6671085f02e6127750103ca48ae6a09ceeb8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Log Message:
-----------
[symbolizer] Change the ErrorHandler from llvm::function_ref to std::function. (#115477)
This fixes dangling `ErrorHandler` references
([here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp#L48-L53)
is an example).
`llvm::function_ref` doesn't own the callable, and it is not safe to
store a function_ref (the `PlainPrinterBase` stores a
`llvm::function_ref` which can easily lead to dangling references).
Commit: 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
https://github.com/llvm/llvm-project/commit/8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-lifetimebound.c
Log Message:
-----------
[clang] Permit lifetimebound in all language modes (#115482)
Lifetimebound annotations can help diagnose common cases of dangling
including escaping the address of a stack variable from a function. This
is useful in all C family languages, restricting these diagnostics to
C++ is an artificial limitation.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: da9499ebfb323602c42aeb674571fe89cec20ca6
https://github.com/llvm/llvm-project/commit/da9499ebfb323602c42aeb674571fe89cec20ca6
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293)
This patch introduces the amended feature flag for
[FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES),
'**sve-aes**'. The existing flag associated with this feature,
'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for
backwards compatibility.
The
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension)
documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1
when
> there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions
and if the associated ACLE intrinsics are available.
The front-end has been amended such that it is compatible with +sve2-aes
and +sve2+sve-aes.
Commit: 7844257fc2afe490ae4b923a770d20dabed5c3c6
https://github.com/llvm/llvm-project/commit/7844257fc2afe490ae4b923a770d20dabed5c3c6
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Use explicit #include instead of transitive #include (#115420)
This benchmark test currently uses `std::unique_ptr` without explicitly
`#include <memory>`. I think we should not rely on transitive inclusion.
Commit: c93eb43a63d3b5c90e828608b5c2063644a3b161
https://github.com/llvm/llvm-project/commit/c93eb43a63d3b5c90e828608b5c2063644a3b161
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lua_api/TestFileHandle.lua
Log Message:
-----------
[lldb] Fix TestFileHandle.lua
- Explicitly create an `SBFile`.
- Add missing call to `close`.
- Use `SetErrorFile` in TestLegacyFileErr.
Commit: e734de1f5a3c2ec0c88221eb0991b0922e30d902
https://github.com/llvm/llvm-project/commit/e734de1f5a3c2ec0c88221eb0991b0922e30d902
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
Revert "[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros" (#115499)
Reverts llvm/llvm-project#112849 due to test failure on Mac, reported by
@nico
Commit: 6737ba40406030cd8a7ea706cd56302f8be7a4b4
https://github.com/llvm/llvm-project/commit/6737ba40406030cd8a7ea706cd56302f8be7a4b4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Update the lifetimebound doc.
The lifetimebound attr is not C++ only anymore after 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Commit: c9552283c0bf277eba490cde9fd913510f4111c0
https://github.com/llvm/llvm-project/commit/c9552283c0bf277eba490cde9fd913510f4111c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for MMX _mm_set*_pi* intrinsics
Commit: 2407ff4645e9124507a4b5d910603ff7fc9e5734
https://github.com/llvm/llvm-project/commit/2407ff4645e9124507a4b5d910603ff7fc9e5734
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_movpi64_epi64
Commit: 51e8f822f39174eaf83b1d5798de329518970b02
https://github.com/llvm/llvm-project/commit/51e8f822f39174eaf83b1d5798de329518970b02
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr62014.ll
Log Message:
-----------
[X86] pr62014.ll - regenerate test checks with vpternlog comments
Commit: 71f82bba35c48eaf98c50aeeb4d2675156681c02
https://github.com/llvm/llvm-project/commit/71f82bba35c48eaf98c50aeeb4d2675156681c02
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
Log Message:
-----------
[SPIRV] Use heterogenous lookups with std::map (NFC) (#115425)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 6ce44266fc2d06dfcbefd8146279473ccada52ca
https://github.com/llvm/llvm-project/commit/6ce44266fc2d06dfcbefd8146279473ccada52ca
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/lib/IR/Dialect.cpp
Log Message:
-----------
[mlir] Use heterogenous lookups with std::map (NFC) (#115426)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: a4819d6aa30f849770c258abba67a4b721642ebf
https://github.com/llvm/llvm-project/commit/a4819d6aa30f849770c258abba67a4b721642ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/IR/MLIRContext.cpp
Log Message:
-----------
[mlir] Simplify code with StringMap::operator[] (NFC) (#115427)
Commit: bc7e5c2016e287b768d2a3a1de15f6bb644622ae
https://github.com/llvm/llvm-project/commit/bc7e5c2016e287b768d2a3a1de15f6bb644622ae
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Avoid repeated hash lookups (NFC) (#115428)
Commit: 2f243a5fb754c3688dfa225ce8073a281bca1a24
https://github.com/llvm/llvm-project/commit/2f243a5fb754c3688dfa225ce8073a281bca1a24
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for 0e39b1348e5fcadb129a6f113e5d708a526d8faa
Commit: 3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
https://github.com/llvm/llvm-project/commit/3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
Log Message:
-----------
[llvm-reduce] Reduce samesign flag from icmp (#115492)
Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Log Message:
-----------
[AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)
We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
`fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
`fma extract(Rn, 0), Rm, Ra -> fmadd`
The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
`fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
`fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`
Commit: 4027400d2ceefb5ce68d4508e5f30dc40c4f535b
https://github.com/llvm/llvm-project/commit/4027400d2ceefb5ce68d4508e5f30dc40c4f535b
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
A clang/test/C/C2y/n3342.c
M clang/test/Misc/warning-flags.c
M clang/test/Sema/declspec.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3342 (#115494)
This paper made qualified function types implementation-defined. We have
always supported this as an extension, so now we're documenting our
behavior.
Note, we still warn about this by default even in C2y mode because a
qualified function type is a sign of programmer confusion.
Commit: f756d38abf2ec40ee06ee5aa668db444e5d6f485
https://github.com/llvm/llvm-project/commit/f756d38abf2ec40ee06ee5aa668db444e5d6f485
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3342.c
Log Message:
-----------
Fix failing test bot
Fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11191
Commit: e5e15f9128b69f77668465b715b7984b8d5ad75a
https://github.com/llvm/llvm-project/commit/e5e15f9128b69f77668465b715b7984b8d5ad75a
Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
add QuietMisdreavus to Clang/ExtractAPI code owners (#115206)
Adding myself to the ExtractAPI code owners listing so i can participate
in code reviews.
Commit: 19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
https://github.com/llvm/llvm-project/commit/19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/vector-sext.ll
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use broadcast on AVX2+ targets
Make use of AVX2 broadcasts to splat the source integer across all lanes to simplify the per-lane byte shuffles.
Prep work to avoid a regression in the fix for #66150
Commit: 79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
https://github.com/llvm/llvm-project/commit/79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use SelectionDAG::getSplat helper instead of shuffle(scalar_to_vector(x))
Commit: 92e0fb0c944254312d7b9c6ca64a026643617f60
https://github.com/llvm/llvm-project/commit/92e0fb0c944254312d7b9c6ca64a026643617f60
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
Log Message:
-----------
[DebugInfo][LoopUnroll] Preserve DebugLocs on optimized cond branches (#114225)
This patch fixes a simple error where as part of loop unrolling we
optimize conditional loop-exiting branches into unconditional branches
when we know that they will or won't exit the loop, but does not
propagate the source location of the original branch to the new one.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
Log Message:
-----------
[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)
Fixes 2 old TODOs
Commit: b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
https://github.com/llvm/llvm-project/commit/b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Remove one SSAUpdater::AddAvailableValue. NFCI. (#115472)
Commit: 39358f846d1e336def88ff9c25581fab392d59fe
https://github.com/llvm/llvm-project/commit/39358f846d1e336def88ff9c25581fab392d59fe
Author: stefankoncarevic <skoncare at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/named-ops.mlir
Log Message:
-----------
[mlir][linalg] Add Grouped Convolution Ops: conv_2d_nhwgc_gfhwc and conv_2d_nhwgc_gfhwc_q (#108192)
This patch adds two new ops: linalg::Conv2DNhwgcGfhwcOp and
linalg::Conv2DNhwgcGfhwcQOp, and uses them to convert tosa group conv2d
Ops.
- Added linalg::Conv2DNhwgcGfhwcOp and linalg::Conv2DNhwgcGfhwcQOp.
- Updated the conversion process to use these new ops for tosa group
conv2d operations.
Commit: c3c2f46f7bd5891af13fef56a8754007f11ff6c1
https://github.com/llvm/llvm-project/commit/c3c2f46f7bd5891af13fef56a8754007f11ff6c1
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/test/C/C2y/n3346.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Claim conformance and add test coverage for WG14 N3346 (#115516)
This converts some undefined behaviors during initialization to instead
be constraint violations. Clang has always implemented these as
constraints, so no compiler changes were needed.
Commit: f7eba08497a2a46f2c10737a110f6b778faf1615
https://github.com/llvm/llvm-project/commit/f7eba08497a2a46f2c10737a110f6b778faf1615
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ObjectYAML/ELFEmitter.cpp
Log Message:
-----------
[ObjectYAML][ELF] Fix misspelling in `Elf_Verdaux` var name (NFC)
Commit: 60972a893e2bf915f6ff043c9396dea9619456fb
https://github.com/llvm/llvm-project/commit/60972a893e2bf915f6ff043c9396dea9619456fb
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/obj2yaml/elf2yaml.cpp
Log Message:
-----------
[ObjectYAML][ELF] Allow verdaux entry offset to be user-defined
Commit: b85e5b49d3efc37e837757a5154884648dc57113
https://github.com/llvm/llvm-project/commit/b85e5b49d3efc37e837757a5154884648dc57113
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Speculatively fix test bots
This should address the issues found by:
https://lab.llvm.org/buildbot/#/builders/12/builds/9226
https://lab.llvm.org/buildbot/#/builders/140/builds/10487
https://lab.llvm.org/buildbot/#/builders/27/builds/1752
Commit: d30a6dcfa06196dd98fc898219eb12bab04a56de
https://github.com/llvm/llvm-project/commit/d30a6dcfa06196dd98fc898219eb12bab04a56de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
Log Message:
-----------
[AMDGPU] Reorganize tests to unblock #112403 (#115503)
We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the `[15 x i32]` arguments to
`[13 x i32]` to bypass the issue.
Commit: e215a1e27d84adad2635a52393621eb4fa439dc9
https://github.com/llvm/llvm-project/commit/e215a1e27d84adad2635a52393621eb4fa439dc9
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
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M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
Commit: 4661467003e7bc7f9bb89ab581517617d2a36c62
https://github.com/llvm/llvm-project/commit/4661467003e7bc7f9bb89ab581517617d2a36c62
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
A clang/test/C/C2y/n3341.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3341 (#115478)
This paper made empty structures and unions implementation-defined. We
have always supported this as a GNU extension, so now we're documenting
our behavior and removing the extension warning in C2y mode.
Commit: b70d1302cf2edaf95817a90f161691c684945273
https://github.com/llvm/llvm-project/commit/b70d1302cf2edaf95817a90f161691c684945273
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Another speculative fix for WG14 N3346
This time it's for builders that don't default to C11 or later, such as:
https://lab.llvm.org/buildbot/#/builders/144/builds/11201
Commit: 2808f05e83643b3d5ef128340f6f4da994ed71e3
https://github.com/llvm/llvm-project/commit/2808f05e83643b3d5ef128340f6f4da994ed71e3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3341.c
Log Message:
-----------
Update test case for bots which don't default to C17
Commit: 17f3e00911b860d535f41185e605c47babcc2039
https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
The increase in fallbacks that was previously reported were not caused
by this change.
Original description:
This matches InstCombine and DAGCombine.
RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.
Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
Commit: e4d57d6a729fd955ccbdd8834065356f26284f3d
https://github.com/llvm/llvm-project/commit/e4d57d6a729fd955ccbdd8834065356f26284f3d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
Log Message:
-----------
[OpenACC] Remove 'loop' link to parent construct
After implementing 'loop', we determined that the link to its parent
only ever uses the type, not the construct itself. This patch removes
it, as it is both a waste and causes problems with serialization.
Commit: e53c46a9084caac115d7f694e5f16f904b0d7124
https://github.com/llvm/llvm-project/commit/e53c46a9084caac115d7f694e5f16f904b0d7124
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
Log Message:
-----------
[Statepoint] Treat result of atomicrmw xchg as a base pointer (#97280)
Atomic RMW Xchg wasn't handled before when searching for known base
pointers in the IR.
Commit: 40740c4494d971ce410e2051b8d3ea7bbe081c76
https://github.com/llvm/llvm-project/commit/40740c4494d971ce410e2051b8d3ea7bbe081c76
Author: Siddhesh Deodhar <153800103+siddhesh195 at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
Log Message:
-----------
Fix crash when using when using --finalize-memref-to-llvm (#112433)
This patch fixes crash when attempting to convert uint to int address
space during finalize-memref-to-llvm by doing the following:
1. Add a check to verify that IntegerAttr is signed int before calling
IntegerAttr::getInt()
2. Emit error when getMemRefAddressSpace returns a failure()
Closes #111242
---------
Co-authored-by: Christian Ulmann <christianulmann at gmail.com>
Commit: 2b885f056585f82903f067840e54557a5b444b65
https://github.com/llvm/llvm-project/commit/2b885f056585f82903f067840e54557a5b444b65
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Fix test for bots that don't default to C17
Commit: a749c98b49dc9a3863b685212d70be98b4f189c3
https://github.com/llvm/llvm-project/commit/a749c98b49dc9a3863b685212d70be98b4f189c3
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Baze] Add missing lldbDataFormatter.py back to BUILD.bazel. (#115519)
- [x] Add `utils/lldbDataFormatters.py` back.
Commit: fe5a64d1160209f22624b112b2629b0d6c4bb264
https://github.com/llvm/llvm-project/commit/fe5a64d1160209f22624b112b2629b0d6c4bb264
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
Log Message:
-----------
[fang][cuda] Allow * in call chevron syntax (#115381)
Using `*` in call chevron syntax should be allowed. This patch updates
the parser to allow this usage.
```
call sub<<<*,nbBlock>>>()
```
Commit: 86405ed1012c97b063cbde12350fdea141e1ab78
https://github.com/llvm/llvm-project/commit/86405ed1012c97b063cbde12350fdea141e1ab78
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
Log Message:
-----------
[DebugInfo][Reassociate] Preserve DebugLocs when reassociating subs (#114226)
In NegateValue in Reassociate, we return the negation of an existing
value in order to break a subtract into an negate + add, potentially
creating a new instruction to perform the negation, but we neglect to
propagate the DebugLoc of the sub being replaced to the negate
instruction if one is created. This patch adds that propagation.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 40e545098e8bb5a18988316331e46c4557378afa
https://github.com/llvm/llvm-project/commit/40e545098e8bb5a18988316331e46c4557378afa
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[clang][CIR] Move CIRGen types into clang::CIRGen (#115385)
https://github.com/llvm/clangir/issues/1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.
Commit: c72389d4feef9eafc902f99c41f85ed218b5bedf
https://github.com/llvm/llvm-project/commit/c72389d4feef9eafc902f99c41f85ed218b5bedf
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
Log Message:
-----------
[clang][CIR] Merge the mlir::cir namespace into cir (#115386)
https://github.com/llvm/clangir/issues/1025 discusses the motivation.
The mechanical parts of this change were done via:
find clang \( -name '*.h' -o -name '*.cpp' -o -name '*.td' \) -print0 |
xargs -0 perl -pi -e 's/mlir::cir/cir/g'
find clang \( -name '*.h' -o -name '*.cpp' \) -print0 | xargs -0 perl
-pi -e 's/::cir/cir/g'
There were some manual fixups and a clang-format run afterwards.
Commit: 0dbdb3251fe1f276785015c1de3b0a1035c9de8f
https://github.com/llvm/llvm-project/commit/0dbdb3251fe1f276785015c1de3b0a1035c9de8f
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Remove mlir-spirv-cpu-runner after 0e39b1348e5fcadb129a6f113e… (#115533)
…5d708a526d8faa
Commit: e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
https://github.com/llvm/llvm-project/commit/e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/AST/Decl.cpp
Log Message:
-----------
[clang] Avoid unnecessary call to clang::NamespaceDecl::isRedundantInlineQualifierFor(). (#115196)
We observed 2X slowdown in lldb's expression evaluation with
https://github.com/llvm/llvm-project/pull/109147 in some cases. It turns
out that calling `isRedundantInlineQualifierFor` is quite expensive.
Using short-circuit evaluation in the if statement to avoid unnecessary
calls to that function.
Commit: 5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
https://github.com/llvm/llvm-project/commit/5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
[RISCV] Add sub_to_add to RISCVPostLegalizerCombiner.
Commit: e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
https://github.com/llvm/llvm-project/commit/e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
Log Message:
-----------
[GlobalISel][AArch64] Allow vector ptr to int unmerges (#115228)
Vector pointer -> scalar integer unmerges are already legal. This
loosens the verifier check for vector-of-pointers -> vectors.
Commit: a29e623e1257b100b507c592a405fee2e0ff34b9
https://github.com/llvm/llvm-project/commit/a29e623e1257b100b507c592a405fee2e0ff34b9
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
Log Message:
-----------
[compiler-rt] Make add_custom_libcxx() resilient to DESTDIR being set
If DESTDIR is set in the environment during the build/test stage, the
local libc++ installation will be installed under DESTDIR instead of being
in the build directory.
See https://github.com/llvm/llvm-project/pull/115077#issuecomment-2464640457
and https://gitlab.kitware.com/cmake/cmake/-/issues/18165.
Pull Request: https://github.com/llvm/llvm-project/pull/115525
Commit: bbcd35270ef4597402b924d547d845893e7fd165
https://github.com/llvm/llvm-project/commit/bbcd35270ef4597402b924d547d845893e7fd165
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (#115539)
…293)"
This reverts commit da9499ebfb323602c42aeb674571fe89cec20ca6.
Commit: 6fb36f0bd0a34e6429960247cf088557ae7a6e96
https://github.com/llvm/llvm-project/commit/6fb36f0bd0a34e6429960247cf088557ae7a6e96
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
Log Message:
-----------
[flang][OpenMP] Remove std::variant with single alternative, NFC
Commit: 7dffc96a54f90569d6226dd5713c80fc8f30c76f
https://github.com/llvm/llvm-project/commit/7dffc96a54f90569d6226dd5713c80fc8f30c76f
Author: vporpo <vporpodas at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Clean up dead instructions (#115267)
When scalars get replaced by vectors the original scalars may become
dead. In that case erase them.
Commit: 144bdf3eb7128518ed162c5a168e3ec90922cd9e
https://github.com/llvm/llvm-project/commit/144bdf3eb7128518ed162c5a168e3ec90922cd9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
Log Message:
-----------
[VPlan] Also check if plan for best legacy VF contains simplifications.
The plan for the VF chosen by the legacy cost model could also contain
additional simplifications that cause cost differences. Also check if it
contains simplifications.
Fixes https://github.com/llvm/llvm-project/issues/114860.
Commit: db6f476e8e29c42691a3c3ea97d7230af2be5df8
https://github.com/llvm/llvm-project/commit/db6f476e8e29c42691a3c3ea97d7230af2be5df8
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Use "countMaxActiveBits() <= 5" to define uint5Bits (#115543)
countMaxTrailingOnes() is not correct. This patch follows the suggestion
from https://github.com/llvm/llvm-project/pull/115372.
Commit: 30ee3f4ec767f2f183d74eb949afa80b8b6261e2
https://github.com/llvm/llvm-project/commit/30ee3f4ec767f2f183d74eb949afa80b8b6261e2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)
Commit: 552f6fe4d503900cae7620f2ddfd7393be670d27
https://github.com/llvm/llvm-project/commit/552f6fe4d503900cae7620f2ddfd7393be670d27
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
Log Message:
-----------
[RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (#115402)
We don't add a custom node for REMW as we can detect it with (srem
(sexti32), (sexti32)).
Commit: dbad9412909a1879f29a4f717b2bf149c9a58369
https://github.com/llvm/llvm-project/commit/dbad9412909a1879f29a4f717b2bf149c9a58369
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Basic/Attributes.cpp
Log Message:
-----------
[NFC][Clang] Use StringSwitch instead of array for parsing attribute scope (#115414)
Commit: b99d4112585302cbd01f9b851a04adc6e4fb5218
https://github.com/llvm/llvm-project/commit/b99d4112585302cbd01f9b851a04adc6e4fb5218
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactoring breakpoints to not use the `g_dap` reference. (#115208)
Refactoring breakpoints to not use the `g_dap` reference.
Instead, when a breakpoint is constructed it will be passed a DAP
reference that it should use for its lifetime.
This is part of a larger refactor to remove the global `g_dap` variable
to allow us to create multiple DAP instances.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: ca33649abe5fad93c57afef54e43ed9b3249cd86
https://github.com/llvm/llvm-project/commit/ca33649abe5fad93c57afef54e43ed9b3249cd86
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
Commit: ccc9d7dc7af535aa240a96bc999911ee9ba2d534
https://github.com/llvm/llvm-project/commit/ccc9d7dc7af535aa240a96bc999911ee9ba2d534
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Update and extend ptradd.ll test. NFC
We can now support v4p0 pointers without running into verifier issues.
Commit: 441b82b20bf3a622155354e17ae66e0ccff50796
https://github.com/llvm/llvm-project/commit/441b82b20bf3a622155354e17ae66e0ccff50796
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/test/Dialect/Vector/int-range-interface.mlir
Log Message:
-----------
[mlir][NFC] IntegerRangeAnalysis: don't loop over splat attr (#115399)
Reland https://github.com/llvm/llvm-project/pull/115229 which was
reverted by https://github.com/llvm/llvm-project/pull/115388 because it
was hitting an assertion in IREE. From the original change: If the
`DenseIntElementsAttr` is a splat value, there is no need to loop over
the entire attr. Instead, just update with the splat value.
The problem with the original implementation is that `SplatElementsAttr`
might be an attr of non `APInt` (e.g. float) elements. Instead, check if
`DenseIntElementsAttr` is splat and use the splat value. Added a test to
ensure there's no crash when handling float attrs.
Commit: 8a7a7b5ffc690bd012cf090d31d47ec938248ba3
https://github.com/llvm/llvm-project/commit/8a7a7b5ffc690bd012cf090d31d47ec938248ba3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Remove unneeded code connecting blocks in VPBB:splitAt (NFC).
insertBlockAfter already takes care of transferring successors. Remove
unneeded code to transfer them manually.
Commit: 26a9f3f5906c62cff7f2245b98affa432b504a87
https://github.com/llvm/llvm-project/commit/26a9f3f5906c62cff7f2245b98affa432b504a87
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Cleanup getSameOpcode, return InstructionsState::invalid() for non-valid inputs
Just a cleanup and related changes
Commit: 8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
https://github.com/llvm/llvm-project/commit/8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/JSONUtils.cpp
Log Message:
-----------
[lldb-dap] Fix lldb-dap build for windows, missing PATH_MAX. (#115551)
This should fix https://lab.llvm.org/buildbot/#/builders/141/builds/3722
Commit: 7a6a52a2f0c6af63f210562d4a0345232d30d54d
https://github.com/llvm/llvm-project/commit/7a6a52a2f0c6af63f210562d4a0345232d30d54d
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/SandboxIR/Instruction.cpp
Log Message:
-----------
[SandboxIR] Remove incorrect assertion. (#115553)
`insertBefore` can be called on a detached instruction, and we can't
check that the underlying instructions are ordered because instructions
without BB parents have no order.
This problem showed up as a different assertion failure in
`llvm::Instruction::comesBefore` in one of the unit tests when
`EXPENSIVE_CHECKS` are enabled.
Commit: fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
https://github.com/llvm/llvm-project/commit/fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
Log Message:
-----------
[AMDGPU] Disable verifier in `call-args-inreg-no-sgpr-for-csrspill-xfail.ll`
Similar to f9bd083, this could fix expensive check failure.
Commit: d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
https://github.com/llvm/llvm-project/commit/d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Support derived type in cuf.alloc (#115550)
Number of bytes to allocate was not computed when using `cuf.alloc` with
a derived type. Update the conversion to compute the number of bytes and
emit an error when type is not supported.
Commit: 023483f5ba6bbbec64bb340578b00bfa3399691d
https://github.com/llvm/llvm-project/commit/023483f5ba6bbbec64bb340578b00bfa3399691d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
Log Message:
-----------
[flang][cuda][NFC] Add test for <<<*, block>>> lowering (#115534)
Chevron syntax has been update to allow `*` to be used for the grid
value. Make sure we set the three grid values to -1, 1, 1 in lowering.
Commit: 6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
https://github.com/llvm/llvm-project/commit/6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/runtime/CUDA/kernel.cpp
Log Message:
-----------
[flang][cuda] Compute grid x when calling a kernel with <<<*, block>>> (#115538)
`-1, 1, 1` is passed when calling a kernel with the `<<<*, block>>>`
syntax. Query the device to compute the grid.x value.
Commit: 50850bc78b00b991cb361cb94a151befd83f6a5d
https://github.com/llvm/llvm-project/commit/50850bc78b00b991cb361cb94a151befd83f6a5d
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[LV] Add test for preserving flags when widening casts; NFC
Commit: 8af5ae0648f85b9196a794700ebe5468a0cefd6b
https://github.com/llvm/llvm-project/commit/8af5ae0648f85b9196a794700ebe5468a0cefd6b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[VPlan] Preserve IR flags when widening casts
We have `nneg` for both `sext` and `uitofp`.
Fixes #114856
Closes #115373
Commit: 738250989ce516f02f809bdfde474a039c77e81f
https://github.com/llvm/llvm-project/commit/738250989ce516f02f809bdfde474a039c77e81f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
Log Message:
-----------
[Clang][perf-training] Do build of libLLVMSupport for perf training (#111625)
This adds a build of the libLLVMSupport to the lit suite that is used
for generating profile data. This helps to improve both PGO and BOLT
optimization of clang over the existing hello world training program.
I considered building all of LLVM instead of just libLLVMSupport, but
there is only a marginal increase in performance for PGO only builds
when training with a build of all of LLVM, and I didn't think it was
enough to justify the increased build times given that it is the default
configuration.
The benchmark[1] I did showed that using libLLVMSupport for training
gives a 1.35 +- 0.02 speed up for clang optimized with PGO + BOLT vs
just 1.05 +- 0.01 speed up when training with hello world.
For comparison, training with a full LLVM build gave a speed up of 1.35
+- 0.1.
Raw data:
| PGO Training | BOLT Training | Speed Up | Error Range |
| ------------ | ------------- | -------- | ----------- |
| LLVM Support | LLVM Support | 1.35 | 0.02 |
| LLVM All | LLVM All | 1.34 | 0.01 |
| LLVM Support | Hello World | 1.29 | 0.02 |
| LLVM All | PGO-ONLY | 1.27 | 0.02 |
| LLVM Support | PGO-ONLY | 1.22 | 0.02 |
| Hello World | Hello World | 1.05 | 0.01 |
| Hello World | PGO-ONLY | 1.03 | 0.01 |
Time it takes to generate profile data (on a 64-core system):
| Training Data | PGO | BOLT |
| ------------- | ----- | ----- |
| LLVM All | 1090s | 3239s |
| LLVM Support | 91s | 655s |
| Hello World | 2s | 9s |
[1] Benchmark was compiling SemaDecl.cpp
Commit: d936924f5e22e8efbc27873f62e8dfc6e410fcf9
https://github.com/llvm/llvm-project/commit/d936924f5e22e8efbc27873f62e8dfc6e410fcf9
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Profile/YAMLProfileReader.cpp
Log Message:
-----------
[BOLT][NFC] Make YamlProfileToFunction a DenseMap (#108712)
YAML function profiles have sparse function IDs, assigned from
sequential function IDs from profiled binary. For example, for one large
binary, YAML profile has 15K functions, but the highest ID is ~600K,
close to number of functions in the profiled binary.
In `matchProfileToFunction`, `YamlProfileToFunction` vector was resized
to match function ID, which entails a 40X overcommit. Change the type of
`YamlProfileToFunction` to DenseMap to reduce memory utilization.
#99891 makes use of it for profile lookup associated with a given binary
function.
Commit: 62a7bb09e3646780b7bceb7cef4eba257e3a9818
https://github.com/llvm/llvm-project/commit/62a7bb09e3646780b7bceb7cef4eba257e3a9818
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Resolve CHECK prefix conflict and add a bunch of FIXMEs to bitmanip tests. NFC
Commit: bc1aa2863bd33756a5cc0b729792be0aabed67f4
https://github.com/llvm/llvm-project/commit/bc1aa2863bd33756a5cc0b729792be0aabed67f4
Author: Lei Wang <wlei at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/test/Other/new-pm-pgo-O0.ll
Log Message:
-----------
[SampleFDO] Support enabling sample loader pass in O0 mode (#113985)
Add support for enabling sample loader pass in O0 mode(under
`-fsample-profile-use`). This can help verify PGO raw profile count
quality or provide a more accurate performance proxy(predictor), as O0
mode has minimal or no compiler optimizations that might otherwise
impact profile count accuracy.
- Explicitly disable the sample loader inlining to ensure it only emits
sampling annotation.
- Use flattened profile for O0 mode.
- Add the pass after `AddDiscriminatorsPass` pass to work with
`-fdebug-info-for-profiling`.
Commit: cb98366ea4ce02e739eb4091c6227b67b60616c9
https://github.com/llvm/llvm-project/commit/cb98366ea4ce02e739eb4091c6227b67b60616c9
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add exp10m1f (#115565)
Commit: ff98efa329f3866ed7ddd461e9473729c2b91568
https://github.com/llvm/llvm-project/commit/ff98efa329f3866ed7ddd461e9473729c2b91568
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV][GISel] Enable shift_immed_chain in RISCVPostLegalizerCombiner
This helps combine back to back shifts that may get created when
sext_inreg is legalized.
Commit: 818d715989a82a54bac038b9c293e34dbea45f5c
https://github.com/llvm/llvm-project/commit/818d715989a82a54bac038b9c293e34dbea45f5c
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] atan2: isTriviallyVectorizable; add to massv and accelerate veclibs (#113637)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
- Return true for atan2 from isTriviallyVectorizable
- Add atan2 to VecFuncs.def for massv and accelerate libraries.
- Add atan2 to hasOptimizedCodeGen
- Add atan2 support in llvm/lib/Analysis/ValueTracking.cpp
llvm::getIntrinsicForCallSite and update vectorization tests
- Add atan2 name check to isLoweredToCall in
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
- Note: there's no test coverage for these names in isLoweredToCall, except that Transforms/TailCallElim/inf-recursion.ll is impacted by the "fabs" case
Thanks to @jroelofs for the atan2 accelerate veclib and associated test
additions, plus the hasOptimizedCodeGen addition.
Part of: Implement the atan2 HLSL Function #70096.
Commit: ff2251543069d9a195256617620b5fdf81512471
https://github.com/llvm/llvm-project/commit/ff2251543069d9a195256617620b5fdf81512471
Author: Alan Zhao <ayzhao at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
R clang/test/CodeGen/X86/amx_avx512_api.c
R clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
R llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
R llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
R llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
R llvm/test/MC/Disassembler/X86/amx-avx512.txt
R llvm/test/MC/X86/amx-avx512-att.s
R llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070
Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
Commit: f791cfc822fab3fa87b4aa10ef96a3401481850f
https://github.com/llvm/llvm-project/commit/f791cfc822fab3fa87b4aa10ef96a3401481850f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port ff2251543069
Commit: 7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
https://github.com/llvm/llvm-project/commit/7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/lib/MC/MCPseudoProbe.cpp
Log Message:
-----------
[MC] Use StringRefs from pseudo_probe_desc section if it's mapped
Add `IsMMapped` flag to `buildGUID2FuncDescMap` controlling whether to
allocate a string in `FuncNameAllocator` or use StringRef directly.
Keep it false by default, only set it for BOLT use case because BOLT
keeps file sections in memory while processing them. llvm-profgen
constructs GUID2FuncDescMap and then releases the binary.
For medium sized binary with 0.8 GiB .pseudo_probe_desc section, this
saves 0.7 GiB peak RSS in perf2bolt.
Test Plan: no-op for llvm-profgen, NFC for perf2bolt
Reviewers: maksfb, dcci, wlei-llvm, rafaelauler, ayermolo
Reviewed By: wlei-llvm
Pull Request: https://github.com/llvm/llvm-project/pull/112996
Commit: b70eb8631386bbccca5a07bb0253aa738d4cda81
https://github.com/llvm/llvm-project/commit/b70eb8631386bbccca5a07bb0253aa738d4cda81
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
Log Message:
-----------
[lld][WebAssemlby] Implement --thinlto-object-suffix-replace/--thinlto-prefix-replace (#114625)
Fixes: #79604
Commit: 6548b6354d1d990e1c98736f5e7c3de876bedc8e
https://github.com/llvm/llvm-project/commit/6548b6354d1d990e1c98736f5e7c3de876bedc8e
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
Commit: d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
https://github.com/llvm/llvm-project/commit/d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
Log Message:
-----------
[HLSL] Add Append/ConsumeStructuredBuffer definitions to HLSLExternalSemaSource (#113643)
Adds `AppendStructuredBuffer` and `ConsumeStructuredBuffer` definition
to HLSLExternalSemaSource. Adds separate tests for the AST shape and
element types, and adds constructor/handle.fromBinding test case to
shared test file for structured buffers.
These buffers do not have any subscript operators. Append and Consume
methods will be added later in llvm/llvm-project#112968.
Fixes #112777
Commit: c93e001ca695e905cb965b36d63f7a348d1dd809
https://github.com/llvm/llvm-project/commit/c93e001ca695e905cb965b36d63f7a348d1dd809
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
Log Message:
-----------
[FIX][AMDGPU] Fix test case failures that caused by reapply of #112403
Commit: 60ea60e36eb6de19e8e509e5b50a390e95801321
https://github.com/llvm/llvm-project/commit/60ea60e36eb6de19e8e509e5b50a390e95801321
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Log Message:
-----------
[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC
Commit: c61832444d7539eddb939df1107a751a6784aff3
https://github.com/llvm/llvm-project/commit/c61832444d7539eddb939df1107a751a6784aff3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Teach extractCallsFromIR to look into inline stacks (#115441)
To undrift the profile, we need to extract as many caller-callee pairs
from the IR as we can to maximize the number of call sites in the
profile we can undrift.
Now, since MemProfUsePass runs after early inlining, some functions
have been inlined, and we may no longer have bodies for those
functions in the IR. To cope with this, this patch teaches
extractCallsFromIR to extract caller-calee pairs from inline stacks.
The output format of extractCallsFromIR remains the same. We still
return a map from caller GUIDs to lists of corresponding call sites.
Commit: 1bf385f10291101163a346c8f075d56e1578351b
https://github.com/llvm/llvm-project/commit/1bf385f10291101163a346c8f075d56e1578351b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
Log Message:
-----------
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
Commit: fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
https://github.com/llvm/llvm-project/commit/fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Add a comment why an export file is needed. (#115556)
- [x] Add follow-up comment on why the export file is needed in
BUILD.bazel
Commit: 501a58344179242f702f55e0ee5c039290426c54
https://github.com/llvm/llvm-project/commit/501a58344179242f702f55e0ee5c039290426c54
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
Log Message:
-----------
[TableGen][SelectionDAG] Remove the `implicit` DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`
However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`
The latter form is also more flexible as it allows reordering output
operands.
In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.
Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
Commit: 5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
https://github.com/llvm/llvm-project/commit/5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
Author: Mirko <mirkomueller97 at live.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/LiveRangeShrink.cpp
A llvm/test/CodeGen/X86/lrshrink-debug.ll
Log Message:
-----------
[CodeGen][X86] LiveRangeShrink: fix increment after end (#115276)
This fixes the infinite loop discovered in #114195.
Since we skip debug instructions at the start of the loop we do not need
to skip them again at the end of the loop.
Commit: 8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
https://github.com/llvm/llvm-project/commit/8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
Commit: cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
https://github.com/llvm/llvm-project/commit/cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 8f4401374ca1
Commit: 09b372aa60548b8ee94a801d3d966001ad60a677
https://github.com/llvm/llvm-project/commit/09b372aa60548b8ee94a801d3d966001ad60a677
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576)
SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses
a literal constant operand.
For vectors, SelectionDAG uses a type with the same number of elements
as other operand of the sext_inreg. I assume for GISel we would just use
the scalar size.
Commit: b83399eab603320d3c2998450f4ada83e7fe746c
https://github.com/llvm/llvm-project/commit/b83399eab603320d3c2998450f4ada83e7fe746c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
Log Message:
-----------
[GlobalISel] Remove unused includes (NFC) (#115429)
Identified with misc-include-cleaner.
Commit: fe6366928201b7500ee7e903c01bf4bbd661ee2d
https://github.com/llvm/llvm-project/commit/fe6366928201b7500ee7e903c01bf4bbd661ee2d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
A llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Support `MachineFunction` in `OptNoneInstrumentation` (#115471)
Support `MachineFunction` in `OptNoneInstrumentation`, also add
`isRequired` to all necessary passes.
Commit: 9afec3ca3e926cd481af372b72ee5bd7e54942d0
https://github.com/llvm/llvm-project/commit/9afec3ca3e926cd481af372b72ee5bd7e54942d0
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Fix test failure in #115471 (#115596)
Add triple to indicate this is x86 test.
Commit: 5a41800ea1d9bf382cf1039da6016550ddb072d7
https://github.com/llvm/llvm-project/commit/5a41800ea1d9bf382cf1039da6016550ddb072d7
Author: Afanasyev Ivan <ivafanas at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[SROA] Fix NumPromoted statistic for SROA pass (#115586)
`NumPromoted` stat should not be increased if `SROASkipMem2Reg` is set
and nothing is changed.
Commit: 10f35a04c94e96c1cc0497f2b3b2ab8536a98059
https://github.com/llvm/llvm-project/commit/10f35a04c94e96c1cc0497f2b3b2ab8536a98059
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Log Message:
-----------
[InstCombine] add control for SimplifyDemandedVectorElts depth limit (#113717)
Allows customizing the depth of the recursive search on vectors that
InstCombine does when looking for unused elements.
We find it helpful to be able to customize this for compile time
reasons.
Commit: 5a08acc1e7874a6cb4b273988b83e587e6fea605
https://github.com/llvm/llvm-project/commit/5a08acc1e7874a6cb4b273988b83e587e6fea605
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
Log Message:
-----------
[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)
Without this, you get an error "Do not know how to soften the result of
this operator!" when compiling for a soft float target.
The libcall names match those defined in glibc
<https://www.gnu.org/software/libc/manual/html_node/Misc-FP-Arithmetic.html>
and more recently added to LLVM's libc
<https://github.com/llvm/llvm-project/pull/86016>.
Commit: ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
https://github.com/llvm/llvm-project/commit/ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
Log Message:
-----------
[RISCV] When using global merging, don't enable merging of external globals by default (#115484)
AArch64 left this disabled after seeing some cases of slightly worse
codegen that weren't tracked down, so I suggest as a path to
incrementally moving towards enable globals merging we follow suit, and
evaluate turning on later.
This patch disables merging of external globals, but also adds a flag to
override that. This reduces churn in test cases, simplifies benchmarking
runs, and this flag can be removed later.
A follow-on PR enables the globals merging pass by default (and as it's
based on this commit, merging of external globals is disabled just as
they are for AArch64).
Commit: 8833a4474654f7413ae3c53a15e350e06bce2d2e
https://github.com/llvm/llvm-project/commit/8833a4474654f7413ae3c53a15e350e06bce2d2e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Connect scalar header to CFG in VPlan unit test.
This makes sure the VPIRBasicBlock is deleted when the VPlan is
destroyed.
Fixes https://github.com/llvm/llvm-project/issues/114623.
Commit: 581106759a3eb85d37aa004e0ad795dc8b433080
https://github.com/llvm/llvm-project/commit/581106759a3eb85d37aa004e0ad795dc8b433080
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/lto-arm64ec.ll
Log Message:
-----------
[LLD][COFF] Support ARM64EC in BitcodeFile::getMachineType (#115474)
Commit: 1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
https://github.com/llvm/llvm-project/commit/1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
Log Message:
-----------
[InstCombine] Add extra tests for preserving load metadata.
Test cases for https://github.com/llvm/llvm-project/issues/115595.
Commit: 56253c79c61fb5478bc3162cfe1e25e98791a148
https://github.com/llvm/llvm-project/commit/56253c79c61fb5478bc3162cfe1e25e98791a148
Author: David Green <david.green at arm.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Generate ptrtoint/inttoptr as opposed to bitcast in unmerge combine. (#115225)
When combining unmerge we could end up with ptr to i64 bitcasts. Make
sure they are created as ptrtoint/inttoptr instead.
Commit: 7ac62f33cffb618758edb6a0997c21b2319fbf9b
https://github.com/llvm/llvm-project/commit/7ac62f33cffb618758edb6a0997c21b2319fbf9b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add load/select test with noundef/invariant.load.
Further extends the test coverage added in 1aff96b3dfc with a load with
noundef and invariant.load metadata, which may trigger UB.
Commit: 6beaa123a2899f52dd5f37b881d7fc398d70e167
https://github.com/llvm/llvm-project/commit/6beaa123a2899f52dd5f37b881d7fc398d70e167
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrUtils.td
Log Message:
-----------
[X86] Make use of `null_frag` (NFC) (#115601)
Commit: 1d41543c95f884e6ebecc63ab9d0d30ce481345c
https://github.com/llvm/llvm-project/commit/1d41543c95f884e6ebecc63ab9d0d30ce481345c
Author: lntue <lntue at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M libc/src/math/generic/log1p.cpp
M libc/test/src/math/smoke/log1p_test.cpp
Log Message:
-----------
[libc][math] Fix log1p SEGV with large inputs when FTZ/DAZ flags are set. (#115541)
Commit: 3654183afb283c9515a482f07fde730dd458a883
https://github.com/llvm/llvm-project/commit/3654183afb283c9515a482f07fde730dd458a883
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Allow promotion if target is a declaration (#115555)
Fixes an oversight in the MemProf ICP handling, that was blocking
promotion/cloning of indirect calls when the profiled target is a
declaration (i.e wasn't imported). There is no issue promoting in
that case, and in fact the comment mentions we should attempt to at
least import as declarations to enable more promotion.
Note that normal ICP currently requires that the target be a definition,
which is how this check ended up here. The comment there says that it
must be a definition because ThinLTO could remove declarations for
symbols found to be globally dead in the binary. However, here we are
always performing MemProf ICP in the ThinLTO backends, which is after
the globally dead symbols are removed (via dropDeadSymbols before
starting the optimization pipeline) [1].
For now, guard this with an option (flag is off which means the new
promotion is enabled by default) to simplify debugging or disabling it
if
this proves problematic.
[1] In fact we could also be more aggressive in regular ICP when invoked
in the ThinLTO backend
Commit: 6fb2a6044f11e251c3847d227049d9dae8b87796
https://github.com/llvm/llvm-project/commit/6fb2a6044f11e251c3847d227049d9dae8b87796
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] Add test coverage for #115575
Commit: 958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
https://github.com/llvm/llvm-project/commit/958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] scalarizeBinopOrCmp - check for out of bounds element indices
Fixes #115575
Commit: ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
https://github.com/llvm/llvm-project/commit/ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
Log Message:
-----------
[Inliner] Prevent adding pointer attributes to non-pointer arguments (#115569)
Fixes a crash seen after #114311
Commit: c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
https://github.com/llvm/llvm-project/commit/c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
Log Message:
-----------
[lldb-dap] Use heterogenous lookups with std::map (NFC) (#115590)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: eedff8b4c0c667c39b034f02c9a40693dff63eda
https://github.com/llvm/llvm-project/commit/eedff8b4c0c667c39b034f02c9a40693dff63eda
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
Log Message:
-----------
[DebugInfo] Simplify code with std::map::operator[] (NFC) (#115591)
Commit: dfe43bd1ca46c59399b7cbbf81b09256232e27f9
https://github.com/llvm/llvm-project/commit/dfe43bd1ca46c59399b7cbbf81b09256232e27f9
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
Log Message:
-----------
[X86] Remove unused includes (NFC) (#115593)
Identified with misc-include-cleaner.
Commit: 95eeae195e608797314d71f7327e638a98764471
https://github.com/llvm/llvm-project/commit/95eeae195e608797314d71f7327e638a98764471
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add PredIdx and SuccIdx arguments to connectBlocks (NFC).
Add extra arguments to connectBlocks which allow selecting which
existing predecessor/successor to update. This avoids having to
disconnect blocks first unnecessarily.
Suggested in https://github.com/llvm/llvm-project/pull/114292.
Commit: f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
https://github.com/llvm/llvm-project/commit/f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/tools/llvm-pdbutil/PdbYaml.h
Log Message:
-----------
[llvm] Add explicit visibility macros to YAMLTraits classes (#111484)
These symbols need to be exported for llvm-pdbutil when using windows
shared library builds.
Exclude the YAML traits declared in llvm-pdbutil so there not declared
as dllimported which will causing missing symbol errors for windows
shared library builds.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
window.
Commit: 230946fad69c952dc434aa3e2f92853c1ee8d304
https://github.com/llvm/llvm-project/commit/230946fad69c952dc434aa3e2f92853c1ee8d304
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
Log Message:
-----------
[ADT] Mark reverse and concat as nodiscard (#115611)
It may not be immediately obvious if these two functions modify the
given ranges or return a view over them. We have seen downstream code
that mistakenly assumed the given range would be mutated.
Add the `[[nodiscard]]` attribute to prevent these errors. Also clarify
the lack of mutation in the documentation comments.
Commit: 69fb9bcde0312e672e6f2280f8662784731d79e6
https://github.com/llvm/llvm-project/commit/69fb9bcde0312e672e6f2280f8662784731d79e6
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
Log Message:
-----------
Fix false positive in bugprone-throw-keyword-missing (#115302)
Fixes #115055
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
https://github.com/llvm/llvm-project/commit/ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add insertOnEdge to VPBlockUtils (NFC).
Add a new helper to insert a new VPBlockBase on an edge between 2
blocks. Suggested in https://github.com/llvm/llvm-project/pull/114292
and also useful for some existing code.
Commit: c236dbc343b497c11790adc61cf4e041aeb42dbc
https://github.com/llvm/llvm-project/commit/c236dbc343b497c11790adc61cf4e041aeb42dbc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[Vectorize] Simplify code with MapVector::operator[] (NFC) (#115592)
Commit: 0ac4821b718dd14e80d3856efa532d52df6878bb
https://github.com/llvm/llvm-project/commit/0ac4821b718dd14e80d3856efa532d52df6878bb
Author: Javed Absar <106147771+javedabsar1 at users.noreply.github.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
Log Message:
-----------
[mlir][linalg] unfold projected permutation. (#114704)
Patterns to decompose the input operand(s) of a linalg.generic that has
a projected permutation` affine-map -- i.e. effectively a folded `transpose`,
`broadcast`, or a mixture of two -- into explicit transpose and broadcast.
This is useful for instance when trying to recognize named ops.
email: quic_mabsar at quicinc.com
Commit: 10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
https://github.com/llvm/llvm-project/commit/10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
Log Message:
-----------
[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: 38b0e1c939e818564019bb5bff95a0f1abbf9d19
https://github.com/llvm/llvm-project/commit/38b0e1c939e818564019bb5bff95a0f1abbf9d19
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Add legalizer-info-validation test. NFC
Based on the same test from AArch64. I used a reasonable superset
ISA string to get the most coverage. Might be worth adding more
RUN lines in the future.
Commit: 08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
https://github.com/llvm/llvm-project/commit/08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
Log Message:
-----------
Fix mistakes in #113532 (#115631)
Found during review #115151
Commit: d6e65a66095cc3c93ea78669bc41d0885780e8ea
https://github.com/llvm/llvm-project/commit/d6e65a66095cc3c93ea78669bc41d0885780e8ea
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
Fix a warning. [-Wunused-but-set-variable]
Commit: 3cdd86bb476bb90e535552fe86ba5f9d15f33d37
https://github.com/llvm/llvm-project/commit/3cdd86bb476bb90e535552fe86ba5f9d15f33d37
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Make GetMinMaxCost support FixedVectorType when REVEC is enabled. (#115417)
Commit: 639cafd05f5559c8fed92d58705dec817f876e23
https://github.com/llvm/llvm-project/commit/639cafd05f5559c8fed92d58705dec817f876e23
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Use boolean predicated legalization action methods to remove a custom lambda. (#115628)
Commit: f344367f583538746b13a5560bcdedacbd295ee7
https://github.com/llvm/llvm-project/commit/f344367f583538746b13a5560bcdedacbd295ee7
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/test/ELF/aarch64-feature-pac.s
Log Message:
-----------
[PAC][lld] Test warning emitted for non-PAuth-marked files with `-z pac-plt` (#112958)
b6162622c054f changed semantics of `-z pac-plt` initially introduced in
e208208a3132c, so, the following comment from test/ELF/aarch64-feature-pac.s
is no longer true:
> There are no warnings in this case as the choice to use PAC in PLT entries
> is orthogonal to the choice of using PAC in relocatable objects. The
> presence of the PAC .note.gnu.property is an indication of preference by
> the relocatable object.
This patch updates the test so we ensure a warning is emitted for an
input file when `-z pac-plt` is passed but the file does not have
GNU_PROPERTY_AARCH64_FEATURE_1_PAC set in GNU_PROPERTY_AARCH64_FEATURE_1_AND
property.
Commit: e4c14190bb097162e15cd5822b3de97ea7bac0d6
https://github.com/llvm/llvm-project/commit/e4c14190bb097162e15cd5822b3de97ea7bac0d6
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
M mlir/test/Analysis/test-dominance.mlir
M mlir/test/lib/IR/TestDominance.cpp
Log Message:
-----------
[mlir][IR] `DominanceInfo`: Fix inconsistency in proper block/op dominance (#115413)
An operation is considered to properly dominate itself in a graph
region. That's because there is no concept of "dominance" in a graph
region. (`dominates` returns "true" for all pairs of ops in the same
block. It makes sense to do the same for `properlyDominates`.)
Previously, a block was *not* considered to dominate itself in a graph
region. This commit fixes this asymmetry between ops and blocks: both
are now properly dominating themselves in a graph region.
Commit: e1495283cf74590fbdeb6d46ad815b4d10b1902f
https://github.com/llvm/llvm-project/commit/e1495283cf74590fbdeb6d46ad815b4d10b1902f
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/test/Driver/riscv-profiles.c
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.
We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024
So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.
Commit: 59770a43826f19ed2a735b1e461a43c63bd456bf
https://github.com/llvm/llvm-project/commit/59770a43826f19ed2a735b1e461a43c63bd456bf
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
Log Message:
-----------
[NFC] Correct imprecise file location in the comment. (#115630)
Commit: 4edd711b4d7ec60117bf77ab79491dba8cf3bb76
https://github.com/llvm/llvm-project/commit/4edd711b4d7ec60117bf77ab79491dba8cf3bb76
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor prefetch intrinsics (#115527)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.prefetch.1D -> 5D variants, supporting both Tile
and Im2Col modes. These intrinsics optionally support cache_hints as
indicated by the boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in cp-async-bulk-tensor-prefetch.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d822c099eeacc69f6bf834a6373a41d0c9f84a3e
https://github.com/llvm/llvm-project/commit/d822c099eeacc69f6bf834a6373a41d0c9f84a3e
Author: Douglas <8796590+dgg5503 at users.noreply.github.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[JITLink] Use `rsplit` on `-sectcreate` argument in llvm-jitlink (#115511)
This accounts for cases where the file path may contain an `@` symbol.
In such cases, the split occurs too early causing argument parsing to
fail.
Commit: 27bf45aa36386136db179c494358670a994a98a5
https://github.com/llvm/llvm-project/commit/27bf45aa36386136db179c494358670a994a98a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
Log Message:
-----------
[InstCombine] Fix poison safety of folding shufflevector into select (#115483)
We are allowed to fold shufflevector into select iff the condition is
guaranteed not to be poison or the RHS is a poison.
Alive2: https://alive2.llvm.org/ce/z/28zEWR
Closes https://github.com/llvm/llvm-project/issues/115465.
Commit: a5a1612deb7af713835b5c8cf22105c5699bc62d
https://github.com/llvm/llvm-project/commit/a5a1612deb7af713835b5c8cf22105c5699bc62d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
Log Message:
-----------
[VPlan] Consistently use DEBUG_TYPE loop-vectorize.
This ensures debug messages in VPlan.cpp are included in the commonly
used -debug-only=loop-vectorize.
Commit: 81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
https://github.com/llvm/llvm-project/commit/81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
Log Message:
-----------
[ORC] Move some typedefs from Core.h to a new header, CoreContainers.h. NFC.
This is a first step towards breaking up Core.h
Commit: 3d2849bd151f415b59044736e069c7605339b8e2
https://github.com/llvm/llvm-project/commit/3d2849bd151f415b59044736e069c7605339b8e2
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Move MaterializationUnit from Core.h into its own header. NFC.
Continuing Core.h clean-up.
Commit: 7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
https://github.com/llvm/llvm-project/commit/7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Switch to C++17 nested namespaces. NFC.
Commit: ac30a0f349c960184c0165adcd87baecfc48a1af
https://github.com/llvm/llvm-project/commit/ac30a0f349c960184c0165adcd87baecfc48a1af
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
Log Message:
-----------
[PAC][lld] Do not emit warnings for `-z pac-plt` with valid PAuth core info (#112959)
When PAuth core info is present and (platform,version) is not (0,0),
treat input files as pac-enabled and do not emit a warning with
`-z pac-plt` passed.
Commit: 2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
https://github.com/llvm/llvm-project/commit/2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/any
M libcxx/include/module.modulemap
M libcxx/include/type_traits
M libcxx/include/variant
Log Message:
-----------
[libc++][NFC] Merge add_{const, cv, volatile}.h into a single header (#115610)
There isn't much benefit in having granular headers for only a few
simple lines of code.
Commit: ad2d313f7455fe27896db8df9ea9aadd60b53436
https://github.com/llvm/llvm-project/commit/ad2d313f7455fe27896db8df9ea9aadd60b53436
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2c10664afafc
Commit: 7c13477351046c115ad86e047f3f7346bb925b19
https://github.com/llvm/llvm-project/commit/7c13477351046c115ad86e047f3f7346bb925b19
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Log Message:
-----------
[X86] Delete unused X86setcc_commute node (NFC) (#115650)
The last use was removed by 87aa59a0.
Commit: 99f1019f596f745c720e97137bcadb239c573e3e
https://github.com/llvm/llvm-project/commit/99f1019f596f745c720e97137bcadb239c573e3e
Author: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/docs/SafeBuffers.rst
Log Message:
-----------
[NFC] Trivial doc fixup in SafeBuffers.rst
Commit: 1d6d073fbbaebbde6891501fe20f02a0ea345131
https://github.com/llvm/llvm-project/commit/1d6d073fbbaebbde6891501fe20f02a0ea345131
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
Log Message:
-----------
[AArch64] Remove FeatureUseScalarIncVL
FeatureUseScalarIncVL is a tuning feature, used to control whether addvl or
add+cnt is used. It was previously added as a dependency for FeatureSVE2, an
architecture feature but this can be seen as a layering violation. The main
disadvantage is that -use-scalar-inc-vl cannot be used without disabling sve2
and all dependant features.
This patch now replaces that with an option that if unset defaults to hasSVE ||
hasSME, but is otherwise overriden by the option. The hope is that no cpus will
rely on the tuning feature (or we can readdit if needed.
Commit: c8f33738a5a801b5bc083ae9b2ced39ef1b12980
https://github.com/llvm/llvm-project/commit/c8f33738a5a801b5bc083ae9b2ced39ef1b12980
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64] Rewrite arm64-ext.ll test and cleanup. NFC
Commit: 91a48e06463b23679907e151bdfec3e6093e9f16
https://github.com/llvm/llvm-project/commit/91a48e06463b23679907e151bdfec3e6093e9f16
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64][GlobalISel] Implicitly truncate APInt in matchExt combine.
The APInt using FirstRealElt + 1 is intended to match the next element, which
might overflow the size of MaskBits. This prevents a new assert in APInt from
triggering.
Commit: 5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
https://github.com/llvm/llvm-project/commit/5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115626)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: a44ee8ec1c87be76e147d97f3be90a7e8630421b
https://github.com/llvm/llvm-project/commit/a44ee8ec1c87be76e147d97f3be90a7e8630421b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115633)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 2c0f463b2546a98e6215f3a85940ab9c0971d2aa
https://github.com/llvm/llvm-project/commit/2c0f463b2546a98e6215f3a85940ab9c0971d2aa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[Vectorize] Simplify code with DenseMap::operator[] (NFC) (#115635)
Commit: 1e25c921d523151e6ed2ffe86029ea2e2b267a6c
https://github.com/llvm/llvm-project/commit/1e25c921d523151e6ed2ffe86029ea2e2b267a6c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Log Message:
-----------
[AArch64/GISel] Remove unused includes (NFC) (#115636)
Identified with misc-include-cleaner.
Commit: 15ce2e183fb801ff418eb1347a9d5893e5665782
https://github.com/llvm/llvm-project/commit/15ce2e183fb801ff418eb1347a9d5893e5665782
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/source/Commands/CommandObjectMultiword.cpp
Log Message:
-----------
[lldb] Use heterogenous lookups with std::map (NFC) (#115590) (#115634)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: ff0698b258eba9afd888159358c7369c3f85e9ae
https://github.com/llvm/llvm-project/commit/ff0698b258eba9afd888159358c7369c3f85e9ae
Author: Will <william.fedele1 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix examples for float to int saturating intrinsics (#115629)
As per the [LangRef:Simple
Constants](https://llvm.org/docs/LangRef.html#simple-constants), exact
decimal values of floating-point constants are required. For instance,
23.9 is a repeating decimal in binary and results in the reported error.
https://godbolt.org/z/1h7ETPnf6
Fixes #113529.
Commit: 028ea71fdda0c02cd11421cd1d26bec6f378666e
https://github.com/llvm/llvm-project/commit/028ea71fdda0c02cd11421cd1d26bec6f378666e
Author: Julian Schmidt <git.julian.schmidt at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
Log Message:
-----------
[clang-tidy] fix insertion location for function pointers in cppcoreguidelines-init-variables (#112091)
Previously, the insertion location for the `= nullptr` fix would be
after the variable name. However, if the variable is of type function
pointer that is not an alias, then the insertion would happen inside the
type specification: `void (*a1)(void*);` -> `void (*a1 =
nullptr)(void*);`.
With this change, the insertion location will be at the next
'terminator'. That is, at the next `,` or `;`, as that will finish the
current declaration: `void (a1)(void*) = nullptr;`.
Fixes #112089
Commit: 7111d031f19ce7d523796b4812d6afcb2958b025
https://github.com/llvm/llvm-project/commit/7111d031f19ce7d523796b4812d6afcb2958b025
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
Log Message:
-----------
[Xtensa] Fix Clang -Wundefined-bool-conversion after #113450
Commit: 3006dddfe091bcb95924d72dddbb84f73186a344
https://github.com/llvm/llvm-project/commit/3006dddfe091bcb95924d72dddbb84f73186a344
Author: Janis Heims <janis.heims at undertheprinter.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/test/CodeGen/M68k/multiple-return.ll
Log Message:
-----------
[M68k] fix call frame destruction elimination when returning structs (#107579)
Fixes #106213.
This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.
Commit: dc11c0601577afb8f67513d041ee25dabe3555b9
https://github.com/llvm/llvm-project/commit/dc11c0601577afb8f67513d041ee25dabe3555b9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
Log Message:
-----------
[ORC] Move absoluteSymbols from Core.h to new AbsoluteSymbols.h header. NFC.
Continuing Core.h clean-up.
If you see any errors about a missing absoluteSymbols function you need to
include the new AbsoluteSymbols.h header.
Commit: 0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
https://github.com/llvm/llvm-project/commit/0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port dc11c0601577
Commit: 3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
https://github.com/llvm/llvm-project/commit/3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
Author: Doug Wyatt <doug at sonosphere.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
Log Message:
-----------
[Clang] SemaFunctionEffects: When verifying a function, ignore any conditional noexcept expression. (#115342)
---------
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
Commit: e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
https://github.com/llvm/llvm-project/commit/e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (#115436)
This is a follow-up patch for
https://github.com/llvm/llvm-project/pull/101811.
That we can remove the type checking for fp16 from SemaRISCV.cpp.
Fixes: https://github.com/llvm/llvm-project/issues/101621 and
https://github.com/llvm/llvm-project/issues/94306
Commit: 595f3e925adaffcb10d40e2e704c67556e9afb18
https://github.com/llvm/llvm-project/commit/595f3e925adaffcb10d40e2e704c67556e9afb18
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
Log Message:
-----------
[mlir][IR][NFC] `PostDominanceInfo`: Mark all functions as `const` (#115597)
Same as `DominanceInfo`, all functions should be `const`.
Commit: 5082acce4fd3646d5760c02b2c21d9cd2a1d7130
https://github.com/llvm/llvm-project/commit/5082acce4fd3646d5760c02b2c21d9cd2a1d7130
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Add custom libc++ workaround for CMake < 3.26
The INSTALL_BYPRODUCTS ExternalProject_Add() argument was only added in
CMake 3.26 and the current minimum is 3.20. Work around this by using an
explicit ExternalProject_Add_Step() call for the install step with a
BYPRODUCTS argument. We can't keep using the `install` name here since that
is reserved by the CMake implementation and results in errors when used.
This commit should be reverted once LLVM depends on CMake 3.26.
Pull Request: https://github.com/llvm/llvm-project/pull/115677
Commit: 9c55766055f31009f2f224f68404e5243e410074
https://github.com/llvm/llvm-project/commit/9c55766055f31009f2f224f68404e5243e410074
Author: Alex Richardson <alexrichardson at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M .github/workflows/libcxx-build-and-test.yaml
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/FunctionLayout.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Core/FunctionLayout.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/Inputs/spurious-marker-symbol.yaml
A bolt/test/AArch64/compact-code-model.s
A bolt/test/AArch64/spurious-marker-symbol.test
A bolt/test/X86/callcont-fallthru.s
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.h
M clang-tools-extra/clang-tidy/abseil/DurationRewriter.cpp
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/docs/ShadowCallStack.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/APINotes/Types.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/SYCLKernelInfo.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TemplateArgumentVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/AttributeCommonInfo.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesTypes.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/DynamicAllocator.h
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
A clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CIRGenAction.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPUtility.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/stdalign.h
M clang/lib/InstallAPI/Frontend.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp
M clang/lib/StaticAnalyzer/Checkers/TraversalChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
A clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
R clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/APINotes/Inputs/Headers/Lifetimebound.apinotes
M clang/test/APINotes/Inputs/Headers/Lifetimebound.h
M clang/test/APINotes/lifetimebound.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/AST/ast-dump-decl.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
M clang/test/AST/ast-print-openacc-loop-construct.cpp
R clang/test/ASTMerge/class-template-spec/Inputs/class-template-spec.cpp
R clang/test/ASTMerge/class-template-spec/test.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-return-value.cpp
R clang/test/Analysis/traversal-algorithm.mm
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
A clang/test/C/C2y/n3344.c
A clang/test/C/C2y/n3346.c
A clang/test/C/C2y/n3364.c
A clang/test/C/C2y/n3370.c
M clang/test/CIR/hello.c
R clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
R clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGen/PowerPC/altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
M clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
M clang/test/CodeGen/PowerPC/ppc-emmintrin.c
M clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init-no-parentheses.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init.c
M clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/SystemZ/zvector2.c
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vbmi2-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/avx512vlvbmi2-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
M clang/test/CodeGen/X86/xop-builtins-cmp.c
M clang/test/CodeGen/X86/xop-builtins.c
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-neon-3v.c
M clang/test/CodeGen/aarch64-neon-intrinsics.c
M clang/test/CodeGen/aarch64-neon-misc.c
M clang/test/CodeGen/aarch64-neon-shifts.c
M clang/test/CodeGen/aarch64-neon-tbl.c
M clang/test/CodeGen/aarch64-poly64.c
M clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c
M clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/arm-bf16-convert-intrinsics.c
M clang/test/CodeGen/arm-mve-intrinsics/absneg.c
M clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
M clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
M clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/vornq.c
M clang/test/CodeGen/arm-neon-shifts.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/attr-target-x86.c
A clang/test/CodeGen/builtin-counted-by-ref.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGen/builtinshufflevector2.c
M clang/test/CodeGen/const-init.c
M clang/test/CodeGen/matrix-type-operators.c
M clang/test/CodeGen/neon-immediate-ubsan.c
M clang/test/CodeGen/nofpclass.c
M clang/test/CodeGen/ppc-vec_ct-truncate.c
M clang/test/CodeGen/target-data.c
M clang/test/CodeGen/variadic-nvptx.c
M clang/test/CodeGen/vecshift.c
M clang/test/CodeGen/vector-scalar.c
M clang/test/CodeGenCUDA/Inputs/cuda.h
A clang/test/CodeGenCUDA/grid-constant.cu
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/auto-var-init.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenCXX/ext-vector-type-conditional.cpp
M clang/test/CodeGenCXX/matrix-type-builtins.cpp
M clang/test/CodeGenCXX/matrix-type-operators.cpp
M clang/test/CodeGenCXX/vector-size-conditional.cpp
M clang/test/CodeGenCXX/vector-splat-conversion.cpp
M clang/test/CodeGenHLSL/BasicFeatures/standard_conversion_sequences.hlsl
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/RasterizerOrderedStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
A clang/test/CodeGenHLSL/builtins/dot4add_u8packed.hlsl
A clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenOpenCL/bool_cast.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/logical-ops.cl
M clang/test/CodeGenOpenCL/partial_initializer.cl
M clang/test/CodeGenOpenCL/shifts.cl
M clang/test/CodeGenOpenCL/vector_literals.cl
M clang/test/Driver/XRay/xray-mode-flags.cpp
M clang/test/Driver/XRay/xray-shared.cpp
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/ps5-linker.c
M clang/test/Driver/riscv-features.c
M clang/test/Driver/riscv-profiles.c
M clang/test/Driver/x86-target-features.c
M clang/test/Headers/__clang_hip_math_deprecated.hip
M clang/test/Headers/wasm.c
M clang/test/Lexer/SourceLocationsOverflow.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/Misc/sloc-usage.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Modules/cxx-templates.cpp
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
A clang/test/OpenMP/allocate_allocator_modifier_ast_print.cpp
A clang/test/OpenMP/allocate_allocator_modifier_codegen.cpp
A clang/test/OpenMP/allocate_allocator_modifier_messages.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-cpu-supports.c
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/attr-target-clones-aarch64.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
M clang/test/Sema/declspec.c
M clang/test/Sema/gnu-flags.c
M clang/test/SemaCUDA/Inputs/cuda.h
A clang/test/SemaCUDA/grid-constant.cu
M clang/test/SemaCXX/attr-lifetimebound.cpp
M clang/test/SemaCXX/attr-target-version.cpp
M clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
A clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/dot4add_u8packed-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/firstbithigh-errors.hlsl
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
M clang/www/c_status.html
M cmake/Modules/CMakePolicy.cmake
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/include/sanitizer/tsan_interface_atomic.h
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
M compiler-rt/lib/builtins/aarch64/sme-libc-routines.c
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/builtins/cpu_model/riscv.c
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/orc/dlfcn_wrapper.cpp
M compiler-rt/lib/orc/elfnix_platform.cpp
M compiler-rt/lib/orc/elfnix_platform.h
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/include/flang/Common/Fortran.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Parser/token-sequence.h
M flang/include/flang/Runtime/CUDA/memory.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Common/Fortran.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-real.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/token-sequence.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/runtime/CUDA/kernel.cpp
M flang/runtime/CUDA/memory.cpp
M flang/runtime/assign.cpp
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private-ptr.mlir
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private.mlir
M flang/test/Driver/arch-specific-libdir-rpath.f95
M flang/test/Evaluate/errors01.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
M flang/test/Lower/PowerPC/ppc-vec-cmp.f90
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-perm.f90
M flang/test/Lower/PowerPC/ppc-vec-sel.f90
M flang/test/Lower/PowerPC/ppc-vec-shift.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
M flang/test/Parser/OpenMP/target-loop-unparse.f90
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
A flang/test/Preprocessing/defined-in-macro.F90
A flang/test/Semantics/Inputs/modfile70.mod
A flang/test/Semantics/OpenMP/loop-bind.f90
M flang/test/Semantics/OpenMP/nested-distribute.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/Semantics/cuf03.cuf
A flang/test/Semantics/cuf17.cuf
M flang/test/Semantics/modfile63.f90
A flang/test/Semantics/modfile70.f90
A flang/test/Semantics/rewrite03.f90
A flang/test/Transforms/debug-assumed-rank-array.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/hdr/func/CMakeLists.txt
R libc/hdr/func/_Exit.h
M libc/newhdrgen/yaml/math.yaml
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/newhdrgen/yaml/unistd.yaml
M libc/spec/linux.td
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
A libc/src/math/exp10m1f.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/exp10m1f.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/log1p.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/mremap.cpp
A libc/src/sys/mman/mremap.h
M libc/src/sys/socket/linux/recvmsg.cpp
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/pipe2.cpp
A libc/src/unistd/pipe2.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/exp10m1f_test.cpp
A libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10m1f_test.cpp
M libc/test/src/math/smoke/log1p_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/at_quick_exit_test.cpp
M libc/test/src/stdlib/atexit_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/mremap_test.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/pipe2_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
A libclc/clc/include/clc/clc_as_type.h
A libclc/clc/include/clc/integer/clc_abs.h
A libclc/clc/include/clc/integer/clc_abs.inc
A libclc/clc/include/clc/integer/clc_abs_diff.h
A libclc/clc/include/clc/integer/clc_abs_diff.inc
M libclc/clc/include/clc/internal/clc.h
A libclc/clc/include/clc/relational/binary_decl.inc
A libclc/clc/include/clc/relational/clc_all.h
A libclc/clc/include/clc/relational/clc_any.h
A libclc/clc/include/clc/relational/clc_bitselect.h
A libclc/clc/include/clc/relational/clc_bitselect.inc
A libclc/clc/include/clc/relational/clc_isequal.h
A libclc/clc/include/clc/relational/clc_isfinite.h
A libclc/clc/include/clc/relational/clc_isgreater.h
A libclc/clc/include/clc/relational/clc_isgreaterequal.h
A libclc/clc/include/clc/relational/clc_isinf.h
A libclc/clc/include/clc/relational/clc_isless.h
A libclc/clc/include/clc/relational/clc_islessequal.h
A libclc/clc/include/clc/relational/clc_islessgreater.h
A libclc/clc/include/clc/relational/clc_isnan.h
A libclc/clc/include/clc/relational/clc_isnormal.h
A libclc/clc/include/clc/relational/clc_isnotequal.h
A libclc/clc/include/clc/relational/clc_isordered.h
A libclc/clc/include/clc/relational/clc_isunordered.h
A libclc/clc/include/clc/relational/clc_select.h
A libclc/clc/include/clc/relational/clc_select.inc
A libclc/clc/include/clc/relational/clc_signbit.h
A libclc/clc/include/clc/relational/floatn.inc
A libclc/clc/include/clc/relational/relational.h
A libclc/clc/include/clc/relational/unary_decl.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_abs.cl
A libclc/clc/lib/generic/integer/clc_abs.inc
A libclc/clc/lib/generic/integer/clc_abs_diff.cl
A libclc/clc/lib/generic/integer/clc_abs_diff.inc
A libclc/clc/lib/generic/relational/clc_all.cl
A libclc/clc/lib/generic/relational/clc_any.cl
A libclc/clc/lib/generic/relational/clc_bitselect.cl
A libclc/clc/lib/generic/relational/clc_bitselect.inc
A libclc/clc/lib/generic/relational/clc_isequal.cl
A libclc/clc/lib/generic/relational/clc_isfinite.cl
A libclc/clc/lib/generic/relational/clc_isgreater.cl
A libclc/clc/lib/generic/relational/clc_isgreaterequal.cl
A libclc/clc/lib/generic/relational/clc_isinf.cl
A libclc/clc/lib/generic/relational/clc_isless.cl
A libclc/clc/lib/generic/relational/clc_islessequal.cl
A libclc/clc/lib/generic/relational/clc_islessgreater.cl
A libclc/clc/lib/generic/relational/clc_isnan.cl
A libclc/clc/lib/generic/relational/clc_isnormal.cl
A libclc/clc/lib/generic/relational/clc_isnotequal.cl
A libclc/clc/lib/generic/relational/clc_isordered.cl
A libclc/clc/lib/generic/relational/clc_isunordered.cl
A libclc/clc/lib/generic/relational/clc_select.cl
A libclc/clc/lib/generic/relational/clc_select.inc
A libclc/clc/lib/generic/relational/clc_signbit.cl
M libclc/generic/include/clc/relational/any.h
R libclc/generic/include/clc/relational/binary_decl.inc
R libclc/generic/include/clc/relational/floatn.inc
R libclc/generic/include/clc/relational/unary_decl.inc
M libclc/generic/lib/integer/abs.cl
M libclc/generic/lib/integer/abs.inc
M libclc/generic/lib/integer/abs_diff.cl
M libclc/generic/lib/integer/abs_diff.inc
M libclc/generic/lib/math/clc_exp10.cl
M libclc/generic/lib/math/clc_fma.cl
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/clc_ldexp.cl
M libclc/generic/lib/math/clc_nextafter.cl
M libclc/generic/lib/math/clc_remainder.cl
M libclc/generic/lib/math/clc_remquo.cl
M libclc/generic/lib/math/clc_tan.cl
M libclc/generic/lib/math/sincos_helpers.cl
M libclc/generic/lib/relational/all.cl
M libclc/generic/lib/relational/any.cl
A libclc/generic/lib/relational/binary_def.inc
M libclc/generic/lib/relational/bitselect.cl
M libclc/generic/lib/relational/isequal.cl
M libclc/generic/lib/relational/isfinite.cl
M libclc/generic/lib/relational/isgreater.cl
M libclc/generic/lib/relational/isgreaterequal.cl
M libclc/generic/lib/relational/isinf.cl
M libclc/generic/lib/relational/isless.cl
M libclc/generic/lib/relational/islessequal.cl
M libclc/generic/lib/relational/islessgreater.cl
M libclc/generic/lib/relational/isnan.cl
M libclc/generic/lib/relational/isnormal.cl
M libclc/generic/lib/relational/isnotequal.cl
M libclc/generic/lib/relational/isordered.cl
M libclc/generic/lib/relational/isunordered.cl
R libclc/generic/lib/relational/relational.h
M libclc/generic/lib/relational/signbit.cl
A libclc/generic/lib/relational/unary_def.inc
M libcxx/CMakeLists.txt
M libcxx/cmake/caches/Generic-hardening-mode-fast-with-abi-breaks.cmake
M libcxx/docs/DesignDocs/ThreadingSupportAPI.rst
M libcxx/docs/Hardening.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/TestingLibcxx.rst
M libcxx/docs/UserDocumentation.rst
M libcxx/docs/VendorDocumentation.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/adjacent_find.h
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/any_of.h
M libcxx/include/__algorithm/copy_if.h
M libcxx/include/__algorithm/count_if.h
M libcxx/include/__algorithm/find.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/lexicographical_compare.h
M libcxx/include/__algorithm/ranges_adjacent_find.h
M libcxx/include/__algorithm/ranges_all_of.h
M libcxx/include/__algorithm/ranges_any_of.h
M libcxx/include/__algorithm/ranges_copy_if.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/ranges_count_if.h
M libcxx/include/__algorithm/ranges_fill_n.h
M libcxx/include/__algorithm/sort.h
M libcxx/include/__algorithm/unique.h
M libcxx/include/__atomic/aliases.h
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__atomic/cxx_atomic_impl.h
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/high_resolution_clock.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/parser_std_format_spec.h
M libcxx/include/__chrono/statically_widen.h
M libcxx/include/__chrono/steady_clock.h
M libcxx/include/__chrono/time_zone.h
M libcxx/include/__chrono/time_zone_link.h
M libcxx/include/__chrono/tzdb.h
M libcxx/include/__chrono/tzdb_list.h
M libcxx/include/__chrono/zoned_time.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__config_site.in
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__cstddef/nullptr_t.h
M libcxx/include/__cstddef/ptrdiff_t.h
M libcxx/include/__cstddef/size_t.h
M libcxx/include/__cxx03/CMakeLists.txt
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/unexpected.h
M libcxx/include/__filesystem/directory_entry.h
M libcxx/include/__filesystem/directory_iterator.h
M libcxx/include/__filesystem/operations.h
M libcxx/include/__filesystem/path.h
M libcxx/include/__filesystem/recursive_directory_iterator.h
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__format/concepts.h
M libcxx/include/__format/format_arg_store.h
M libcxx/include/__format/format_context.h
M libcxx/include/__format/format_functions.h
M libcxx/include/__format/format_parse_context.h
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_char.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/__format/formatter_string.h
M libcxx/include/__format/parser_std_format_spec.h
M libcxx/include/__format/unicode.h
M libcxx/include/__format/write_escaped.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/hash.h
M libcxx/include/__fwd/fstream.h
M libcxx/include/__fwd/ios.h
M libcxx/include/__fwd/istream.h
M libcxx/include/__fwd/ostream.h
M libcxx/include/__fwd/sstream.h
M libcxx/include/__fwd/streambuf.h
M libcxx/include/__fwd/string.h
M libcxx/include/__fwd/string_view.h
M libcxx/include/__iterator/bounded_iter.h
A libcxx/include/__iterator/static_bounded_iter.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/apple.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/freebsd.h
M libcxx/include/__mbstate_t.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory_resource/synchronized_pool_resource.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__ostream/print.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/__random/random_device.h
M libcxx/include/__ranges/istream_view.h
M libcxx/include/__stop_token/atomic_unique_lock.h
M libcxx/include/__stop_token/stop_callback.h
M libcxx/include/__stop_token/stop_source.h
M libcxx/include/__stop_token/stop_state.h
M libcxx/include/__stop_token/stop_token.h
M libcxx/include/__string/char_traits.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/__thread/formatter.h
M libcxx/include/__thread/id.h
M libcxx/include/__thread/jthread.h
M libcxx/include/__thread/support.h
M libcxx/include/__thread/this_thread.h
M libcxx/include/__thread/thread.h
M libcxx/include/__thread/timed_backoff_policy.h
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_integral.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/__vector/vector.h
M libcxx/include/any
M libcxx/include/array
M libcxx/include/barrier
M libcxx/include/chrono
M libcxx/include/clocale
M libcxx/include/codecvt
M libcxx/include/complex
M libcxx/include/condition_variable
M libcxx/include/cstdint
M libcxx/include/cstdlib
M libcxx/include/deque
M libcxx/include/format
M libcxx/include/forward_list
M libcxx/include/fstream
M libcxx/include/future
M libcxx/include/iomanip
M libcxx/include/ios
M libcxx/include/iosfwd
M libcxx/include/iostream
M libcxx/include/istream
M libcxx/include/latch
M libcxx/include/list
M libcxx/include/locale
M libcxx/include/module.modulemap
M libcxx/include/mutex
M libcxx/include/new
M libcxx/include/ostream
M libcxx/include/print
M libcxx/include/ranges
M libcxx/include/regex
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/sstream
M libcxx/include/stdatomic.h
M libcxx/include/stop_token
M libcxx/include/streambuf
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/syncstream
M libcxx/include/thread
M libcxx/include/type_traits
M libcxx/include/variant
M libcxx/include/vector
M libcxx/include/version
M libcxx/include/wchar.h
M libcxx/modules/std.compat.cppm.in
M libcxx/modules/std.compat/clocale.inc
M libcxx/modules/std.compat/cstdlib.inc
M libcxx/modules/std.compat/cwchar.inc
M libcxx/modules/std.compat/cwctype.inc
M libcxx/modules/std.cppm.in
M libcxx/modules/std/atomic.inc
M libcxx/modules/std/barrier.inc
M libcxx/modules/std/chrono.inc
M libcxx/modules/std/clocale.inc
M libcxx/modules/std/codecvt.inc
M libcxx/modules/std/complex.inc
M libcxx/modules/std/condition_variable.inc
M libcxx/modules/std/cstdlib.inc
M libcxx/modules/std/cwchar.inc
M libcxx/modules/std/cwctype.inc
M libcxx/modules/std/filesystem.inc
M libcxx/modules/std/format.inc
M libcxx/modules/std/fstream.inc
M libcxx/modules/std/future.inc
M libcxx/modules/std/iomanip.inc
M libcxx/modules/std/ios.inc
M libcxx/modules/std/iosfwd.inc
M libcxx/modules/std/iostream.inc
M libcxx/modules/std/istream.inc
M libcxx/modules/std/latch.inc
M libcxx/modules/std/locale.inc
M libcxx/modules/std/memory.inc
M libcxx/modules/std/mutex.inc
M libcxx/modules/std/ostream.inc
M libcxx/modules/std/print.inc
M libcxx/modules/std/random.inc
M libcxx/modules/std/ranges.inc
M libcxx/modules/std/regex.inc
M libcxx/modules/std/semaphore.inc
M libcxx/modules/std/shared_mutex.inc
M libcxx/modules/std/spanstream.inc
M libcxx/modules/std/sstream.inc
M libcxx/modules/std/stop_token.inc
M libcxx/modules/std/streambuf.inc
M libcxx/modules/std/string.inc
M libcxx/modules/std/string_view.inc
M libcxx/modules/std/strstream.inc
M libcxx/modules/std/syncstream.inc
M libcxx/modules/std/thread.inc
M libcxx/src/algorithm.cpp
M libcxx/src/call_once.cpp
M libcxx/src/chrono.cpp
M libcxx/src/experimental/include/tzdb/tzdb_list_private.h
M libcxx/src/filesystem/time_utils.h
M libcxx/src/include/atomic_support.h
M libcxx/src/include/config_elast.h
M libcxx/src/ios.cpp
M libcxx/src/ios.instantiations.cpp
M libcxx/src/iostream.cpp
M libcxx/src/locale.cpp
M libcxx/src/memory.cpp
M libcxx/src/memory_resource.cpp
M libcxx/src/ostream.cpp
M libcxx/src/print.cpp
M libcxx/src/random_shuffle.cpp
M libcxx/src/std_stream.h
M libcxx/src/string.cpp
M libcxx/src/system_error.cpp
M libcxx/test/CMakeLists.txt
M libcxx/test/benchmarks/CMakeLists.txt
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/atomic_wait_vs_mutex_lock.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lit.cfg.py.in
R libcxx/test/benchmarks/lit.site.cfg.py.in
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/util_smartptr.bench.cpp
M libcxx/test/benchmarks/vector_operations.bench.cpp
M libcxx/test/configs/cmake-bridge.cfg.in
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.back.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.front.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.subscript.pass.cpp
M libcxx/test/libcxx/depr/depr.c.headers/extern_c.pass.cpp
M libcxx/test/libcxx/feature_test_macro/ftm_metadata.sh.py
M libcxx/test/libcxx/feature_test_macro/test_data.json
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/test/libcxx/feature_test_macro/version_header_implementation.sh.py
M libcxx/test/libcxx/include_as_c.sh.cpp
M libcxx/test/libcxx/input.output/iostream.format/print.fun/transcoding.pass.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.tests.h
A libcxx/test/std/containers/sequences/array/assert.back.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.front.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.indexing.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.iterators.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/barrier.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/latch.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/semaphore.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/stop_token.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/utilities/expected/expected.unexpected/equality.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp
M libcxx/test/support/filesystem_test_helper.h
M libcxx/test/support/test_macros.h
M libcxx/test/tools/clang_tidy_checks/internal_ftm_use.cpp
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/header_information.py
M libcxx/utils/libcxx/test/config.py
M libcxx/utils/libcxx/test/dsl.py
M libcxx/utils/libcxx/test/features.py
M libcxx/utils/libcxx/test/format.py
R libcxx/utils/libcxx/test/googlebenchmark.py
M libcxx/utils/libcxx/test/params.py
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
M libcxxabi/test/configs/cmake-bridge.cfg.in
M libunwind/src/UnwindRegistersRestore.S
M libunwind/src/UnwindRegistersSave.S
M libunwind/test/configs/cmake-bridge.cfg.in
M lld/COFF/Chunks.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Writer.cpp
M lld/Common/ErrorHandler.cpp
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/AVR.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/MSP430.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SPARCV9.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/CallGraphSort.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/EhFrame.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Thunks.cpp
M lld/ELF/Writer.cpp
M lld/include/lld/Common/ErrorHandler.h
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-altnames.s
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-delayimport.test
M lld/test/COFF/arm64ec-export-thunks.test
M lld/test/COFF/arm64ec-import.test
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-loadcfg.s
A lld/test/COFF/arm64ec-pdb.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/cfguard-off-instrumented.s
A lld/test/COFF/locally-imported-arm64ec.test
A lld/test/COFF/lto-arm64ec.ll
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
M lld/test/ELF/arm-fix-cortex-a8-blx.s
M lld/test/ELF/arm-fix-cortex-a8-recognize.s
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/source/Commands/CommandObjectMultiword.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ABI/CMakeLists.txt
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
A lldb/source/Plugins/ABI/LoongArch/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/test/API/commands/target/basic/TestTargetCommand.py
M lldb/test/API/functionalities/abbreviation/TestAbbreviations.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpointsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/common.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/main.cpp
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lang/cpp/const_static_integral_member/main.cpp
M lldb/test/API/lit.cfg.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/test/Shell/lit.cfg.py
M lldb/test/Unit/lit.cfg.py
M lldb/test/Unit/lit.site.cfg.py.in
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/unittests/Host/AlarmTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CodeReview.rst
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/docs/Contributing.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/TableGen/ProgRef.rst
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
M llvm/include/llvm/ADT/STLExtras.h
A llvm/include/llvm/Analysis/LastRunTrackingAnalysis.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/include/llvm/MC/MCSchedule.h
M llvm/include/llvm/Object/ObjectFile.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/SandboxIR/Pass.h
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/include/llvm/Transforms/InstCombine/InstCombine.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/include/llvm/Transforms/Scalar.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
R llvm/include/llvm/Transforms/Scalar/TLSVariableHoist.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CGSCCPassManager.cpp
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DemandedBits.cpp
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp
M llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp
M llvm/lib/Analysis/InstCount.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
A llvm/lib/Analysis/LastRunTrackingAnalysis.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/MC/MCDisassembler/Disassembler.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/MC/MCSchedule.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
M llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/lib/Target/M68k/M68kSubtarget.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSubtarget.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/Internalize.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
M llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/KCFI.cpp
M llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/ObjCARC/ProvenanceAnalysis.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/LoopPredication.cpp
M llvm/lib/Transforms/Scalar/LowerWidenableCondition.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/Scalar.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
R llvm/lib/Transforms/Scalar/TLSVariableHoist.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/BasicAA/phi-values-usage.ll
M llvm/test/Analysis/BasicAA/underlying-value.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
M llvm/test/Analysis/BranchProbabilityInfo/loop.ll
M llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/logicalop.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/div.ll
M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
M llvm/test/Analysis/CostModel/AMDGPU/fneg.ll
M llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll
M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
M llvm/test/Analysis/CostModel/AMDGPU/rem.ll
M llvm/test/Analysis/CostModel/ARM/divrem.ll
M llvm/test/Analysis/CostModel/ARM/logicalop.ll
M llvm/test/Analysis/CostModel/PowerPC/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/arith-int.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
M llvm/test/Analysis/CostModel/SystemZ/divrem-pow2.ll
M llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll
M llvm/test/Analysis/CostModel/SystemZ/logicalop.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
M llvm/test/Analysis/CostModel/X86/div-codesize.ll
M llvm/test/Analysis/CostModel/X86/div-latency.ll
M llvm/test/Analysis/CostModel/X86/div-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/div.ll
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Analysis/CostModel/X86/logicalop.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul-codesize.ll
M llvm/test/Analysis/CostModel/X86/mul-latency.ll
M llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul.ll
M llvm/test/Analysis/CostModel/X86/rem-codesize.ll
M llvm/test/Analysis/CostModel/X86/rem-latency.ll
M llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
M llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll
M llvm/test/Analysis/CostModel/X86/vdiv-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
M llvm/test/Analysis/CycleInfo/basic.ll
M llvm/test/Analysis/CycleInfo/unreachable-predecessor.ll
M llvm/test/Analysis/Delinearization/type_mismatch.ll
M llvm/test/Analysis/Delinearization/undef.ll
M llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
M llvm/test/Analysis/DemandedBits/vectors.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
M llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll
M llvm/test/Analysis/Dominators/basic.ll
M llvm/test/Analysis/Dominators/print-dot-dom.ll
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
M llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
M llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll
M llvm/test/Analysis/MemorySSA/cyclicphi.ll
M llvm/test/Analysis/MemorySSA/debugvalue.ll
M llvm/test/Analysis/MemorySSA/debugvalue2.ll
M llvm/test/Analysis/MemorySSA/forward-unreachable.ll
M llvm/test/Analysis/MemorySSA/function-clobber.ll
M llvm/test/Analysis/MemorySSA/invariant-groups.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-simplified-clone.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll
M llvm/test/Analysis/MemorySSA/phi-translation.ll
M llvm/test/Analysis/MemorySSA/pr28880.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr41640.ll
M llvm/test/Analysis/MemorySSA/pr41853.ll
M llvm/test/Analysis/MemorySSA/pr42940.ll
M llvm/test/Analysis/MemorySSA/pr43317.ll
M llvm/test/Analysis/MemorySSA/pr43320.ll
M llvm/test/Analysis/MemorySSA/pr43427.ll
M llvm/test/Analysis/MemorySSA/pr43438.ll
M llvm/test/Analysis/MemorySSA/pr43493.ll
M llvm/test/Analysis/MemorySSA/pr43541.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr45976.ll
M llvm/test/Analysis/MemorySSA/reduce_clobber_limit.ll
M llvm/test/Analysis/MemorySSA/renamephis.ll
M llvm/test/Analysis/MemorySSA/unreachable.ll
M llvm/test/Analysis/MemorySSA/update_unroll.ll
M llvm/test/Analysis/PhiValues/basic.ll
M llvm/test/Analysis/PhiValues/long_phi_chain.ll
M llvm/test/Analysis/PostDominators/pr6047_a.ll
M llvm/test/Analysis/PostDominators/pr6047_b.ll
M llvm/test/Analysis/PostDominators/pr6047_c.ll
M llvm/test/Analysis/PostDominators/pr6047_d.ll
M llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
M llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
M llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll
M llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll
M llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
M llvm/test/Analysis/ScalarEvolution/pr22674.ll
M llvm/test/Analysis/ScalarEvolution/pr22856.ll
M llvm/test/Analysis/ScalarEvolution/pr25369.ll
M llvm/test/Analysis/ScalarEvolution/scev-aa.ll
M llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll
M llvm/test/Analysis/ScalarEvolution/scev-invalid.ll
M llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
M llvm/test/Analysis/ValueTracking/known-bits.ll
M llvm/test/Analysis/ValueTracking/known-fpclass.ll
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
M llvm/test/Analysis/ValueTracking/knownbits-and-or-xor-lowbit.ll
M llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll
M llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
M llvm/test/Analysis/ValueTracking/knownzero-shift.ll
M llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
M llvm/test/Analysis/ValueTracking/numsignbits-shl.ll
M llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll
M llvm/test/Assembler/ConstantExprFold.ll
M llvm/test/Assembler/atomicrmw.ll
A llvm/test/Assembler/c-style-comment.ll
M llvm/test/Assembler/constant-splat.ll
M llvm/test/Assembler/convergence-control.ll
M llvm/test/Assembler/debug-info.ll
A llvm/test/Assembler/invalid-c-style-comment0.ll
A llvm/test/Assembler/invalid-c-style-comment1.ll
A llvm/test/Assembler/invalid-c-style-comment2.ll
A llvm/test/Assembler/invalid-c-style-comment3.ll
M llvm/test/Assembler/opaque-ptr.ll
M llvm/test/Assembler/target-type-param-errors.ll
M llvm/test/Bitcode/constantsTest.3.2.ll
M llvm/test/Bitcode/convergence-control.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
A llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/convertphitype.ll
M llvm/test/CodeGen/AArch64/double_reduct.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
A llvm/test/CodeGen/AArch64/latency.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
A llvm/test/CodeGen/AArch64/trunc-nsw-nuw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
A llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
R llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
A llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
A llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
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M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
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M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
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M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
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M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
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M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
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M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
R llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
A llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
A llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vni8-live-reg-opt.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
A llvm/test/CodeGen/ARM/latency.ll
M llvm/test/CodeGen/ARM/vector-promotion.ll
A llvm/test/CodeGen/DirectX/WaveActiveCountBits.ll
M llvm/test/CodeGen/DirectX/atan2.ll
R llvm/test/CodeGen/DirectX/clamp-vec.ll
M llvm/test/CodeGen/DirectX/clamp.ll
A llvm/test/CodeGen/DirectX/dot4add_u8packed.ll
M llvm/test/CodeGen/DirectX/exp-vec.ll
A llvm/test/CodeGen/DirectX/firstbithigh.ll
A llvm/test/CodeGen/DirectX/firstbitshigh_error.ll
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A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
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M llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll
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M llvm/test/SafepointIRVerifier/unrecorded-live-at-sp.ll
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M llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll
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M llvm/test/Transforms/BDCE/dead-uses.ll
M llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
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A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
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M llvm/test/Transforms/CorrelatedValuePropagation/overflows.ll
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
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M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
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A llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
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M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
M llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
M llvm/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll
M llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
M llvm/test/Transforms/InstCombine/canonicalize.ll
M llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
M llvm/test/Transforms/InstCombine/cast-int-icmp-eq-0.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
M llvm/test/Transforms/InstCombine/compare-signs.ll
M llvm/test/Transforms/InstCombine/compare-udiv.ll
M llvm/test/Transforms/InstCombine/consecutive-ptrmask.ll
M llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll
M llvm/test/Transforms/InstCombine/ctpop-cttz.ll
M llvm/test/Transforms/InstCombine/ctpop-pow2.ll
M llvm/test/Transforms/InstCombine/ctpop.ll
M llvm/test/Transforms/InstCombine/demorgan.ll
M llvm/test/Transforms/InstCombine/dependent-ivs.ll
M llvm/test/Transforms/InstCombine/div-shift.ll
M llvm/test/Transforms/InstCombine/div.ll
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
M llvm/test/Transforms/InstCombine/exact.ll
M llvm/test/Transforms/InstCombine/exp2-1.ll
M llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fabs-copysign.ll
M llvm/test/Transforms/InstCombine/fabs-fneg-fold.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/fast-math.ll
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 822ff0d8a4498d5595b1c6e0f9bd59ca48088e9e
https://github.com/llvm/llvm-project/commit/822ff0d8a4498d5595b1c6e0f9bd59ca48088e9e
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M .github/workflows/libcxx-build-and-test.yaml
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/FunctionLayout.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Core/FunctionLayout.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/Inputs/spurious-marker-symbol.yaml
A bolt/test/AArch64/compact-code-model.s
A bolt/test/AArch64/spurious-marker-symbol.test
A bolt/test/X86/callcont-fallthru.s
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.cpp
M clang-tools-extra/clang-include-fixer/InMemorySymbolIndex.h
M clang-tools-extra/clang-tidy/abseil/DurationRewriter.cpp
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/docs/ShadowCallStack.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/APINotes/Types.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/SYCLKernelInfo.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TemplateArgumentVisitor.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/AttributeCommonInfo.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.def
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Sema/SemaOpenMP.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesTypes.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/DynamicAllocator.h
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/OpenMPKinds.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
A clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CIRGenAction.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPUtility.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/stdalign.h
M clang/lib/InstallAPI/Frontend.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp
M clang/lib/StaticAnalyzer/Checkers/TraversalChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
A clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
R clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/APINotes/Inputs/Headers/Lifetimebound.apinotes
M clang/test/APINotes/Inputs/Headers/Lifetimebound.h
M clang/test/APINotes/lifetimebound.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/AST/ast-dump-decl.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
M clang/test/AST/ast-print-openacc-loop-construct.cpp
R clang/test/ASTMerge/class-template-spec/Inputs/class-template-spec.cpp
R clang/test/ASTMerge/class-template-spec/test.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
A clang/test/Analysis/Checkers/WebKit/call-args-checked-return-value.cpp
R clang/test/Analysis/traversal-algorithm.mm
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
A clang/test/C/C2y/n3344.c
A clang/test/C/C2y/n3346.c
A clang/test/C/C2y/n3364.c
A clang/test/C/C2y/n3370.c
M clang/test/CIR/hello.c
R clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
R clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/CodeGen/PowerPC/altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c
M clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
M clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
M clang/test/CodeGen/PowerPC/ppc-emmintrin.c
M clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init-no-parentheses.c
M clang/test/CodeGen/PowerPC/vector-bool-pixel-altivec-init.c
M clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/SystemZ/zvector2.c
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx10_2bf16-builtins.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vbmi2-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/avx512vlvbmi2-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
M clang/test/CodeGen/X86/xop-builtins-cmp.c
M clang/test/CodeGen/X86/xop-builtins.c
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-neon-3v.c
M clang/test/CodeGen/aarch64-neon-intrinsics.c
M clang/test/CodeGen/aarch64-neon-misc.c
M clang/test/CodeGen/aarch64-neon-shifts.c
M clang/test/CodeGen/aarch64-neon-tbl.c
M clang/test/CodeGen/aarch64-poly64.c
M clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c
M clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/arm-bf16-convert-intrinsics.c
M clang/test/CodeGen/arm-mve-intrinsics/absneg.c
M clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
M clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
M clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
M clang/test/CodeGen/arm-mve-intrinsics/vornq.c
M clang/test/CodeGen/arm-neon-shifts.c
M clang/test/CodeGen/arm_neon_intrinsics.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/attr-target-x86.c
A clang/test/CodeGen/builtin-counted-by-ref.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGen/builtinshufflevector2.c
M clang/test/CodeGen/const-init.c
M clang/test/CodeGen/matrix-type-operators.c
M clang/test/CodeGen/neon-immediate-ubsan.c
M clang/test/CodeGen/nofpclass.c
M clang/test/CodeGen/ppc-vec_ct-truncate.c
M clang/test/CodeGen/target-data.c
M clang/test/CodeGen/variadic-nvptx.c
M clang/test/CodeGen/vecshift.c
M clang/test/CodeGen/vector-scalar.c
M clang/test/CodeGenCUDA/Inputs/cuda.h
A clang/test/CodeGenCUDA/grid-constant.cu
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/auto-var-init.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenCXX/ext-vector-type-conditional.cpp
M clang/test/CodeGenCXX/matrix-type-builtins.cpp
M clang/test/CodeGenCXX/matrix-type-operators.cpp
M clang/test/CodeGenCXX/vector-size-conditional.cpp
M clang/test/CodeGenCXX/vector-splat-conversion.cpp
M clang/test/CodeGenHLSL/BasicFeatures/standard_conversion_sequences.hlsl
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/RasterizerOrderedStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-subscripts.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
A clang/test/CodeGenHLSL/builtins/dot4add_u8packed.hlsl
A clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/rcp.hlsl
M clang/test/CodeGenHLSL/builtins/sign.hlsl
M clang/test/CodeGenOpenCL/bool_cast.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/logical-ops.cl
M clang/test/CodeGenOpenCL/partial_initializer.cl
M clang/test/CodeGenOpenCL/shifts.cl
M clang/test/CodeGenOpenCL/vector_literals.cl
M clang/test/Driver/XRay/xray-mode-flags.cpp
M clang/test/Driver/XRay/xray-shared.cpp
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/ps5-linker.c
M clang/test/Driver/riscv-features.c
M clang/test/Driver/riscv-profiles.c
M clang/test/Driver/x86-target-features.c
M clang/test/Headers/__clang_hip_math_deprecated.hip
M clang/test/Headers/wasm.c
M clang/test/Lexer/SourceLocationsOverflow.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/Misc/sloc-usage.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Modules/cxx-templates.cpp
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
A clang/test/OpenMP/allocate_allocator_modifier_ast_print.cpp
A clang/test/OpenMP/allocate_allocator_modifier_codegen.cpp
A clang/test/OpenMP/allocate_allocator_modifier_messages.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-cpu-supports.c
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/attr-target-clones-aarch64.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
M clang/test/Sema/declspec.c
M clang/test/Sema/gnu-flags.c
M clang/test/SemaCUDA/Inputs/cuda.h
A clang/test/SemaCUDA/grid-constant.cu
M clang/test/SemaCXX/attr-lifetimebound.cpp
M clang/test/SemaCXX/attr-target-version.cpp
M clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
M clang/test/SemaCXX/cxx2c-placeholder-vars.cpp
A clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/dot4add_u8packed-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/firstbithigh-errors.hlsl
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
M clang/www/c_status.html
M cmake/Modules/CMakePolicy.cmake
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/include/sanitizer/tsan_interface_atomic.h
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
M compiler-rt/lib/builtins/aarch64/sme-libc-routines.c
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/builtins/cpu_model/riscv.c
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/orc/dlfcn_wrapper.cpp
M compiler-rt/lib/orc/elfnix_platform.cpp
M compiler-rt/lib/orc/elfnix_platform.h
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
M flang/include/flang/Common/Fortran-features.h
M flang/include/flang/Common/Fortran.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Parser/token-sequence.h
M flang/include/flang/Runtime/CUDA/memory.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Common/Fortran-features.cpp
M flang/lib/Common/Fortran.cpp
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/fold-real.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/token-sequence.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/runtime/CUDA/kernel.cpp
M flang/runtime/CUDA/memory.cpp
M flang/runtime/assign.cpp
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private-ptr.mlir
R flang/test/Analysis/AliasAnalysis/alias-analysis-omp-teams-distribute-private.mlir
M flang/test/Driver/arch-specific-libdir-rpath.f95
M flang/test/Evaluate/errors01.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
M flang/test/Lower/PowerPC/ppc-vec-cmp.f90
M flang/test/Lower/PowerPC/ppc-vec-convert.f90
M flang/test/Lower/PowerPC/ppc-vec-perm.f90
M flang/test/Lower/PowerPC/ppc-vec-sel.f90
M flang/test/Lower/PowerPC/ppc-vec-shift.f90
M flang/test/Lower/PowerPC/ppc-vec-splat.f90
M flang/test/Parser/OpenMP/target-loop-unparse.f90
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
A flang/test/Preprocessing/defined-in-macro.F90
A flang/test/Semantics/Inputs/modfile70.mod
A flang/test/Semantics/OpenMP/loop-bind.f90
M flang/test/Semantics/OpenMP/nested-distribute.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/Semantics/cuf03.cuf
A flang/test/Semantics/cuf17.cuf
M flang/test/Semantics/modfile63.f90
A flang/test/Semantics/modfile70.f90
A flang/test/Semantics/rewrite03.f90
A flang/test/Transforms/debug-assumed-rank-array.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/hdr/func/CMakeLists.txt
R libc/hdr/func/_Exit.h
M libc/newhdrgen/yaml/math.yaml
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/newhdrgen/yaml/unistd.yaml
M libc/spec/linux.td
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
A libc/src/math/exp10m1f.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/exp10m1f.cpp
M libc/src/math/generic/explogxf.h
M libc/src/math/generic/log1p.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/mremap.cpp
A libc/src/sys/mman/mremap.h
M libc/src/sys/socket/linux/recvmsg.cpp
M libc/src/unistd/CMakeLists.txt
M libc/src/unistd/linux/CMakeLists.txt
A libc/src/unistd/linux/pipe2.cpp
A libc/src/unistd/pipe2.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/exp10m1f_test.cpp
A libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10m1f_test.cpp
M libc/test/src/math/smoke/log1p_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/at_quick_exit_test.cpp
M libc/test/src/stdlib/atexit_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/mremap_test.cpp
M libc/test/src/unistd/CMakeLists.txt
A libc/test/src/unistd/pipe2_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
A libclc/clc/include/clc/clc_as_type.h
A libclc/clc/include/clc/integer/clc_abs.h
A libclc/clc/include/clc/integer/clc_abs.inc
A libclc/clc/include/clc/integer/clc_abs_diff.h
A libclc/clc/include/clc/integer/clc_abs_diff.inc
M libclc/clc/include/clc/internal/clc.h
A libclc/clc/include/clc/relational/binary_decl.inc
A libclc/clc/include/clc/relational/clc_all.h
A libclc/clc/include/clc/relational/clc_any.h
A libclc/clc/include/clc/relational/clc_bitselect.h
A libclc/clc/include/clc/relational/clc_bitselect.inc
A libclc/clc/include/clc/relational/clc_isequal.h
A libclc/clc/include/clc/relational/clc_isfinite.h
A libclc/clc/include/clc/relational/clc_isgreater.h
A libclc/clc/include/clc/relational/clc_isgreaterequal.h
A libclc/clc/include/clc/relational/clc_isinf.h
A libclc/clc/include/clc/relational/clc_isless.h
A libclc/clc/include/clc/relational/clc_islessequal.h
A libclc/clc/include/clc/relational/clc_islessgreater.h
A libclc/clc/include/clc/relational/clc_isnan.h
A libclc/clc/include/clc/relational/clc_isnormal.h
A libclc/clc/include/clc/relational/clc_isnotequal.h
A libclc/clc/include/clc/relational/clc_isordered.h
A libclc/clc/include/clc/relational/clc_isunordered.h
A libclc/clc/include/clc/relational/clc_select.h
A libclc/clc/include/clc/relational/clc_select.inc
A libclc/clc/include/clc/relational/clc_signbit.h
A libclc/clc/include/clc/relational/floatn.inc
A libclc/clc/include/clc/relational/relational.h
A libclc/clc/include/clc/relational/unary_decl.inc
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/integer/clc_abs.cl
A libclc/clc/lib/generic/integer/clc_abs.inc
A libclc/clc/lib/generic/integer/clc_abs_diff.cl
A libclc/clc/lib/generic/integer/clc_abs_diff.inc
A libclc/clc/lib/generic/relational/clc_all.cl
A libclc/clc/lib/generic/relational/clc_any.cl
A libclc/clc/lib/generic/relational/clc_bitselect.cl
A libclc/clc/lib/generic/relational/clc_bitselect.inc
A libclc/clc/lib/generic/relational/clc_isequal.cl
A libclc/clc/lib/generic/relational/clc_isfinite.cl
A libclc/clc/lib/generic/relational/clc_isgreater.cl
A libclc/clc/lib/generic/relational/clc_isgreaterequal.cl
A libclc/clc/lib/generic/relational/clc_isinf.cl
A libclc/clc/lib/generic/relational/clc_isless.cl
A libclc/clc/lib/generic/relational/clc_islessequal.cl
A libclc/clc/lib/generic/relational/clc_islessgreater.cl
A libclc/clc/lib/generic/relational/clc_isnan.cl
A libclc/clc/lib/generic/relational/clc_isnormal.cl
A libclc/clc/lib/generic/relational/clc_isnotequal.cl
A libclc/clc/lib/generic/relational/clc_isordered.cl
A libclc/clc/lib/generic/relational/clc_isunordered.cl
A libclc/clc/lib/generic/relational/clc_select.cl
A libclc/clc/lib/generic/relational/clc_select.inc
A libclc/clc/lib/generic/relational/clc_signbit.cl
M libclc/generic/include/clc/relational/any.h
R libclc/generic/include/clc/relational/binary_decl.inc
R libclc/generic/include/clc/relational/floatn.inc
R libclc/generic/include/clc/relational/unary_decl.inc
M libclc/generic/lib/integer/abs.cl
M libclc/generic/lib/integer/abs.inc
M libclc/generic/lib/integer/abs_diff.cl
M libclc/generic/lib/integer/abs_diff.inc
M libclc/generic/lib/math/clc_exp10.cl
M libclc/generic/lib/math/clc_fma.cl
M libclc/generic/lib/math/clc_fmod.cl
M libclc/generic/lib/math/clc_hypot.cl
M libclc/generic/lib/math/clc_ldexp.cl
M libclc/generic/lib/math/clc_nextafter.cl
M libclc/generic/lib/math/clc_remainder.cl
M libclc/generic/lib/math/clc_remquo.cl
M libclc/generic/lib/math/clc_tan.cl
M libclc/generic/lib/math/sincos_helpers.cl
M libclc/generic/lib/relational/all.cl
M libclc/generic/lib/relational/any.cl
A libclc/generic/lib/relational/binary_def.inc
M libclc/generic/lib/relational/bitselect.cl
M libclc/generic/lib/relational/isequal.cl
M libclc/generic/lib/relational/isfinite.cl
M libclc/generic/lib/relational/isgreater.cl
M libclc/generic/lib/relational/isgreaterequal.cl
M libclc/generic/lib/relational/isinf.cl
M libclc/generic/lib/relational/isless.cl
M libclc/generic/lib/relational/islessequal.cl
M libclc/generic/lib/relational/islessgreater.cl
M libclc/generic/lib/relational/isnan.cl
M libclc/generic/lib/relational/isnormal.cl
M libclc/generic/lib/relational/isnotequal.cl
M libclc/generic/lib/relational/isordered.cl
M libclc/generic/lib/relational/isunordered.cl
R libclc/generic/lib/relational/relational.h
M libclc/generic/lib/relational/signbit.cl
A libclc/generic/lib/relational/unary_def.inc
M libcxx/CMakeLists.txt
M libcxx/cmake/caches/Generic-hardening-mode-fast-with-abi-breaks.cmake
M libcxx/docs/DesignDocs/ThreadingSupportAPI.rst
M libcxx/docs/Hardening.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/TestingLibcxx.rst
M libcxx/docs/UserDocumentation.rst
M libcxx/docs/VendorDocumentation.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/adjacent_find.h
M libcxx/include/__algorithm/all_of.h
M libcxx/include/__algorithm/any_of.h
M libcxx/include/__algorithm/copy_if.h
M libcxx/include/__algorithm/count_if.h
M libcxx/include/__algorithm/find.h
M libcxx/include/__algorithm/iterator_operations.h
M libcxx/include/__algorithm/lexicographical_compare.h
M libcxx/include/__algorithm/ranges_adjacent_find.h
M libcxx/include/__algorithm/ranges_all_of.h
M libcxx/include/__algorithm/ranges_any_of.h
M libcxx/include/__algorithm/ranges_copy_if.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/ranges_count_if.h
M libcxx/include/__algorithm/ranges_fill_n.h
M libcxx/include/__algorithm/sort.h
M libcxx/include/__algorithm/unique.h
M libcxx/include/__atomic/aliases.h
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__atomic/cxx_atomic_impl.h
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/high_resolution_clock.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/parser_std_format_spec.h
M libcxx/include/__chrono/statically_widen.h
M libcxx/include/__chrono/steady_clock.h
M libcxx/include/__chrono/time_zone.h
M libcxx/include/__chrono/time_zone_link.h
M libcxx/include/__chrono/tzdb.h
M libcxx/include/__chrono/tzdb_list.h
M libcxx/include/__chrono/zoned_time.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__config_site.in
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__cstddef/nullptr_t.h
M libcxx/include/__cstddef/ptrdiff_t.h
M libcxx/include/__cstddef/size_t.h
M libcxx/include/__cxx03/CMakeLists.txt
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/unexpected.h
M libcxx/include/__filesystem/directory_entry.h
M libcxx/include/__filesystem/directory_iterator.h
M libcxx/include/__filesystem/operations.h
M libcxx/include/__filesystem/path.h
M libcxx/include/__filesystem/recursive_directory_iterator.h
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__format/concepts.h
M libcxx/include/__format/format_arg_store.h
M libcxx/include/__format/format_context.h
M libcxx/include/__format/format_functions.h
M libcxx/include/__format/format_parse_context.h
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_char.h
M libcxx/include/__format/formatter_floating_point.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__format/formatter_output.h
M libcxx/include/__format/formatter_string.h
M libcxx/include/__format/parser_std_format_spec.h
M libcxx/include/__format/unicode.h
M libcxx/include/__format/write_escaped.h
M libcxx/include/__functional/function.h
M libcxx/include/__functional/hash.h
M libcxx/include/__fwd/fstream.h
M libcxx/include/__fwd/ios.h
M libcxx/include/__fwd/istream.h
M libcxx/include/__fwd/ostream.h
M libcxx/include/__fwd/sstream.h
M libcxx/include/__fwd/streambuf.h
M libcxx/include/__fwd/string.h
M libcxx/include/__fwd/string_view.h
M libcxx/include/__iterator/bounded_iter.h
A libcxx/include/__iterator/static_bounded_iter.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/apple.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_defaults.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/locale_base_api/freebsd.h
M libcxx/include/__mbstate_t.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory_resource/synchronized_pool_resource.h
M libcxx/include/__mutex/mutex.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__ostream/print.h
M libcxx/include/__random/binomial_distribution.h
M libcxx/include/__random/random_device.h
M libcxx/include/__ranges/istream_view.h
M libcxx/include/__stop_token/atomic_unique_lock.h
M libcxx/include/__stop_token/stop_callback.h
M libcxx/include/__stop_token/stop_source.h
M libcxx/include/__stop_token/stop_state.h
M libcxx/include/__stop_token/stop_token.h
M libcxx/include/__string/char_traits.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/__support/xlocale/__strtonum_fallback.h
M libcxx/include/__thread/formatter.h
M libcxx/include/__thread/id.h
M libcxx/include/__thread/jthread.h
M libcxx/include/__thread/support.h
M libcxx/include/__thread/this_thread.h
M libcxx/include/__thread/thread.h
M libcxx/include/__thread/timed_backoff_policy.h
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_integral.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/__vector/vector.h
M libcxx/include/any
M libcxx/include/array
M libcxx/include/barrier
M libcxx/include/chrono
M libcxx/include/clocale
M libcxx/include/codecvt
M libcxx/include/complex
M libcxx/include/condition_variable
M libcxx/include/cstdint
M libcxx/include/cstdlib
M libcxx/include/deque
M libcxx/include/format
M libcxx/include/forward_list
M libcxx/include/fstream
M libcxx/include/future
M libcxx/include/iomanip
M libcxx/include/ios
M libcxx/include/iosfwd
M libcxx/include/iostream
M libcxx/include/istream
M libcxx/include/latch
M libcxx/include/list
M libcxx/include/locale
M libcxx/include/module.modulemap
M libcxx/include/mutex
M libcxx/include/new
M libcxx/include/ostream
M libcxx/include/print
M libcxx/include/ranges
M libcxx/include/regex
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/sstream
M libcxx/include/stdatomic.h
M libcxx/include/stop_token
M libcxx/include/streambuf
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/syncstream
M libcxx/include/thread
M libcxx/include/type_traits
M libcxx/include/variant
M libcxx/include/vector
M libcxx/include/version
M libcxx/include/wchar.h
M libcxx/modules/std.compat.cppm.in
M libcxx/modules/std.compat/clocale.inc
M libcxx/modules/std.compat/cstdlib.inc
M libcxx/modules/std.compat/cwchar.inc
M libcxx/modules/std.compat/cwctype.inc
M libcxx/modules/std.cppm.in
M libcxx/modules/std/atomic.inc
M libcxx/modules/std/barrier.inc
M libcxx/modules/std/chrono.inc
M libcxx/modules/std/clocale.inc
M libcxx/modules/std/codecvt.inc
M libcxx/modules/std/complex.inc
M libcxx/modules/std/condition_variable.inc
M libcxx/modules/std/cstdlib.inc
M libcxx/modules/std/cwchar.inc
M libcxx/modules/std/cwctype.inc
M libcxx/modules/std/filesystem.inc
M libcxx/modules/std/format.inc
M libcxx/modules/std/fstream.inc
M libcxx/modules/std/future.inc
M libcxx/modules/std/iomanip.inc
M libcxx/modules/std/ios.inc
M libcxx/modules/std/iosfwd.inc
M libcxx/modules/std/iostream.inc
M libcxx/modules/std/istream.inc
M libcxx/modules/std/latch.inc
M libcxx/modules/std/locale.inc
M libcxx/modules/std/memory.inc
M libcxx/modules/std/mutex.inc
M libcxx/modules/std/ostream.inc
M libcxx/modules/std/print.inc
M libcxx/modules/std/random.inc
M libcxx/modules/std/ranges.inc
M libcxx/modules/std/regex.inc
M libcxx/modules/std/semaphore.inc
M libcxx/modules/std/shared_mutex.inc
M libcxx/modules/std/spanstream.inc
M libcxx/modules/std/sstream.inc
M libcxx/modules/std/stop_token.inc
M libcxx/modules/std/streambuf.inc
M libcxx/modules/std/string.inc
M libcxx/modules/std/string_view.inc
M libcxx/modules/std/strstream.inc
M libcxx/modules/std/syncstream.inc
M libcxx/modules/std/thread.inc
M libcxx/src/algorithm.cpp
M libcxx/src/call_once.cpp
M libcxx/src/chrono.cpp
M libcxx/src/experimental/include/tzdb/tzdb_list_private.h
M libcxx/src/filesystem/time_utils.h
M libcxx/src/include/atomic_support.h
M libcxx/src/include/config_elast.h
M libcxx/src/ios.cpp
M libcxx/src/ios.instantiations.cpp
M libcxx/src/iostream.cpp
M libcxx/src/locale.cpp
M libcxx/src/memory.cpp
M libcxx/src/memory_resource.cpp
M libcxx/src/ostream.cpp
M libcxx/src/print.cpp
M libcxx/src/random_shuffle.cpp
M libcxx/src/std_stream.h
M libcxx/src/string.cpp
M libcxx/src/system_error.cpp
M libcxx/test/CMakeLists.txt
M libcxx/test/benchmarks/CMakeLists.txt
M libcxx/test/benchmarks/algorithms/min.bench.cpp
M libcxx/test/benchmarks/atomic_wait_vs_mutex_lock.bench.cpp
M libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lit.cfg.py.in
R libcxx/test/benchmarks/lit.site.cfg.py.in
M libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
M libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/test/benchmarks/util_smartptr.bench.cpp
M libcxx/test/benchmarks/vector_operations.bench.cpp
M libcxx/test/configs/cmake-bridge.cfg.in
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.back.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.front.pass.cpp
R libcxx/test/libcxx/containers/sequences/array/array.zero/assert.subscript.pass.cpp
M libcxx/test/libcxx/depr/depr.c.headers/extern_c.pass.cpp
M libcxx/test/libcxx/feature_test_macro/ftm_metadata.sh.py
M libcxx/test/libcxx/feature_test_macro/test_data.json
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/test/libcxx/feature_test_macro/version_header_implementation.sh.py
M libcxx/test/libcxx/include_as_c.sh.cpp
M libcxx/test/libcxx/input.output/iostream.format/print.fun/transcoding.pass.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/libcxx/vendor/apple/availability-with-pedantic-errors.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/container.adaptors.format/format.functions.tests.h
A libcxx/test/std/containers/sequences/array/assert.back.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.front.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.indexing.pass.cpp
A libcxx/test/std/containers/sequences/array/assert.iterators.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/barrier.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/latch.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/semaphore.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/stop_token.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/utilities/expected/expected.unexpected/equality.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtmap/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.cmp/cmp_nullptr.pass.cpp
M libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.special/cmp_nullptr.pass.cpp
M libcxx/test/support/filesystem_test_helper.h
M libcxx/test/support/test_macros.h
M libcxx/test/tools/clang_tidy_checks/internal_ftm_use.cpp
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/header_information.py
M libcxx/utils/libcxx/test/config.py
M libcxx/utils/libcxx/test/dsl.py
M libcxx/utils/libcxx/test/features.py
M libcxx/utils/libcxx/test/format.py
R libcxx/utils/libcxx/test/googlebenchmark.py
M libcxx/utils/libcxx/test/params.py
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
M libcxxabi/test/configs/cmake-bridge.cfg.in
M libunwind/src/UnwindRegistersRestore.S
M libunwind/src/UnwindRegistersSave.S
M libunwind/test/configs/cmake-bridge.cfg.in
M lld/COFF/Chunks.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Writer.cpp
M lld/Common/ErrorHandler.cpp
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/AVR.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/MSP430.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SPARCV9.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/CallGraphSort.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/EhFrame.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptLexer.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Thunks.cpp
M lld/ELF/Writer.cpp
M lld/include/lld/Common/ErrorHandler.h
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-altnames.s
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-delayimport.test
M lld/test/COFF/arm64ec-export-thunks.test
M lld/test/COFF/arm64ec-import.test
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-loadcfg.s
A lld/test/COFF/arm64ec-pdb.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/cfguard-off-instrumented.s
A lld/test/COFF/locally-imported-arm64ec.test
A lld/test/COFF/lto-arm64ec.ll
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
M lld/test/ELF/arm-fix-cortex-a8-blx.s
M lld/test/ELF/arm-fix-cortex-a8-recognize.s
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/source/Commands/CommandObjectMultiword.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ABI/CMakeLists.txt
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
A lldb/source/Plugins/ABI/LoongArch/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/test/API/commands/target/basic/TestTargetCommand.py
M lldb/test/API/functionalities/abbreviation/TestAbbreviations.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpointsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/common.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/main.cpp
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lang/cpp/const_static_integral_member/main.cpp
M lldb/test/API/lit.cfg.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/test/Shell/lit.cfg.py
M lldb/test/Unit/lit.cfg.py
M lldb/test/Unit/lit.site.cfg.py.in
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/unittests/Host/AlarmTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CodeReview.rst
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/docs/Contributing.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/TableGen/ProgRef.rst
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
M llvm/include/llvm/ADT/STLExtras.h
A llvm/include/llvm/Analysis/LastRunTrackingAnalysis.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/include/llvm/MC/MCSchedule.h
M llvm/include/llvm/Object/ObjectFile.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/SandboxIR/Pass.h
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/include/llvm/Transforms/InstCombine/InstCombine.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/include/llvm/Transforms/Scalar.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
R llvm/include/llvm/Transforms/Scalar/TLSVariableHoist.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/CGSCCPassManager.cpp
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/Analysis/CostModel.cpp
M llvm/lib/Analysis/CycleAnalysis.cpp
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DemandedBits.cpp
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp
M llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp
M llvm/lib/Analysis/InstCount.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
A llvm/lib/Analysis/LastRunTrackingAnalysis.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/MustExecute.cpp
M llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/MC/MCDisassembler/Disassembler.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/MC/MCSchedule.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
M llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/lib/Target/M68k/M68kSubtarget.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSubtarget.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
M llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCA/X86CustomBehaviour.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/HipStdPar/HipStdPar.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/Internalize.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/BoundsChecking.cpp
M llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp
M llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/KCFI.cpp
M llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp
M llvm/lib/Transforms/ObjCARC/ProvenanceAnalysis.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/LoopPredication.cpp
M llvm/lib/Transforms/Scalar/LowerWidenableCondition.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/Scalar.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
R llvm/lib/Transforms/Scalar/TLSVariableHoist.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/BasicAA/phi-values-usage.ll
M llvm/test/Analysis/BasicAA/underlying-value.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
M llvm/test/Analysis/BranchProbabilityInfo/loop.ll
M llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/arith-widening.ll
M llvm/test/Analysis/CostModel/AArch64/div.ll
M llvm/test/Analysis/CostModel/AArch64/div_cte.ll
M llvm/test/Analysis/CostModel/AArch64/fshl.ll
M llvm/test/Analysis/CostModel/AArch64/fshr.ll
M llvm/test/Analysis/CostModel/AArch64/logicalop.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/rem.ll
M llvm/test/Analysis/CostModel/AMDGPU/div.ll
M llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll
M llvm/test/Analysis/CostModel/AMDGPU/fneg.ll
M llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll
M llvm/test/Analysis/CostModel/AMDGPU/mul.ll
M llvm/test/Analysis/CostModel/AMDGPU/rem.ll
M llvm/test/Analysis/CostModel/ARM/divrem.ll
M llvm/test/Analysis/CostModel/ARM/logicalop.ll
M llvm/test/Analysis/CostModel/PowerPC/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/arith-int.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/logicalop.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-phi-const.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
M llvm/test/Analysis/CostModel/SystemZ/divrem-pow2.ll
M llvm/test/Analysis/CostModel/SystemZ/intrinsic-cost-crash.ll
M llvm/test/Analysis/CostModel/SystemZ/logicalop.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
M llvm/test/Analysis/CostModel/X86/div-codesize.ll
M llvm/test/Analysis/CostModel/X86/div-latency.ll
M llvm/test/Analysis/CostModel/X86/div-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/div.ll
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Analysis/CostModel/X86/logicalop.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul-codesize.ll
M llvm/test/Analysis/CostModel/X86/mul-latency.ll
M llvm/test/Analysis/CostModel/X86/mul-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/mul.ll
M llvm/test/Analysis/CostModel/X86/rem-codesize.ll
M llvm/test/Analysis/CostModel/X86/rem-latency.ll
M llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/rem.ll
M llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll
M llvm/test/Analysis/CostModel/X86/vdiv-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
M llvm/test/Analysis/CycleInfo/basic.ll
M llvm/test/Analysis/CycleInfo/unreachable-predecessor.ll
M llvm/test/Analysis/Delinearization/type_mismatch.ll
M llvm/test/Analysis/Delinearization/undef.ll
M llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
M llvm/test/Analysis/DemandedBits/vectors.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
M llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll
M llvm/test/Analysis/Dominators/basic.ll
M llvm/test/Analysis/Dominators/print-dot-dom.ll
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
M llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
M llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll
M llvm/test/Analysis/MemorySSA/cyclicphi.ll
M llvm/test/Analysis/MemorySSA/debugvalue.ll
M llvm/test/Analysis/MemorySSA/debugvalue2.ll
M llvm/test/Analysis/MemorySSA/forward-unreachable.ll
M llvm/test/Analysis/MemorySSA/function-clobber.ll
M llvm/test/Analysis/MemorySSA/invariant-groups.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-disablebasicaa.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-simplified-clone.ll
M llvm/test/Analysis/MemorySSA/loop-rotate-valuemap.ll
M llvm/test/Analysis/MemorySSA/phi-translation.ll
M llvm/test/Analysis/MemorySSA/pr28880.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr41640.ll
M llvm/test/Analysis/MemorySSA/pr41853.ll
M llvm/test/Analysis/MemorySSA/pr42940.ll
M llvm/test/Analysis/MemorySSA/pr43317.ll
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M llvm/test/Analysis/MemorySSA/pr43427.ll
M llvm/test/Analysis/MemorySSA/pr43438.ll
M llvm/test/Analysis/MemorySSA/pr43493.ll
M llvm/test/Analysis/MemorySSA/pr43541.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr45976.ll
M llvm/test/Analysis/MemorySSA/reduce_clobber_limit.ll
M llvm/test/Analysis/MemorySSA/renamephis.ll
M llvm/test/Analysis/MemorySSA/unreachable.ll
M llvm/test/Analysis/MemorySSA/update_unroll.ll
M llvm/test/Analysis/PhiValues/basic.ll
M llvm/test/Analysis/PhiValues/long_phi_chain.ll
M llvm/test/Analysis/PostDominators/pr6047_a.ll
M llvm/test/Analysis/PostDominators/pr6047_b.ll
M llvm/test/Analysis/PostDominators/pr6047_c.ll
M llvm/test/Analysis/PostDominators/pr6047_d.ll
M llvm/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
M llvm/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll
M llvm/test/Analysis/ScalarEvolution/avoid-infinite-recursion-1.ll
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M llvm/test/Analysis/ScalarEvolution/expander-replace-congruent-ivs.ll
M llvm/test/Analysis/ScalarEvolution/how-far-to-zero.ll
M llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/pointer-sign-bits.ll
M llvm/test/Analysis/ScalarEvolution/pr22674.ll
M llvm/test/Analysis/ScalarEvolution/pr22856.ll
M llvm/test/Analysis/ScalarEvolution/pr25369.ll
M llvm/test/Analysis/ScalarEvolution/scev-aa.ll
M llvm/test/Analysis/ScalarEvolution/scev-canonical-mode.ll
M llvm/test/Analysis/ScalarEvolution/scev-invalid.ll
M llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll
M llvm/test/Analysis/ValueTracking/known-bits.ll
M llvm/test/Analysis/ValueTracking/known-fpclass.ll
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
M llvm/test/Analysis/ValueTracking/knownbits-and-or-xor-lowbit.ll
M llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll
M llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
M llvm/test/Analysis/ValueTracking/knownzero-shift.ll
M llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
M llvm/test/Analysis/ValueTracking/numsignbits-shl.ll
M llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll
M llvm/test/Assembler/ConstantExprFold.ll
M llvm/test/Assembler/atomicrmw.ll
A llvm/test/Assembler/c-style-comment.ll
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A llvm/test/Assembler/invalid-c-style-comment2.ll
A llvm/test/Assembler/invalid-c-style-comment3.ll
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M llvm/test/Assembler/target-type-param-errors.ll
M llvm/test/Bitcode/constantsTest.3.2.ll
M llvm/test/Bitcode/convergence-control.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
A llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
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M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/convertphitype.ll
M llvm/test/CodeGen/AArch64/double_reduct.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
A llvm/test/CodeGen/AArch64/latency.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
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M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
A llvm/test/CodeGen/AArch64/trunc-nsw-nuw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
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M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
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M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
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M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
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M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
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M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
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R llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
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A llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
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M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
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M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
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M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
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M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
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M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
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M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
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M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
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M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
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M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
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M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
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M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
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M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
A llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
R llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
A llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
A llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
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M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
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M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
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M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
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M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
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A llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
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A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
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A llvm/test/CodeGen/SystemZ/xray.ll
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A llvm/test/CodeGen/Thumb2/mve-vadc-vsbc-spill.ll
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A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
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M llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll
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M llvm/test/Transforms/AggressiveInstCombine/popcount.ll
M llvm/test/Transforms/AggressiveInstCombine/trunc_multi_uses.ll
M llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll
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M llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
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A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
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M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
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M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DivRemPairs/AMDGPU/div-rem-pairs.ll
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A llvm/test/Transforms/FunctionSpecialization/solver-dead-blocks.ll
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M llvm/test/Transforms/InferAddressSpaces/AMDGPU/infer-getelementptr.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
M llvm/test/Transforms/InferAddressSpaces/masked-gather-scatter.ll
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
M llvm/test/Transforms/InstCombine/2007-03-21-SignedRangeTest.ll
M llvm/test/Transforms/InstCombine/2008-01-21-MulTrunc.ll
M llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
M llvm/test/Transforms/InstCombine/2008-12-17-SRemNegConstVec.ll
M llvm/test/Transforms/InstCombine/AArch64/2012-04-23-Neon-Intrinsics.ll
M llvm/test/Transforms/InstCombine/AArch64/aes-intrinsics.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/ARM/2012-04-23-Neon-Intrinsics.ll
M llvm/test/Transforms/InstCombine/ARM/aes-intrinsics.ll
M llvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll
M llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll
M llvm/test/Transforms/InstCombine/X86/x86-movmsk.ll
M llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-muldq.ll
M llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-pack.ll
M llvm/test/Transforms/InstCombine/X86/x86-pmulh.ll
M llvm/test/Transforms/InstCombine/X86/x86-pmulhrs.ll
M llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-xop.ll
M llvm/test/Transforms/InstCombine/abs-1.ll
M llvm/test/Transforms/InstCombine/abs-intrinsic.ll
M llvm/test/Transforms/InstCombine/add-mask-neg.ll
M llvm/test/Transforms/InstCombine/add-mask.ll
M llvm/test/Transforms/InstCombine/add-shl-sdiv-to-srem.ll
M llvm/test/Transforms/InstCombine/add-sitofp.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/add4.ll
M llvm/test/Transforms/InstCombine/add_or_sub.ll
M llvm/test/Transforms/InstCombine/addsub-constant-folding.ll
M llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
M llvm/test/Transforms/InstCombine/and-compare.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/and-or-icmp-const-icmp.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/and-or-not.ll
M llvm/test/Transforms/InstCombine/and-or.ll
M llvm/test/Transforms/InstCombine/and-xor-or.ll
M llvm/test/Transforms/InstCombine/and.ll
M llvm/test/Transforms/InstCombine/and2.ll
M llvm/test/Transforms/InstCombine/apint-add.ll
M llvm/test/Transforms/InstCombine/apint-mul1.ll
M llvm/test/Transforms/InstCombine/apint-mul2.ll
M llvm/test/Transforms/InstCombine/apint-select.ll
M llvm/test/Transforms/InstCombine/apint-shift.ll
M llvm/test/Transforms/InstCombine/ashr-demand.ll
M llvm/test/Transforms/InstCombine/ashr-lshr.ll
M llvm/test/Transforms/InstCombine/avg-lsb.ll
M llvm/test/Transforms/InstCombine/binop-and-shifts.ll
M llvm/test/Transforms/InstCombine/binop-cast.ll
M llvm/test/Transforms/InstCombine/binop-of-displaced-shifts.ll
M llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll
M llvm/test/Transforms/InstCombine/binop-select.ll
M llvm/test/Transforms/InstCombine/bit-checks.ll
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/bit_floor.ll
M llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
M llvm/test/Transforms/InstCombine/bitcast.ll
M llvm/test/Transforms/InstCombine/bitreverse.ll
M llvm/test/Transforms/InstCombine/bswap-fold.ll
M llvm/test/Transforms/InstCombine/bswap.ll
M llvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
M llvm/test/Transforms/InstCombine/canonicalize-clamp-like-pattern-between-negative-and-positive-thresholds.ll
M llvm/test/Transforms/InstCombine/canonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
M llvm/test/Transforms/InstCombine/canonicalize-lack-of-signed-truncation-check.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
M llvm/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll
M llvm/test/Transforms/InstCombine/canonicalize-signed-truncation-check.ll
M llvm/test/Transforms/InstCombine/canonicalize.ll
M llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
M llvm/test/Transforms/InstCombine/cast-int-icmp-eq-0.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
M llvm/test/Transforms/InstCombine/compare-signs.ll
M llvm/test/Transforms/InstCombine/compare-udiv.ll
M llvm/test/Transforms/InstCombine/consecutive-ptrmask.ll
M llvm/test/Transforms/InstCombine/copysign-fneg-fabs.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll
M llvm/test/Transforms/InstCombine/ctpop-cttz.ll
M llvm/test/Transforms/InstCombine/ctpop-pow2.ll
M llvm/test/Transforms/InstCombine/ctpop.ll
M llvm/test/Transforms/InstCombine/demorgan.ll
M llvm/test/Transforms/InstCombine/dependent-ivs.ll
M llvm/test/Transforms/InstCombine/div-shift.ll
M llvm/test/Transforms/InstCombine/div.ll
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
M llvm/test/Transforms/InstCombine/exact.ll
M llvm/test/Transforms/InstCombine/exp2-1.ll
M llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fabs-copysign.ll
M llvm/test/Transforms/InstCombine/fabs-fneg-fold.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/fast-math.ll
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
Log Message:
-----------
rebase
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/66939f5f43f5...822ff0d8a449
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