[all-commits] [llvm/llvm-project] c93eb4: [lldb] Fix TestFileHandle.lua

[Amir Ayupov via All-commits]

  Branch: refs/heads/users/shawbyoung/spr/bolt-match-blocks-with-pseudo-probes
  Home:   https://github.com/llvm/llvm-project
  Commit: c93eb43a63d3b5c90e828608b5c2063644a3b161
      https://github.com/llvm/llvm-project/commit/c93eb43a63d3b5c90e828608b5c2063644a3b161
  Author: Jonas Devlieghere <jonas at devlieghere.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M lldb/test/API/lua_api/TestFileHandle.lua

  Log Message:
  -----------
  [lldb] Fix TestFileHandle.lua

 - Explicitly create an `SBFile`.
 - Add missing call to `close`.
 - Use `SetErrorFile` in TestLegacyFileErr.


  Commit: e734de1f5a3c2ec0c88221eb0991b0922e30d902
      https://github.com/llvm/llvm-project/commit/e734de1f5a3c2ec0c88221eb0991b0922e30d902
  Author: Fabian Ritter <fabian.ritter at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/docs/AMDGPUSupport.rst
    M clang/docs/HIPSupport.rst
    M clang/include/clang/Basic/MacroBuilder.h
    M clang/lib/Basic/Targets/AMDGPU.cpp
    R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip

  Log Message:
  -----------
  Revert "[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros" (#115499)

Reverts llvm/llvm-project#112849 due to test failure on Mac, reported by
@nico


  Commit: 6737ba40406030cd8a7ea706cd56302f8be7a4b4
      https://github.com/llvm/llvm-project/commit/6737ba40406030cd8a7ea706cd56302f8be7a4b4
  Author: Haojian Wu <hokein.wu at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/include/clang/Basic/AttrDocs.td

  Log Message:
  -----------
  Update the lifetimebound doc.

The lifetimebound attr is not C++ only anymore after 8b29c05b73310bba3d7abd007dbbd839c46b0ab4


  Commit: c9552283c0bf277eba490cde9fd913510f4111c0
      https://github.com/llvm/llvm-project/commit/c9552283c0bf277eba490cde9fd913510f4111c0
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/lib/Headers/mmintrin.h
    M clang/test/CodeGen/X86/builtin_test_helpers.h
    M clang/test/CodeGen/X86/mmx-builtins.c

  Log Message:
  -----------
  [clang][x86] Add constexpr support for MMX _mm_set*_pi* intrinsics


  Commit: 2407ff4645e9124507a4b5d910603ff7fc9e5734
      https://github.com/llvm/llvm-project/commit/2407ff4645e9124507a4b5d910603ff7fc9e5734
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/lib/Headers/emmintrin.h
    M clang/test/CodeGen/X86/sse2-builtins.c

  Log Message:
  -----------
  [clang][x86] Add constexpr support for _mm_movpi64_epi64


  Commit: 51e8f822f39174eaf83b1d5798de329518970b02
      https://github.com/llvm/llvm-project/commit/51e8f822f39174eaf83b1d5798de329518970b02
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/X86/pr62014.ll

  Log Message:
  -----------
  [X86] pr62014.ll - regenerate test checks with vpternlog comments


  Commit: 71f82bba35c48eaf98c50aeeb4d2675156681c02
      https://github.com/llvm/llvm-project/commit/71f82bba35c48eaf98c50aeeb4d2675156681c02
  Author: Kazu Hirata <kazu at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

  Log Message:
  -----------
  [SPIRV] Use heterogenous lookups with std::map (NFC) (#115425)

Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.


  Commit: 6ce44266fc2d06dfcbefd8146279473ccada52ca
      https://github.com/llvm/llvm-project/commit/6ce44266fc2d06dfcbefd8146279473ccada52ca
  Author: Kazu Hirata <kazu at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/include/mlir/IR/DialectRegistry.h
    M mlir/lib/IR/Dialect.cpp

  Log Message:
  -----------
  [mlir] Use heterogenous lookups with std::map (NFC) (#115426)

Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.


  Commit: a4819d6aa30f849770c258abba67a4b721642ebf
      https://github.com/llvm/llvm-project/commit/a4819d6aa30f849770c258abba67a4b721642ebf
  Author: Kazu Hirata <kazu at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/lib/IR/MLIRContext.cpp

  Log Message:
  -----------
  [mlir] Simplify code with StringMap::operator[] (NFC) (#115427)


  Commit: bc7e5c2016e287b768d2a3a1de15f6bb644622ae
      https://github.com/llvm/llvm-project/commit/bc7e5c2016e287b768d2a3a1de15f6bb644622ae
  Author: Kazu Hirata <kazu at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

  Log Message:
  -----------
  [SLP] Avoid repeated hash lookups (NFC) (#115428)


  Commit: 2f243a5fb754c3688dfa225ce8073a281bca1a24
      https://github.com/llvm/llvm-project/commit/2f243a5fb754c3688dfa225ce8073a281bca1a24
  Author: Haojian Wu <hokein.wu at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [bazel] Port for 0e39b1348e5fcadb129a6f113e5d708a526d8faa


  Commit: 3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
      https://github.com/llvm/llvm-project/commit/3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-11-09 (Sat, 09 Nov 2024)

  Changed paths:
    M llvm/test/tools/llvm-reduce/reduce-flags.ll
    M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp

  Log Message:
  -----------
  [llvm-reduce] Reduce samesign flag from icmp (#115492)


  Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
      https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
  Author: David Green <david.green at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
    M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll

  Log Message:
  -----------
  [AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)

We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
  `fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
  `fma extract(Rn, 0), Rm, Ra -> fmadd`

The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
  `fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
  `fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`


  Commit: 4027400d2ceefb5ce68d4508e5f30dc40c4f535b
      https://github.com/llvm/llvm-project/commit/4027400d2ceefb5ce68d4508e5f30dc40c4f535b
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/docs/LanguageExtensions.rst
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/lib/Sema/SemaType.cpp
    A clang/test/C/C2y/n3342.c
    M clang/test/Misc/warning-flags.c
    M clang/test/Sema/declspec.c
    M clang/www/c_status.html

  Log Message:
  -----------
  [C2y] Add test coverage and documentation for WG14 N3342 (#115494)

This paper made qualified function types implementation-defined. We have
always supported this as an extension, so now we're documenting our
behavior.

Note, we still warn about this by default even in C2y mode because a
qualified function type is a sign of programmer confusion.


  Commit: f756d38abf2ec40ee06ee5aa668db444e5d6f485
      https://github.com/llvm/llvm-project/commit/f756d38abf2ec40ee06ee5aa668db444e5d6f485
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/test/C/C2y/n3342.c

  Log Message:
  -----------
  Fix failing test bot

Fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11191


  Commit: e5e15f9128b69f77668465b715b7984b8d5ad75a
      https://github.com/llvm/llvm-project/commit/e5e15f9128b69f77668465b715b7984b8d5ad75a
  Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M .github/CODEOWNERS

  Log Message:
  -----------
  add QuietMisdreavus to Clang/ExtractAPI code owners (#115206)

Adding myself to the ExtractAPI code owners listing so i can participate
in code reviews.


  Commit: 19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
      https://github.com/llvm/llvm-project/commit/19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
    M llvm/test/CodeGen/X86/vector-sext.ll

  Log Message:
  -----------
  [X86] combineToExtendBoolVectorInReg - use broadcast on AVX2+ targets

Make use of AVX2 broadcasts to splat the source integer across all lanes to simplify the per-lane byte shuffles.

Prep work to avoid a regression in the fix for #66150


  Commit: 79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
      https://github.com/llvm/llvm-project/commit/79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86] combineToExtendBoolVectorInReg - use SelectionDAG::getSplat helper instead of shuffle(scalar_to_vector(x))


  Commit: 92e0fb0c944254312d7b9c6ca64a026643617f60
      https://github.com/llvm/llvm-project/commit/92e0fb0c944254312d7b9c6ca64a026643617f60
  Author: Stephen Tozer <stephen.tozer at sony.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Utils/LoopUnroll.cpp
    A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll

  Log Message:
  -----------
  [DebugInfo][LoopUnroll] Preserve DebugLocs on optimized cond branches (#114225)

This patch fixes a simple error where as part of loop unrolling we
optimize conditional loop-exiting branches into unconditional branches
when we know that they will or won't exit the loop, but does not
propagate the source location of the original branch to the new one.

Found using https://github.com/llvm/llvm-project/pull/107279.


  Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
      https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt

  Log Message:
  -----------
  [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)

Fixes 2 old TODOs


  Commit: b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
      https://github.com/llvm/llvm-project/commit/b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp

  Log Message:
  -----------
  [StructurizeCFG] Remove one SSAUpdater::AddAvailableValue. NFCI. (#115472)


  Commit: 39358f846d1e336def88ff9c25581fab392d59fe
      https://github.com/llvm/llvm-project/commit/39358f846d1e336def88ff9c25581fab392d59fe
  Author: stefankoncarevic <skoncare at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
    M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
    M mlir/test/Dialect/Linalg/named-ops.mlir

  Log Message:
  -----------
  [mlir][linalg] Add Grouped Convolution Ops: conv_2d_nhwgc_gfhwc and conv_2d_nhwgc_gfhwc_q (#108192)

This patch adds two new ops: linalg::Conv2DNhwgcGfhwcOp and
linalg::Conv2DNhwgcGfhwcQOp, and uses them to convert tosa group conv2d
Ops.
- Added linalg::Conv2DNhwgcGfhwcOp and linalg::Conv2DNhwgcGfhwcQOp.
- Updated the conversion process to use these new ops for tosa group
conv2d operations.


  Commit: c3c2f46f7bd5891af13fef56a8754007f11ff6c1
      https://github.com/llvm/llvm-project/commit/c3c2f46f7bd5891af13fef56a8754007f11ff6c1
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    A clang/test/C/C2y/n3346.c
    M clang/www/c_status.html

  Log Message:
  -----------
  [C2y] Claim conformance and add test coverage for WG14 N3346 (#115516)

This converts some undefined behaviors during initialization to instead
be constraint violations. Clang has always implemented these as
constraints, so no compiler changes were needed.


  Commit: f7eba08497a2a46f2c10737a110f6b778faf1615
      https://github.com/llvm/llvm-project/commit/f7eba08497a2a46f2c10737a110f6b778faf1615
  Author: Antonio Frighetto <me at antoniofrighetto.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/ObjectYAML/ELFEmitter.cpp

  Log Message:
  -----------
  [ObjectYAML][ELF] Fix misspelling in `Elf_Verdaux` var name (NFC)


  Commit: 60972a893e2bf915f6ff043c9396dea9619456fb
      https://github.com/llvm/llvm-project/commit/60972a893e2bf915f6ff043c9396dea9619456fb
  Author: Antonio Frighetto <me at antoniofrighetto.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/include/llvm/ObjectYAML/ELFYAML.h
    M llvm/lib/ObjectYAML/ELFEmitter.cpp
    M llvm/lib/ObjectYAML/ELFYAML.cpp
    M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
    M llvm/tools/obj2yaml/elf2yaml.cpp

  Log Message:
  -----------
  [ObjectYAML][ELF] Allow verdaux entry offset to be user-defined


  Commit: b85e5b49d3efc37e837757a5154884648dc57113
      https://github.com/llvm/llvm-project/commit/b85e5b49d3efc37e837757a5154884648dc57113
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/test/C/C2y/n3346.c

  Log Message:
  -----------
  Speculatively fix test bots

This should address the issues found by:
https://lab.llvm.org/buildbot/#/builders/12/builds/9226
https://lab.llvm.org/buildbot/#/builders/140/builds/10487
https://lab.llvm.org/buildbot/#/builders/27/builds/1752


  Commit: d30a6dcfa06196dd98fc898219eb12bab04a56de
      https://github.com/llvm/llvm-project/commit/d30a6dcfa06196dd98fc898219eb12bab04a56de
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll

  Log Message:
  -----------
  [AMDGPU] Reorganize tests to unblock #112403 (#115503)

We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the `[15 x i32]` arguments to
`[13 x i32]` to bypass the issue.


  Commit: e215a1e27d84adad2635a52393621eb4fa439dc9
      https://github.com/llvm/llvm-project/commit/e215a1e27d84adad2635a52393621eb4fa439dc9
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/always-uniform.ll
    M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
    M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
    A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
    M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
    M llvm/test/CodeGen/AMDGPU/andorbitset.ll
    M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
    M llvm/test/CodeGen/AMDGPU/anyext.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
    M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
    M llvm/test/CodeGen/AMDGPU/bfm.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
    M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
    M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
    M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
    M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
    M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/ctpop64.ll
    M llvm/test/CodeGen/AMDGPU/cttz.ll
    M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
    M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
    M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
    M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
    M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2.ll
    M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
    M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
    M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
    M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fabs.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.ll
    M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
    M llvm/test/CodeGen/AMDGPU/fma-combine.ll
    M llvm/test/CodeGen/AMDGPU/fma.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
    M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/fp-classify.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
    M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
    M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
    M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
    M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
    M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
    M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
    M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/global_smrd.ll
    M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/imm.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
    M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
    M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
    M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
    M llvm/test/CodeGen/AMDGPU/loop_break.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
    M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
    M llvm/test/CodeGen/AMDGPU/max.i16.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/omod.ll
    M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
    M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/permute.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
    M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/rotl.ll
    M llvm/test/CodeGen/AMDGPU/rotr.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
    M llvm/test/CodeGen/AMDGPU/sad.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
    M llvm/test/CodeGen/AMDGPU/sign_extend.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
    M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/smrd.ll
    M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
    M llvm/test/CodeGen/AMDGPU/spill-m0.ll
    M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/sub.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store.ll
    M llvm/test/CodeGen/AMDGPU/trunc.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/uaddo.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
    M llvm/test/CodeGen/AMDGPU/uniform-select.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/usubo.ll
    M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_pack.ll
    M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
    M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/vselect.ll
    M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/xor.ll
    M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected

  Log Message:
  -----------
  [AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)


  Commit: 4661467003e7bc7f9bb89ab581517617d2a36c62
      https://github.com/llvm/llvm-project/commit/4661467003e7bc7f9bb89ab581517617d2a36c62
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/docs/LanguageExtensions.rst
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Sema/SemaDecl.cpp
    A clang/test/C/C2y/n3341.c
    M clang/www/c_status.html

  Log Message:
  -----------
  [C2y] Add test coverage and documentation for WG14 N3341 (#115478)

This paper made empty structures and unions implementation-defined. We
have always supported this as a GNU extension, so now we're documenting
our behavior and removing the extension warning in C2y mode.


  Commit: b70d1302cf2edaf95817a90f161691c684945273
      https://github.com/llvm/llvm-project/commit/b70d1302cf2edaf95817a90f161691c684945273
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/test/C/C2y/n3346.c

  Log Message:
  -----------
  Another speculative fix for WG14 N3346

This time it's for builders that don't default to C11 or later, such as:
https://lab.llvm.org/buildbot/#/builders/144/builds/11201


  Commit: 2808f05e83643b3d5ef128340f6f4da994ed71e3
      https://github.com/llvm/llvm-project/commit/2808f05e83643b3d5ef128340f6f4da994ed71e3
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/test/C/C2y/n3341.c

  Log Message:
  -----------
  Update test case for bots which don't default to C17


  Commit: 17f3e00911b860d535f41185e605c47babcc2039
      https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll

  Log Message:
  -----------
  Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"

The increase in fallbacks that was previously reported were not caused
by this change.

Original description:

This matches InstCombine and DAGCombine.

RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.

Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.


  Commit: e4d57d6a729fd955ccbdd8834065356f26284f3d
      https://github.com/llvm/llvm-project/commit/e4d57d6a729fd955ccbdd8834065356f26284f3d
  Author: erichkeane <ekeane at nvidia.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/include/clang/AST/StmtOpenACC.h
    M clang/include/clang/Sema/SemaOpenACC.h
    M clang/lib/AST/StmtOpenACC.cpp
    M clang/lib/AST/TextNodeDumper.cpp
    M clang/lib/Sema/SemaOpenACC.cpp
    M clang/lib/Serialization/ASTReaderStmt.cpp
    M clang/lib/Serialization/ASTWriterStmt.cpp
    M clang/test/SemaOpenACC/compute-construct-default-clause.c
    M clang/test/SemaOpenACC/compute-construct-if-clause.c
    M clang/test/SemaOpenACC/loop-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp

  Log Message:
  -----------
  [OpenACC] Remove 'loop' link to parent construct

After implementing 'loop', we determined that the link to its parent
only ever uses the type, not the construct itself. This patch removes
it, as it is both a waste and causes problems with serialization.


  Commit: e53c46a9084caac115d7f694e5f16f904b0d7124
      https://github.com/llvm/llvm-project/commit/e53c46a9084caac115d7f694e5f16f904b0d7124
  Author: Csanád Hajdú <csanad.hajdu at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
    A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll

  Log Message:
  -----------
  [Statepoint] Treat result of atomicrmw xchg as a base pointer (#97280)

Atomic RMW Xchg wasn't handled before when searching for known base
pointers in the IR.


  Commit: 40740c4494d971ce410e2051b8d3ea7bbe081c76
      https://github.com/llvm/llvm-project/commit/40740c4494d971ce410e2051b8d3ea7bbe081c76
  Author: Siddhesh Deodhar <153800103+siddhesh195 at users.noreply.github.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
    M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
    A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir

  Log Message:
  -----------
  Fix crash when using when using --finalize-memref-to-llvm (#112433)

This patch fixes crash when attempting to convert uint to int address
space during finalize-memref-to-llvm by doing the following:

1. Add a check to verify that IntegerAttr is signed int before calling
IntegerAttr::getInt()
 2. Emit error when getMemRefAddressSpace returns a failure()

Closes  #111242

---------

Co-authored-by: Christian Ulmann <christianulmann at gmail.com>


  Commit: 2b885f056585f82903f067840e54557a5b444b65
      https://github.com/llvm/llvm-project/commit/2b885f056585f82903f067840e54557a5b444b65
  Author: Aaron Ballman <aaron at aaronballman.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/test/C/C2y/n3346.c

  Log Message:
  -----------
  Fix test for bots that don't default to C17


  Commit: a749c98b49dc9a3863b685212d70be98b4f189c3
      https://github.com/llvm/llvm-project/commit/a749c98b49dc9a3863b685212d70be98b4f189c3
  Author: weiwei chen <weiwei.chen at modular.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel

  Log Message:
  -----------
  [Baze] Add missing lldbDataFormatter.py back to BUILD.bazel. (#115519)

- [x] Add `utils/lldbDataFormatters.py` back.


  Commit: fe5a64d1160209f22624b112b2629b0d6c4bb264
      https://github.com/llvm/llvm-project/commit/fe5a64d1160209f22624b112b2629b0d6c4bb264
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M flang/include/flang/Parser/dump-parse-tree.h
    M flang/include/flang/Parser/parse-tree.h
    M flang/lib/Parser/program-parsers.cpp
    M flang/lib/Parser/unparse.cpp
    M flang/lib/Semantics/expression.cpp
    M flang/test/Parser/cuf-sanity-common
    M flang/test/Parser/cuf-sanity-tree.CUF
    M flang/test/Parser/cuf-sanity-unparse.CUF

  Log Message:
  -----------
  [fang][cuda] Allow * in call chevron syntax (#115381)

Using `*` in call chevron syntax should be allowed. This patch updates
the parser to allow this usage.

```
call sub<<<*,nbBlock>>>()
```


  Commit: 86405ed1012c97b063cbde12350fdea141e1ab78
      https://github.com/llvm/llvm-project/commit/86405ed1012c97b063cbde12350fdea141e1ab78
  Author: Stephen Tozer <stephen.tozer at sony.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Scalar/Reassociate.cpp
    A llvm/test/Transforms/Reassociate/preserve-debugloc.ll

  Log Message:
  -----------
  [DebugInfo][Reassociate] Preserve DebugLocs when reassociating subs (#114226)

In NegateValue in Reassociate, we return the negation of an existing
value in order to break a subtract into an negate + add, potentially
creating a new instruction to perform the negation, but we neglect to
propagate the DebugLoc of the sub being replaced to the negate
instruction if one is created. This patch adds that propagation.

Found using https://github.com/llvm/llvm-project/pull/107279.


  Commit: 40e545098e8bb5a18988316331e46c4557378afa
      https://github.com/llvm/llvm-project/commit/40e545098e8bb5a18988316331e46c4557378afa
  Author: Shoaib Meenai <smeenai at fb.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/include/clang/CIR/CIRGenerator.h
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    M clang/lib/CIR/CodeGen/CIRGenModule.h
    M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
    M clang/lib/CIR/CodeGen/CIRGenerator.cpp

  Log Message:
  -----------
  [clang][CIR] Move CIRGen types into clang::CIRGen (#115385)

https://github.com/llvm/clangir/issues/1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.


  Commit: c72389d4feef9eafc902f99c41f85ed218b5bedf
      https://github.com/llvm/llvm-project/commit/c72389d4feef9eafc902f99c41f85ed218b5bedf
  Author: Shoaib Meenai <smeenai at fb.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    M clang/lib/CIR/CodeGen/CIRGenerator.cpp
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
    M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp

  Log Message:
  -----------
  [clang][CIR] Merge the mlir::cir namespace into cir (#115386)

https://github.com/llvm/clangir/issues/1025 discusses the motivation.
The mechanical parts of this change were done via:

find clang \( -name '*.h' -o -name '*.cpp' -o -name '*.td' \) -print0 |
xargs -0 perl -pi -e 's/mlir::cir/cir/g'
find clang \( -name '*.h' -o -name '*.cpp' \) -print0 | xargs -0 perl
-pi -e 's/::cir/cir/g'

There were some manual fixups and a clang-format run afterwards.


  Commit: 0dbdb3251fe1f276785015c1de3b0a1035c9de8f
      https://github.com/llvm/llvm-project/commit/0dbdb3251fe1f276785015c1de3b0a1035c9de8f
  Author: Pranav Kant <prka at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [bazel] Remove mlir-spirv-cpu-runner after 0e39b1348e5fcadb129a6f113e… (#115533)

…5d708a526d8faa


  Commit: e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
      https://github.com/llvm/llvm-project/commit/e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
  Author: Zequan Wu <zequanwu at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/lib/AST/Decl.cpp

  Log Message:
  -----------
  [clang] Avoid unnecessary call to clang::NamespaceDecl::isRedundantInlineQualifierFor(). (#115196)

We observed 2X slowdown in lldb's expression evaluation with
https://github.com/llvm/llvm-project/pull/109147 in some cases. It turns
out that calling `isRedundantInlineQualifierFor` is quite expensive.
Using short-circuit evaluation in the if statement to avoid unnecessary
calls to that function.


  Commit: 5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
      https://github.com/llvm/llvm-project/commit/5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCombine.td
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll

  Log Message:
  -----------
  [RISCV] Add sub_to_add to RISCVPostLegalizerCombiner.


  Commit: e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
      https://github.com/llvm/llvm-project/commit/e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
  Author: David Green <david.green at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

  Log Message:
  -----------
  [GlobalISel][AArch64] Allow vector ptr to int unmerges (#115228)

Vector pointer -> scalar integer unmerges are already legal. This
loosens the verifier check for vector-of-pointers -> vectors.


  Commit: a29e623e1257b100b507c592a405fee2e0ff34b9
      https://github.com/llvm/llvm-project/commit/a29e623e1257b100b507c592a405fee2e0ff34b9
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M compiler-rt/cmake/Modules/AddCompilerRT.cmake

  Log Message:
  -----------
  [compiler-rt] Make add_custom_libcxx() resilient to DESTDIR being set

If DESTDIR is set in the environment during the build/test stage, the
local libc++ installation will be installed under DESTDIR instead of being
in the build directory.

See https://github.com/llvm/llvm-project/pull/115077#issuecomment-2464640457
and https://gitlab.kitware.com/cmake/cmake/-/issues/18165.

Pull Request: https://github.com/llvm/llvm-project/pull/115525


  Commit: bbcd35270ef4597402b924d547d845893e7fd165
      https://github.com/llvm/llvm-project/commit/bbcd35270ef4597402b924d547d845893e7fd165
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/include/clang/Basic/arm_sve.td
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Basic/Targets/AArch64.h
    M clang/test/CodeGen/aarch64-fmv-dependencies.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
    M clang/test/Driver/aarch64-implied-sve-features.c
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
    M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64FMV.td
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
    M llvm/test/MC/AArch64/SVE2/aesd.s
    M llvm/test/MC/AArch64/SVE2/aese.s
    M llvm/test/MC/AArch64/SVE2/aesimc.s
    M llvm/test/MC/AArch64/SVE2/aesmc.s
    M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu.s
    M llvm/test/MC/AArch64/SVE2/pmullb-128.s
    M llvm/test/MC/AArch64/SVE2/pmullt-128.s
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (#115539)

…293)"

This reverts commit da9499ebfb323602c42aeb674571fe89cec20ca6.


  Commit: 6fb36f0bd0a34e6429960247cf088557ae7a6e96
      https://github.com/llvm/llvm-project/commit/6fb36f0bd0a34e6429960247cf088557ae7a6e96
  Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M flang/include/flang/Parser/parse-tree.h
    M flang/lib/Lower/OpenMP/Clauses.cpp

  Log Message:
  -----------
  [flang][OpenMP] Remove std::variant with single alternative, NFC


  Commit: 7dffc96a54f90569d6226dd5713c80fc8f30c76f
      https://github.com/llvm/llvm-project/commit/7dffc96a54f90569d6226dd5713c80fc8f30c76f
  Author: vporpo <vporpodas at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
    M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
    M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll

  Log Message:
  -----------
  [SandboxVec][BottomUpVec] Clean up dead instructions (#115267)

When scalars get replaced by vectors the original scalars may become
dead. In that case erase them.


  Commit: 144bdf3eb7128518ed162c5a168e3ec90922cd9e
      https://github.com/llvm/llvm-project/commit/144bdf3eb7128518ed162c5a168e3ec90922cd9e
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll

  Log Message:
  -----------
  [VPlan] Also check if plan for best legacy VF contains simplifications.

The plan for the VF chosen by the legacy cost model could also contain
additional simplifications that cause cost differences. Also check if it
contains simplifications.

Fixes https://github.com/llvm/llvm-project/issues/114860.


  Commit: db6f476e8e29c42691a3c3ea97d7230af2be5df8
      https://github.com/llvm/llvm-project/commit/db6f476e8e29c42691a3c3ea97d7230af2be5df8
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll

  Log Message:
  -----------
  AMDGPU: Use "countMaxActiveBits() <= 5" to define uint5Bits (#115543)

countMaxTrailingOnes() is not correct. This patch follows the suggestion
from https://github.com/llvm/llvm-project/pull/115372.


  Commit: 30ee3f4ec767f2f183d74eb949afa80b8b6261e2
      https://github.com/llvm/llvm-project/commit/30ee3f4ec767f2f183d74eb949afa80b8b6261e2
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll

  Log Message:
  -----------
  AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)


  Commit: 552f6fe4d503900cae7620f2ddfd7393be670d27
      https://github.com/llvm/llvm-project/commit/552f6fe4d503900cae7620f2ddfd7393be670d27
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir

  Log Message:
  -----------
  [RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (#115402)

We don't add a custom node for REMW as we can detect it with (srem
(sexti32), (sexti32)).


  Commit: dbad9412909a1879f29a4f717b2bf149c9a58369
      https://github.com/llvm/llvm-project/commit/dbad9412909a1879f29a4f717b2bf149c9a58369
  Author: Chinmay Deshpande <chdeshpa at amd.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/lib/Basic/Attributes.cpp

  Log Message:
  -----------
  [NFC][Clang] Use StringSwitch instead of array for parsing attribute scope (#115414)


  Commit: b99d4112585302cbd01f9b851a04adc6e4fb5218
      https://github.com/llvm/llvm-project/commit/b99d4112585302cbd01f9b851a04adc6e4fb5218
  Author: John Harrison <harjohn at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M lldb/tools/lldb-dap/Breakpoint.cpp
    M lldb/tools/lldb-dap/Breakpoint.h
    M lldb/tools/lldb-dap/BreakpointBase.cpp
    M lldb/tools/lldb-dap/BreakpointBase.h
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/DAPForward.h
    M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
    M lldb/tools/lldb-dap/ExceptionBreakpoint.h
    M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
    M lldb/tools/lldb-dap/FunctionBreakpoint.h
    M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
    M lldb/tools/lldb-dap/InstructionBreakpoint.h
    M lldb/tools/lldb-dap/JSONUtils.cpp
    M lldb/tools/lldb-dap/JSONUtils.h
    M lldb/tools/lldb-dap/SourceBreakpoint.cpp
    M lldb/tools/lldb-dap/SourceBreakpoint.h
    M lldb/tools/lldb-dap/Watchpoint.cpp
    M lldb/tools/lldb-dap/Watchpoint.h
    M lldb/tools/lldb-dap/lldb-dap.cpp

  Log Message:
  -----------
  [lldb-dap] Refactoring breakpoints to not use the `g_dap` reference. (#115208)

Refactoring breakpoints to not use the `g_dap` reference.

Instead, when a breakpoint is constructed it will be passed a DAP
reference that it should use for its lifetime.

This is part of a larger refactor to remove the global `g_dap` variable
to allow us to create multiple DAP instances.

---------

Co-authored-by: Pavel Labath <pavel at labath.sk>


  Commit: ca33649abe5fad93c57afef54e43ed9b3249cd86
      https://github.com/llvm/llvm-project/commit/ca33649abe5fad93c57afef54e43ed9b3249cd86
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/always-uniform.ll
    M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
    M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
    R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
    M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
    M llvm/test/CodeGen/AMDGPU/andorbitset.ll
    M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
    M llvm/test/CodeGen/AMDGPU/anyext.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
    M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
    M llvm/test/CodeGen/AMDGPU/bfi_int.ll
    M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
    M llvm/test/CodeGen/AMDGPU/bfm.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
    M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
    M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
    M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
    M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
    M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
    M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
    M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
    M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
    M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/ctpop64.ll
    M llvm/test/CodeGen/AMDGPU/cttz.ll
    M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
    M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
    M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
    M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
    M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
    M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
    M llvm/test/CodeGen/AMDGPU/ds_read2.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2.ll
    M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
    M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
    M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
    M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fabs.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.ll
    M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
    M llvm/test/CodeGen/AMDGPU/fma-combine.ll
    M llvm/test/CodeGen/AMDGPU/fma.ll
    M llvm/test/CodeGen/AMDGPU/fmax3.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
    M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/fp-classify.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
    M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
    M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fshr.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
    M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
    M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
    M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
    M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
    M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
    M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/global_smrd.ll
    M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/imm.ll
    M llvm/test/CodeGen/AMDGPU/imm16.ll
    M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
    M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
    M llvm/test/CodeGen/AMDGPU/kernel-args.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
    M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
    M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
    M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
    M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
    M llvm/test/CodeGen/AMDGPU/loop_break.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
    M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
    M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
    M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
    M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/madak.ll
    M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
    M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
    M llvm/test/CodeGen/AMDGPU/max.i16.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory_clause.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul_int24.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
    M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/omod.ll
    M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
    M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
    M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
    M llvm/test/CodeGen/AMDGPU/permute.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
    M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
    M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/rotl.ll
    M llvm/test/CodeGen/AMDGPU/rotr.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
    M llvm/test/CodeGen/AMDGPU/sad.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
    M llvm/test/CodeGen/AMDGPU/sign_extend.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
    M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/smrd.ll
    M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
    M llvm/test/CodeGen/AMDGPU/spill-m0.ll
    M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
    M llvm/test/CodeGen/AMDGPU/sub.ll
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
    M llvm/test/CodeGen/AMDGPU/trunc-store.ll
    M llvm/test/CodeGen/AMDGPU/trunc.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/uaddo.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
    M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
    M llvm/test/CodeGen/AMDGPU/uniform-select.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/usubo.ll
    M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/v_pack.ll
    M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
    M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
    M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/vselect.ll
    M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/xor.ll
    M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected

  Log Message:
  -----------
  Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.


  Commit: ccc9d7dc7af535aa240a96bc999911ee9ba2d534
      https://github.com/llvm/llvm-project/commit/ccc9d7dc7af535aa240a96bc999911ee9ba2d534
  Author: David Green <david.green at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/ptradd.ll

  Log Message:
  -----------
  [GlobalISel][AArch64] Update and extend ptradd.ll test. NFC

We can now support v4p0 pointers without running into verifier issues.


  Commit: 441b82b20bf3a622155354e17ae66e0ccff50796
      https://github.com/llvm/llvm-project/commit/441b82b20bf3a622155354e17ae66e0ccff50796
  Author: Ian Wood <ianwood2024 at u.northwestern.edu>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
    M mlir/test/Dialect/Vector/int-range-interface.mlir

  Log Message:
  -----------
  [mlir][NFC] IntegerRangeAnalysis: don't loop over splat attr (#115399)

Reland https://github.com/llvm/llvm-project/pull/115229 which was
reverted by https://github.com/llvm/llvm-project/pull/115388 because it
was hitting an assertion in IREE. From the original change: If the
`DenseIntElementsAttr` is a splat value, there is no need to loop over
the entire attr. Instead, just update with the splat value.


The problem with the original implementation is that `SplatElementsAttr`
might be an attr of non `APInt` (e.g. float) elements. Instead, check if
`DenseIntElementsAttr` is splat and use the splat value. Added a test to
ensure there's no crash when handling float attrs.


  Commit: 8a7a7b5ffc690bd012cf090d31d47ec938248ba3
      https://github.com/llvm/llvm-project/commit/8a7a7b5ffc690bd012cf090d31d47ec938248ba3
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlan.cpp

  Log Message:
  -----------
  [VPlan] Remove unneeded code connecting blocks in VPBB:splitAt (NFC).

insertBlockAfter already takes care of transferring successors. Remove
unneeded code to transfer them manually.


  Commit: 26a9f3f5906c62cff7f2245b98affa432b504a87
      https://github.com/llvm/llvm-project/commit/26a9f3f5906c62cff7f2245b98affa432b504a87
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

  Log Message:
  -----------
  [SLP][NFC]Cleanup getSameOpcode, return InstructionsState::invalid() for non-valid inputs

Just a cleanup and related changes


  Commit: 8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
      https://github.com/llvm/llvm-project/commit/8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
  Author: John Harrison <harjohn at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M lldb/tools/lldb-dap/JSONUtils.cpp

  Log Message:
  -----------
  [lldb-dap] Fix lldb-dap build for windows, missing PATH_MAX. (#115551)

This should fix https://lab.llvm.org/buildbot/#/builders/141/builds/3722


  Commit: 7a6a52a2f0c6af63f210562d4a0345232d30d54d
      https://github.com/llvm/llvm-project/commit/7a6a52a2f0c6af63f210562d4a0345232d30d54d
  Author: Jorge Gorbe Moya <jgorbe at google.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/SandboxIR/Instruction.cpp

  Log Message:
  -----------
  [SandboxIR] Remove incorrect assertion. (#115553)

`insertBefore` can be called on a detached instruction, and we can't
check that the underlying instructions are ordered because instructions
without BB parents have no order.

This problem showed up as a different assertion failure in
`llvm::Instruction::comesBefore` in one of the unit tests when
`EXPENSIVE_CHECKS` are enabled.


  Commit: fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
      https://github.com/llvm/llvm-project/commit/fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll

  Log Message:
  -----------
  [AMDGPU] Disable verifier in `call-args-inreg-no-sgpr-for-csrspill-xfail.ll`

Similar to f9bd083, this could fix expensive check failure.


  Commit: d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
      https://github.com/llvm/llvm-project/commit/d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
    M flang/test/Fir/CUDA/cuda-alloc-free.fir

  Log Message:
  -----------
  [flang][cuda] Support derived type in cuf.alloc (#115550)

Number of bytes to allocate was not computed when using `cuf.alloc` with
a derived type. Update the conversion to compute the number of bytes and
emit an error when type is not supported.


  Commit: 023483f5ba6bbbec64bb340578b00bfa3399691d
      https://github.com/llvm/llvm-project/commit/023483f5ba6bbbec64bb340578b00bfa3399691d
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M flang/test/Lower/CUDA/cuda-kernel-calls.cuf

  Log Message:
  -----------
  [flang][cuda][NFC] Add test for <<<*, block>>> lowering (#115534)

Chevron syntax has been update to allow `*` to be used for the grid
value. Make sure we set the three grid values to -1, 1, 1 in lowering.


  Commit: 6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
      https://github.com/llvm/llvm-project/commit/6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M flang/runtime/CUDA/kernel.cpp

  Log Message:
  -----------
  [flang][cuda] Compute grid x when calling a kernel with <<<*, block>>>  (#115538)

`-1, 1, 1` is passed when calling a kernel with the `<<<*, block>>>`
syntax. Query the device to compute the grid.x value.


  Commit: 50850bc78b00b991cb361cb94a151befd83f6a5d
      https://github.com/llvm/llvm-project/commit/50850bc78b00b991cb361cb94a151befd83f6a5d
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll

  Log Message:
  -----------
  [LV] Add test for preserving flags when widening casts; NFC


  Commit: 8af5ae0648f85b9196a794700ebe5468a0cefd6b
      https://github.com/llvm/llvm-project/commit/8af5ae0648f85b9196a794700ebe5468a0cefd6b
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll

  Log Message:
  -----------
  [VPlan] Preserve IR flags when widening casts

We have `nneg` for both `sext` and `uitofp`.

Fixes #114856

Closes #115373


  Commit: 738250989ce516f02f809bdfde474a039c77e81f
      https://github.com/llvm/llvm-project/commit/738250989ce516f02f809bdfde474a039c77e81f
  Author: Tom Stellard <tstellar at redhat.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M clang/utils/perf-training/bolt.lit.cfg
    M clang/utils/perf-training/bolt.lit.site.cfg.in
    M clang/utils/perf-training/lit.cfg
    M clang/utils/perf-training/lit.site.cfg.in
    A clang/utils/perf-training/llvm-support/build.test

  Log Message:
  -----------
  [Clang][perf-training] Do build of libLLVMSupport for perf training (#111625)

This adds a build of the libLLVMSupport to the lit suite that is used
for generating profile data. This helps to improve both PGO and BOLT
optimization of clang over the existing hello world training program.

I considered building all of LLVM instead of just libLLVMSupport, but
there is only a marginal increase in performance for PGO only builds
when training with a build of all of LLVM, and I didn't think it was
enough to justify the increased build times given that it is the default
configuration.

The benchmark[1] I did showed that using libLLVMSupport for training
gives a 1.35 +- 0.02 speed up for clang optimized with PGO + BOLT vs
just 1.05 +- 0.01 speed up when training with hello world.

For comparison, training with a full LLVM build gave a speed up of 1.35
+- 0.1.

Raw data:

| PGO Training | BOLT Training | Speed Up | Error Range |
| ------------ | ------------- | -------- | ----------- |
| LLVM Support | LLVM Support  | 1.35     | 0.02        |
| LLVM All     | LLVM All      | 1.34     | 0.01        |
| LLVM Support | Hello World   | 1.29     | 0.02        |
| LLVM All     | PGO-ONLY      | 1.27     | 0.02        |
| LLVM Support | PGO-ONLY      | 1.22     | 0.02        |
| Hello World  | Hello World   | 1.05     | 0.01        |
| Hello World  | PGO-ONLY      | 1.03     | 0.01        |

Time it takes to generate profile data (on a 64-core system):

| Training Data | PGO   | BOLT  |
| ------------- | ----- | ----- |
| LLVM All      | 1090s | 3239s |
| LLVM Support  |   91s |  655s |
| Hello World  |    2s |    9s |

[1] Benchmark was compiling SemaDecl.cpp


  Commit: d936924f5e22e8efbc27873f62e8dfc6e410fcf9
      https://github.com/llvm/llvm-project/commit/d936924f5e22e8efbc27873f62e8dfc6e410fcf9
  Author: Amir Ayupov <aaupov at fb.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M bolt/include/bolt/Profile/YAMLProfileReader.h
    M bolt/lib/Profile/YAMLProfileReader.cpp

  Log Message:
  -----------
  [BOLT][NFC] Make YamlProfileToFunction a DenseMap (#108712)

YAML function profiles have sparse function IDs, assigned from
sequential function IDs from profiled binary. For example, for one large
binary, YAML profile has 15K functions, but the highest ID is ~600K,
close to number of functions in the profiled binary.

In `matchProfileToFunction`, `YamlProfileToFunction` vector was resized
to match function ID, which entails a 40X overcommit. Change the type of
`YamlProfileToFunction` to DenseMap to reduce memory utilization.

#99891 makes use of it for profile lookup associated with a given binary
function.


  Commit: 2502434bf541db29b813c355f1b679bd07f0def5
      https://github.com/llvm/llvm-project/commit/2502434bf541db29b813c355f1b679bd07f0def5
  Author: Amir Ayupov <aaupov at fb.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M .github/CODEOWNERS
    M clang/docs/AMDGPUSupport.rst
    M clang/docs/HIPSupport.rst
    M clang/docs/LanguageExtensions.rst
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/AST/StmtOpenACC.h
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Basic/MacroBuilder.h
    M clang/include/clang/Basic/arm_sve.td
    M clang/include/clang/CIR/CIRGenerator.h
    M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/include/clang/Sema/SemaOpenACC.h
    M clang/lib/AST/Decl.cpp
    M clang/lib/AST/StmtOpenACC.cpp
    M clang/lib/AST/TextNodeDumper.cpp
    M clang/lib/Basic/Attributes.cpp
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Basic/Targets/AArch64.h
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    M clang/lib/CIR/CodeGen/CIRGenModule.h
    M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
    M clang/lib/CIR/CodeGen/CIRGenerator.cpp
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
    M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
    M clang/lib/Headers/emmintrin.h
    M clang/lib/Headers/mmintrin.h
    M clang/lib/Sema/SemaDecl.cpp
    M clang/lib/Sema/SemaOpenACC.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/lib/Serialization/ASTReaderStmt.cpp
    M clang/lib/Serialization/ASTWriterStmt.cpp
    A clang/test/C/C2y/n3341.c
    A clang/test/C/C2y/n3342.c
    A clang/test/C/C2y/n3346.c
    M clang/test/CodeGen/X86/builtin_test_helpers.h
    M clang/test/CodeGen/X86/mmx-builtins.c
    M clang/test/CodeGen/X86/sse2-builtins.c
    M clang/test/CodeGen/aarch64-fmv-dependencies.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
    M clang/test/Driver/aarch64-implied-sve-features.c
    R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M clang/test/Misc/warning-flags.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
    M clang/test/Sema/declspec.c
    M clang/test/SemaOpenACC/compute-construct-default-clause.c
    M clang/test/SemaOpenACC/compute-construct-if-clause.c
    M clang/test/SemaOpenACC/loop-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
    M clang/utils/perf-training/bolt.lit.cfg
    M clang/utils/perf-training/bolt.lit.site.cfg.in
    M clang/utils/perf-training/lit.cfg
    M clang/utils/perf-training/lit.site.cfg.in
    A clang/utils/perf-training/llvm-support/build.test
    M clang/www/c_status.html
    M compiler-rt/cmake/Modules/AddCompilerRT.cmake
    M flang/include/flang/Parser/dump-parse-tree.h
    M flang/include/flang/Parser/parse-tree.h
    M flang/lib/Lower/OpenMP/Clauses.cpp
    M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
    M flang/lib/Parser/program-parsers.cpp
    M flang/lib/Parser/unparse.cpp
    M flang/lib/Semantics/expression.cpp
    M flang/runtime/CUDA/kernel.cpp
    M flang/test/Fir/CUDA/cuda-alloc-free.fir
    M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
    M flang/test/Parser/cuf-sanity-common
    M flang/test/Parser/cuf-sanity-tree.CUF
    M flang/test/Parser/cuf-sanity-unparse.CUF
    M lldb/test/API/lua_api/TestFileHandle.lua
    M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
    M lldb/tools/lldb-dap/Breakpoint.cpp
    M lldb/tools/lldb-dap/Breakpoint.h
    M lldb/tools/lldb-dap/BreakpointBase.cpp
    M lldb/tools/lldb-dap/BreakpointBase.h
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/DAPForward.h
    M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
    M lldb/tools/lldb-dap/ExceptionBreakpoint.h
    M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
    M lldb/tools/lldb-dap/FunctionBreakpoint.h
    M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
    M lldb/tools/lldb-dap/InstructionBreakpoint.h
    M lldb/tools/lldb-dap/JSONUtils.cpp
    M lldb/tools/lldb-dap/JSONUtils.h
    M lldb/tools/lldb-dap/SourceBreakpoint.cpp
    M lldb/tools/lldb-dap/SourceBreakpoint.h
    M lldb/tools/lldb-dap/Watchpoint.cpp
    M lldb/tools/lldb-dap/Watchpoint.h
    M lldb/tools/lldb-dap/lldb-dap.cpp
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/ObjectYAML/ELFYAML.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/ObjectYAML/ELFEmitter.cpp
    M llvm/lib/ObjectYAML/ELFYAML.cpp
    M llvm/lib/SandboxIR/Instruction.cpp
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64FMV.td
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVCombine.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/Scalar/Reassociate.cpp
    M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
    M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
    M llvm/lib/Transforms/Utils/LoopUnroll.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
    M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
    M llvm/test/CodeGen/X86/pr62014.ll
    M llvm/test/CodeGen/X86/vector-sext.ll
    M llvm/test/MC/AArch64/SVE2/aesd.s
    M llvm/test/MC/AArch64/SVE2/aese.s
    M llvm/test/MC/AArch64/SVE2/aesimc.s
    M llvm/test/MC/AArch64/SVE2/aesmc.s
    M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu.s
    M llvm/test/MC/AArch64/SVE2/pmullb-128.s
    M llvm/test/MC/AArch64/SVE2/pmullt-128.s
    A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
    A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
    A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
    A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
    A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
    M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
    M llvm/test/tools/llvm-reduce/reduce-flags.ll
    M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
    M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
    M llvm/tools/obj2yaml/elf2yaml.cpp
    M llvm/unittests/TargetParser/TargetParserTest.cpp
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
    M mlir/include/mlir/IR/DialectRegistry.h
    M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
    M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
    M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
    M mlir/lib/IR/Dialect.cpp
    M mlir/lib/IR/MLIRContext.cpp
    M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
    A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
    M mlir/test/Dialect/Linalg/named-ops.mlir
    M mlir/test/Dialect/Vector/int-range-interface.mlir
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]


  Commit: 956bcf22acb40e74ac5e0be244f4417635d39157
      https://github.com/llvm/llvm-project/commit/956bcf22acb40e74ac5e0be244f4417635d39157
  Author: Amir Ayupov <aaupov at fb.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M .github/CODEOWNERS
    M clang/docs/AMDGPUSupport.rst
    M clang/docs/HIPSupport.rst
    M clang/docs/LanguageExtensions.rst
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/AST/StmtOpenACC.h
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Basic/MacroBuilder.h
    M clang/include/clang/Basic/arm_sve.td
    M clang/include/clang/CIR/CIRGenerator.h
    M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/include/clang/Sema/SemaOpenACC.h
    M clang/lib/AST/Decl.cpp
    M clang/lib/AST/StmtOpenACC.cpp
    M clang/lib/AST/TextNodeDumper.cpp
    M clang/lib/Basic/Attributes.cpp
    M clang/lib/Basic/Targets/AArch64.cpp
    M clang/lib/Basic/Targets/AArch64.h
    M clang/lib/Basic/Targets/AMDGPU.cpp
    M clang/lib/CIR/CodeGen/CIRGenModule.cpp
    M clang/lib/CIR/CodeGen/CIRGenModule.h
    M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
    M clang/lib/CIR/CodeGen/CIRGenerator.cpp
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
    M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
    M clang/lib/Headers/emmintrin.h
    M clang/lib/Headers/mmintrin.h
    M clang/lib/Sema/SemaDecl.cpp
    M clang/lib/Sema/SemaOpenACC.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/lib/Serialization/ASTReaderStmt.cpp
    M clang/lib/Serialization/ASTWriterStmt.cpp
    A clang/test/C/C2y/n3341.c
    A clang/test/C/C2y/n3342.c
    A clang/test/C/C2y/n3346.c
    M clang/test/CodeGen/X86/builtin_test_helpers.h
    M clang/test/CodeGen/X86/mmx-builtins.c
    M clang/test/CodeGen/X86/sse2-builtins.c
    M clang/test/CodeGen/aarch64-fmv-dependencies.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
    M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
    M clang/test/Driver/aarch64-implied-sve-features.c
    R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
    M clang/test/Driver/print-supported-extensions-aarch64.c
    M clang/test/Misc/warning-flags.c
    M clang/test/Preprocessor/aarch64-target-features.c
    M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
    M clang/test/Sema/declspec.c
    M clang/test/SemaOpenACC/compute-construct-default-clause.c
    M clang/test/SemaOpenACC/compute-construct-if-clause.c
    M clang/test/SemaOpenACC/loop-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
    M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
    M clang/utils/perf-training/bolt.lit.cfg
    M clang/utils/perf-training/bolt.lit.site.cfg.in
    M clang/utils/perf-training/lit.cfg
    M clang/utils/perf-training/lit.site.cfg.in
    A clang/utils/perf-training/llvm-support/build.test
    M clang/www/c_status.html
    M compiler-rt/cmake/Modules/AddCompilerRT.cmake
    M flang/include/flang/Parser/dump-parse-tree.h
    M flang/include/flang/Parser/parse-tree.h
    M flang/lib/Lower/OpenMP/Clauses.cpp
    M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
    M flang/lib/Parser/program-parsers.cpp
    M flang/lib/Parser/unparse.cpp
    M flang/lib/Semantics/expression.cpp
    M flang/runtime/CUDA/kernel.cpp
    M flang/test/Fir/CUDA/cuda-alloc-free.fir
    M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
    M flang/test/Parser/cuf-sanity-common
    M flang/test/Parser/cuf-sanity-tree.CUF
    M flang/test/Parser/cuf-sanity-unparse.CUF
    M lldb/test/API/lua_api/TestFileHandle.lua
    M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
    M lldb/tools/lldb-dap/Breakpoint.cpp
    M lldb/tools/lldb-dap/Breakpoint.h
    M lldb/tools/lldb-dap/BreakpointBase.cpp
    M lldb/tools/lldb-dap/BreakpointBase.h
    M lldb/tools/lldb-dap/DAP.cpp
    M lldb/tools/lldb-dap/DAPForward.h
    M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
    M lldb/tools/lldb-dap/ExceptionBreakpoint.h
    M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
    M lldb/tools/lldb-dap/FunctionBreakpoint.h
    M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
    M lldb/tools/lldb-dap/InstructionBreakpoint.h
    M lldb/tools/lldb-dap/JSONUtils.cpp
    M lldb/tools/lldb-dap/JSONUtils.h
    M lldb/tools/lldb-dap/SourceBreakpoint.cpp
    M lldb/tools/lldb-dap/SourceBreakpoint.h
    M lldb/tools/lldb-dap/Watchpoint.cpp
    M lldb/tools/lldb-dap/Watchpoint.h
    M lldb/tools/lldb-dap/lldb-dap.cpp
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/ObjectYAML/ELFYAML.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/ObjectYAML/ELFEmitter.cpp
    M llvm/lib/ObjectYAML/ELFYAML.cpp
    M llvm/lib/SandboxIR/Instruction.cpp
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64FMV.td
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVCombine.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/Scalar/Reassociate.cpp
    M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
    M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
    M llvm/lib/Transforms/Utils/LoopUnroll.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
    M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
    M llvm/test/CodeGen/X86/pr62014.ll
    M llvm/test/CodeGen/X86/vector-sext.ll
    M llvm/test/MC/AArch64/SVE2/aesd.s
    M llvm/test/MC/AArch64/SVE2/aese.s
    M llvm/test/MC/AArch64/SVE2/aesimc.s
    M llvm/test/MC/AArch64/SVE2/aesmc.s
    M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
    M llvm/test/MC/AArch64/SVE2/directive-cpu.s
    M llvm/test/MC/AArch64/SVE2/pmullb-128.s
    M llvm/test/MC/AArch64/SVE2/pmullt-128.s
    A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
    A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
    A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
    A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
    A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
    M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
    M llvm/test/tools/llvm-reduce/reduce-flags.ll
    M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
    M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
    M llvm/tools/obj2yaml/elf2yaml.cpp
    M llvm/unittests/TargetParser/TargetParserTest.cpp
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
    M mlir/include/mlir/IR/DialectRegistry.h
    M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
    M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
    M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
    M mlir/lib/IR/Dialect.cpp
    M mlir/lib/IR/MLIRContext.cpp
    M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
    A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
    M mlir/test/Dialect/Linalg/named-ops.mlir
    M mlir/test/Dialect/Vector/int-range-interface.mlir
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  rebase

Created using spr 1.3.4


Compare: https://github.com/llvm/llvm-project/compare/e7bce6d392ba...956bcf22acb4

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications