[all-commits] [llvm/llvm-project] 552f6f: [RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV6...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 552f6fe4d503900cae7620f2ddfd7393be670d27
      https://github.com/llvm/llvm-project/commit/552f6fe4d503900cae7620f2ddfd7393be670d27
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir

  Log Message:
  -----------
  [RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (#115402)

We don't add a custom node for REMW as we can detect it with (srem
(sexti32), (sexti32)).



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications