[all-commits] [llvm/llvm-project] e109c4: Revert "Add clang::lifetimebound annotation to llv...
Shoaib Meenai via All-commits
all-commits at lists.llvm.org
Fri Nov 8 10:43:33 PST 2024
Branch: refs/heads/users/smeenai/2/head
Home: https://github.com/llvm/llvm-project
Commit: e109c493210572535de25950e7b83f74b8d11a6a
https://github.com/llvm/llvm-project/commit/e109c493210572535de25950e7b83f74b8d11a6a
Author: Pranav Kant <prka at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLFunctionalExtras.h
Log Message:
-----------
Revert "Add clang::lifetimebound annotation to llvm::function_ref (#1… (#115376)
…15019)"
This reverts commit 9f796159f28775b3f93d77e173c1fd3413c2e60e.
This is breaking compiler-rt/lib/sanitizer_common/...
Author knows about the breakage.
Commit: dec38399795a7f238508ee100e5b057165724a60
https://github.com/llvm/llvm-project/commit/dec38399795a7f238508ee100e5b057165724a60
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP][NFC]Add a test with the missed vectorization opportunity for stores with same address
Commit: ae9d0623ad65d84022bb4ed8446b6491451ae575
https://github.com/llvm/llvm-project/commit/ae9d0623ad65d84022bb4ed8446b6491451ae575
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as
fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as
fcvt.s.wu. There are still some regressions that suggest we should match
g_zero_extend in zexti32.
Commit: 7475156d49406785a974b1205d11fe3de9c1553e
https://github.com/llvm/llvm-project/commit/7475156d49406785a974b1205d11fe3de9c1553e
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
A clang/test/CodeGen/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
Log Message:
-----------
[Clang] Add __builtin_counted_by_ref builtin (#114495)
The __builtin_counted_by_ref builtin is used on a flexible array
pointer and returns a pointer to the "counted_by" attribute's COUNT
argument, which is a field in the same non-anonymous struct as the
flexible array member. This is useful for automatically setting the
count field without needing the programmer's intervention. Otherwise
it's possible to get this anti-pattern:
ptr = alloc(<ty>, ..., COUNT);
ptr->FAM[9] = 42; /* <<< Sanitizer will complain */
ptr->count = COUNT;
To prevent this anti-pattern, the user can create an allocator that
automatically performs the assignment:
#define alloc(TY, FAM, COUNT) ({ \
TY __p = alloc(get_size(TY, COUNT)); \
if (__builtin_counted_by_ref(__p->FAM)) \
*__builtin_counted_by_ref(__p->FAM) = COUNT; \
__p; \
})
The builtin's behavior is heavily dependent upon the "counted_by"
attribute existing. It's main utility is during allocation to avoid
the above anti-pattern. If the flexible array member doesn't have that
attribute, the builtin becomes a no-op. Therefore, if the flexible
array member has a "count" field not referenced by "counted_by", it
must be set explicitly after the allocation as this builtin will
return a "nullptr" and the assignment will most likely be elided.
---------
Co-authored-by: Bill Wendling <isanbard at gmail.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
https://github.com/llvm/llvm-project/commit/bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)
Enable pattern matching from "x<<32-y>>32-y" to "bfe x, 0, y" when we
know y is in [0,31].
This is the follow-up for the PR:
https://github.com/llvm/llvm-project/pull/114279 to fix the issue:
https://github.com/llvm/llvm-project/issues/114282
Commit: 62db1c8a076c7167e404412182f4a8915f4ff6ee
https://github.com/llvm/llvm-project/commit/62db1c8a076c7167e404412182f4a8915f4ff6ee
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP]Better decision making on whether to try stores packs for vectorization
Since the stores are sorted by distance, comparing the indices in the
original array and early exit, if the index is less than the index of
the last store, not always the best strategy. Better to remove such
stores explicitly to try better to check for the vectorization
opportunity.
Fixes #115008
Commit: c02da382471fd0b338af76ce220e9567e3cb854a
https://github.com/llvm/llvm-project/commit/c02da382471fd0b338af76ce220e9567e3cb854a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
Log Message:
-----------
[RISCV] Add tests for deinterleave(2-8) shuffles
Commit: 02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
https://github.com/llvm/llvm-project/commit/02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Match single source deinterleave shuffles for vnsrl (#114878)
We had previously only been matching the two source case where both
sources came from a wider source type. We can also match the single
source case - provided the result is m4 or smaller because we will need
a wider type to represent the source.
The main goal of this to ensure that vnsrl matching is robust to a
possible change in canonicalization for length changing shuffles that
I'm considering, but it has the nice effect of picking up a few cases we
missed along the way.
Commit: e189d61924ba0165b3a344c3d945b3e2aa373485
https://github.com/llvm/llvm-project/commit/e189d61924ba0165b3a344c3d945b3e2aa373485
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
A llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Add extractCallsFromIR (#115218)
This patch adds extractCallsFromIR, a function to extract calls from
the IR, which will be used to undrift call site locations in the
MemProf profile.
In a nutshell, the MemProf undrifting works as follows:
- Extract call site locations from the IR.
- Extract call site locations from the MemProf profile.
- Undrift the call site locations with longestCommonSequence.
This patch implements the first bullet point above. Specifically,
given the IR, the new function returns a map from caller GUIDs to
lists of corresponding call sites. For example:
Given:
foo() {
f1();
f2(); f3();
}
extractCallsFromIR returns:
Caller: foo ->
{{(Line 1, Column 3), Callee: f1},
{(Line 2, Column 3), Callee: f2},
{(Line 2, Column 9), Callee: f3}}
where the line numbers, relative to the beginning of the caller, and
column numbers are sorted in the ascending order. The value side of
the map -- the list of call sites -- can be directly passed to
longestCommonSequence.
To facilitate the review process, I've only implemented basic features
in extractCallsFromIR in this patch.
- The new function extracts calls from the LLVM "call" instructions
only. It does not look into the inline stack.
- It does not recognize or treat heap allocation functions in any
special way.
I will address these missing features in subsequent patches.
Commit: 53e49f15ab0b9b03e5671faea6f7870914b8f0ea
https://github.com/llvm/llvm-project/commit/53e49f15ab0b9b03e5671faea6f7870914b8f0ea
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
Log Message:
-----------
[clang][serialization] Pass `ASTContext` explicitly (#115235)
This patch removes `ASTWriter::Context` and starts passing `ASTContext
&` explicitly to functions that actually need it. This is a
non-functional change with the end-goal of being able to write
lightweight PCM files with no `ASTContext` at all.
Commit: fd799add2186356dc19e81106a1428a2edf7c20b
https://github.com/llvm/llvm-project/commit/fd799add2186356dc19e81106a1428a2edf7c20b
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
Log Message:
-----------
Reapply "[libc++abi] Stop copying headers to the build directory"
This was needed before https://github.com/llvm/llvm-project/pull/115077
since the compiler-rt test build made assumptions about the build
layout of libc++ and libc++abi, but now they link against a local
installation of these libraries so we no longer need this workaround.
The last attempt at landing this was reverted due to buildbot failures
which should be fixed by https://github.com/llvm/llvm-zorg/pull/299.
Pull Request: https://github.com/llvm/llvm-project/pull/115379
Commit: 3b1b1271fb552c996d9fdfa9a997f33013dd275f
https://github.com/llvm/llvm-project/commit/3b1b1271fb552c996d9fdfa9a997f33013dd275f
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
A llvm/test/CodeGen/Xtensa/branch-relaxation.ll
M llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
Log Message:
-----------
[Xtensa] Implement support for the BranchRelaxation. (#113450)
Commit: 49ee6069db372ce326bc36678e745459868c3771
https://github.com/llvm/llvm-project/commit/49ee6069db372ce326bc36678e745459868c3771
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/FunctionLayout.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/lib/Core/FunctionLayout.cpp
M bolt/lib/Passes/LongJmp.cpp
A bolt/test/AArch64/compact-code-model.s
Log Message:
-----------
[BOLT][AArch64] Add support for compact code model (#112110)
Add `--compact-code-model` option that executes alternative branch
relaxation with an assumption that the resulting binary has less than
128MB of code. The relaxation is done in `relaxLocalBranches()`, which
operates on a function level and executes on multiple functions in
parallel.
Running the new option on AArch64 Clang binary produces slightly smaller
code and the relaxation finishes in about 1/10th of the time.
Note that the new `.text` has to be smaller than 128MB, *and* `.plt` has
to be closer than 128MB to `.text`.
Commit: faefedf7f8d520035a7c699baa12d5bb9bb93f49
https://github.com/llvm/llvm-project/commit/faefedf7f8d520035a7c699baa12d5bb9bb93f49
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/exp10m1f.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/exp10m1f.cpp
M libc/src/math/generic/explogxf.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/exp10m1f_test.cpp
A libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10m1f_test.cpp
Log Message:
-----------
[libc][math][c23] Add exp10m1f C23 math function (#87992)
Fixes #86503.
Commit: accd8f98be29fb086d83cd318eeba8e491fcb799
https://github.com/llvm/llvm-project/commit/accd8f98be29fb086d83cd318eeba8e491fcb799
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
Log Message:
-----------
[BOLT] Fix a warning
This patch:
bolt/lib/Passes/LongJmp.cpp:830:14: error: variable 'NumIterations'
set but not used [-Werror,-Wunused-but-set-variable]
Commit: 1cb119b168a6d24f32b05de7f22c7a06a0f0c407
https://github.com/llvm/llvm-project/commit/1cb119b168a6d24f32b05de7f22c7a06a0f0c407
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Instrumentation/BUILD.gn
Log Message:
-----------
[gn build] Port e189d61924ba
Commit: d4525b016f5a1ab2852acb2108742b2f9d0bd3bd
https://github.com/llvm/llvm-project/commit/d4525b016f5a1ab2852acb2108742b2f9d0bd3bd
Author: Egor Zhdan <e_zhdan at apple.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/AST/TemplateArgumentVisitor.h
Log Message:
-----------
[Clang] Dispatch default overloads of `TemplateArgumentVisitor` to the implementation
This fixes an issue where overriding
`clang::ConstTemplateArgumentVisitor::VisitTemplateArgument` in an
implementation visitor class did not have the desired effect: the
overload was not invoked when one of the visitor methods (e.g.
`VisitDeclarationArgument`) is not implemented, instead it dispatched to
`clang::ConstTemplateArgumentVisitor::VisitTemplateArgument` itself and
always returned a default-initialized result.
This makes `TemplateArgumentVisitor` and `ConstTemplateArgumentVisitor`
follow the implicit convention that is followed elsewhere in Clang AST,
in `RecursiveASTVisitor` and `TypeVisitor`.
Commit: cd022b7b2aa9e4a5762c4e82e24b228114956e3b
https://github.com/llvm/llvm-project/commit/cd022b7b2aa9e4a5762c4e82e24b228114956e3b
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
Log Message:
-----------
Revert "[mlir] IntegerRangeAnalysis: don't loop over splat..." (#115388)
Hitting assertion in IREE
https://github.com/iree-org/iree/actions/runs/11732283897/job/32684201665?pr=19066
```
iree-compile: /__w/iree/iree/third_party/llvm-project/mlir/include/mlir/IR/BuiltinAttributes.h:423: auto mlir::DenseElementsAttr::getValues() const [T = llvm::APInt]: Assertion `succeeded(range) && "element type cannot be iterated"' failed.
```
Reverts llvm/llvm-project#115229
Commit: 5b697ef5dd6b3e29e257e6099014bf8d8e77ac9a
https://github.com/llvm/llvm-project/commit/5b697ef5dd6b3e29e257e6099014bf8d8e77ac9a
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir] Update CODEOWNERS file for vector dialect (#115398)
Adding myself to stay updated on patches since I have been reviewing /
upstreaming things related to vector dialect.
Commit: 74e6478f81b646f4bcaf6236161e54c7cb239874
https://github.com/llvm/llvm-project/commit/74e6478f81b646f4bcaf6236161e54c7cb239874
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/callcont-fallthru.s
Log Message:
-----------
[BOLT] Set call to continuation count in pre-aggregated profile
#109683 identified an issue with pre-aggregated profile where a call to
continuation fallthrough edge count is missing (profile discontinuity).
This issue only affects pre-aggregated profile but not perf data since
LBR stack has the necessary information to determine if the trace (fall-
through) starts at call continuation, whereas pre-aggregated fallthrough
lacks this information.
The solution is to look at branch records in pre-aggregated profiles
that correspond to returns and assign counts to call to continuation
fallthrough:
- BranchFrom is in another function or DSO,
- BranchTo may be a call continuation site:
- not an entry point/landing pad.
Note that we can't directly check if BranchFrom corresponds to a return
instruction if it's in external DSO.
Keep call continuation handling for perf data (`getFallthroughsInTrace`)
[1] as-is due to marginally better performance. The difference is that
return-converted call to continuation fallthrough is slightly more
frequent than other fallthroughs since the former only requires one LBR
address while the latter need two that belong to the profiled binary.
Hence return-converted fallthroughs have larger "weight" which affects
code layout.
[1] `DataAggregator::getFallthroughsInTrace`
https://github.com/llvm/llvm-project/blob/fea18afeed39fe4435d67eee1834f0f34b23013d/bolt/lib/Profile/DataAggregator.cpp#L906-L915
Test Plan: added callcont-fallthru.s
Reviewers: maksfb, ayermolo, ShatianWang, dcci
Reviewed By: maksfb, ShatianWang
Pull Request: https://github.com/llvm/llvm-project/pull/109486
Commit: 1ced07e06e23659a96dbf6d53cd68d3bbbe3d792
https://github.com/llvm/llvm-project/commit/1ced07e06e23659a96dbf6d53cd68d3bbbe3d792
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: XFAIL DWARFv4 variant on Darwin (#115401)
https://github.com/llvm/llvm-project/pull/111859 fixed these tests for
DWARFv4 on Linux by adjusting the manual index. As part of the change we
unXFAILed these tests for DWARFv4 on all platforms. However, the manual
index isn't used on macOS so they're still broken. This patch reverts
the XFAIL on Darwin for DWARFv4.
Example CI failure:
```
FAIL: test_inline_static_members_dwarf4_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 153, in test_inline_static_members_dwarf4
self.check_inline_static_members("-gdwarf-4")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
```
Commit: 74deb661dfa9301ec6fed46114e59317b1503ded
https://github.com/llvm/llvm-project/commit/74deb661dfa9301ec6fed46114e59317b1503ded
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CXX/temp/temp.res/p4.cpp
Log Message:
-----------
Revert "[Clang] skip default argument instantiation for non-defining friend declarations without specialization info to meet [dcl.fct.default] p4" (#115404)
Reverts llvm/llvm-project#113777
Reverted due to regression reported here:
https://github.com/llvm/llvm-project/pull/113777#issuecomment-2463465741
Commit: 037f8044f69f88101620707af1db948e6804e080
https://github.com/llvm/llvm-project/commit/037f8044f69f88101620707af1db948e6804e080
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
Log Message:
-----------
[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)
fcopysign takes two operands, one for the magnitude and exponent and the
other for the sign. The result type is determined by the magnitude and
exponent operand. The sign operand does not need to be the same type.
Note, in IR all 3 types must match.
We have isel patterns for all possible combinations of types and the
legalizer thinks they are all legal, but we had no tests for it. I was
unable to find any combiner rules that would create an instruction with
mismatch types.
Commit: d3177d8b902bb2dc4a8d61cd51e2662e605d7515
https://github.com/llvm/llvm-project/commit/d3177d8b902bb2dc4a8d61cd51e2662e605d7515
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
Log Message:
-----------
[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
Commit: 1febd71b4dcff17130d3a605eda880de046bbd0f
https://github.com/llvm/llvm-project/commit/1febd71b4dcff17130d3a605eda880de046bbd0f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
A llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
Log Message:
-----------
[NVPTX] Add TTI support for folding isspacep in InferAS (#114486)
This change enables constant folding of '`@llvm.nvvm.isspacep.*`'
intrinsics if the address space can be propagated in InferAdressSpace.
Commit: 36d757f8406a00539228e15b44bb850936871421
https://github.com/llvm/llvm-project/commit/36d757f8406a00539228e15b44bb850936871421
Author: Adam Yang <hanbyang at microsoft.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
R llvm/test/CodeGen/DirectX/clamp-vec.ll
M llvm/test/CodeGen/DirectX/clamp.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
A llvm/test/CodeGen/SPIRV/opencl/clamp.ll
Log Message:
-----------
[HLSL][SPIRV] Added clamp intrinsic (#113394)
Fixes #88052
- Added the following intrinsics:
- `int_spv_uclamp`
- `int_spv_sclamp`
- `int_spv_fclamp`
- Updated DirectX counterparts to have the same three clamp intrinsics.
- Update the clamp.hlsl unit tests to include SPIRV
- Added the SPIRV specific tests
Commit: 4e668d5b27a339918bee4d994fca31d962519e80
https://github.com/llvm/llvm-project/commit/4e668d5b27a339918bee4d994fca31d962519e80
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/ELF_LoongArch_relocations.s
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/lit.local.cfg
Log Message:
-----------
[RuntimeDyld] Add LoongArch support
This is necessary for supporting function calls in LLDB expressions for
LoongArch.
This patch is inspired by #99336 and simply extracts the parts related
to RuntimeDyld.
Reviewed By: lhames
Pull Request: https://github.com/llvm/llvm-project/pull/114741
Commit: 1c8fca82a0f4ac6df5db539e96adcad143f5ebe7
https://github.com/llvm/llvm-project/commit/1c8fca82a0f4ac6df5db539e96adcad143f5ebe7
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/source/Plugins/ABI/CMakeLists.txt
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
A lldb/source/Plugins/ABI/LoongArch/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Log Message:
-----------
[lldb][LoongArch] Function calls support in lldb expressions
This patch adds desired feature flags in JIT compiler to enable
hard-float instructions if target supports them and allows to use floats
and doubles in lldb expressions.
Fited tests:
lldb-shell :: Expr/TestAnonNamespaceParamFunc.cpp
lldb-shell :: Expr/TestIRMemoryMap.test
lldb-shell :: Expr/TestStringLiteralExpr.test
lldb-shell :: SymbolFile/DWARF/debug-types-expressions.test
Similar as #99336
Depens on: https://github.com/llvm/llvm-project/pull/114741
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/114742
Commit: 889d67785905ea85cdb17b2bf2b4b6f010b641f5
https://github.com/llvm/llvm-project/commit/889d67785905ea85cdb17b2bf2b4b6f010b641f5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
Log Message:
-----------
clang/AMDGPU: Restore O3 checks in default-attributes.hip (#115238)
These were dropped in b1bcb7ca460fcd317bbc8309e14c8761bf8394e0 to
avoid some bot failures.
Commit: 4fb43c47ddf0138bf5cb64ec64dfb530bc7db051
https://github.com/llvm/llvm-project/commit/4fb43c47ddf0138bf5cb64ec64dfb530bc7db051
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
Log Message:
-----------
AMDGPU: Fold more scalar operations on frame index to VALU (#115059)
Further extend workaround for the lack of proper regbankselect
for frame indexes.
Commit: e520b28397fa7ad39a9934df65f45cbdf5514a84
https://github.com/llvm/llvm-project/commit/e520b28397fa7ad39a9934df65f45cbdf5514a84
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
A clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/WaveActiveCountBits.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveCountBits.ll
Log Message:
-----------
[DXIL][SPIRV] Lower `WaveActiveCountBits` intrinsic (#113382)
```
- add codegen for llvm builtin to spirv/directx intrinsic in CGBuiltin.cpp
- add lowering of spirv intrinsic to spirv backend in SPIRVInstructionSelector.cpp
- add lowering of directx intrinsic to dxil op in DXIL.td
- add test cases to illustrate passes
- add test case for semantic analysis
```
Resolves #80176
Commit: 8440ced89f232f71ad28a91cd88965548b3095b0
https://github.com/llvm/llvm-project/commit/8440ced89f232f71ad28a91cd88965548b3095b0
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M lld/ELF/Thunks.cpp
Log Message:
-----------
[ELF] Change a Fatal to assert in addThunkAArch64. NFC
Commit: ee1608dd8e6d06d5aa6e62d7bbb6d60bae7bb5a5
https://github.com/llvm/llvm-project/commit/ee1608dd8e6d06d5aa6e62d7bbb6d60bae7bb5a5
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MISched] Set DumpDirection after initPolicy (#115112)
Previously we set the dump direction according to command line
options, but we may override the scheduling direction in `initPolicy`
and this results in mismatch between dump and actual policy.
Here we simply set the dump direction after initializing the policy.
Commit: 50e73aeea2a7e2cbaeb66252aadea9a6144937df
https://github.com/llvm/llvm-project/commit/50e73aeea2a7e2cbaeb66252aadea9a6144937df
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/target-loop-unparse.f90
A flang/test/Semantics/OpenMP/loop-bind.f90
M flang/test/Semantics/OpenMP/nested-distribute.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Parse `bind` clause for `loop` direcitve. (#113662)
Adds parsing for the `bind` clause. The clause was already part of the
`loop` direcitve's definition but parsing was still missing.
Commit: bfa3ffb1e2d7c976c4db10dbdd8f5d09976c63be
https://github.com/llvm/llvm-project/commit/bfa3ffb1e2d7c976c4db10dbdd8f5d09976c63be
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
Log Message:
-----------
[FIX] Add missing component introduced in #115218
That causes link error:
```
ld.lld: error: undefined symbol: llvm::memprof::IndexedMemProfRecord::getGUID(llvm::StringRef)
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced by MemProfUseTest.cpp
>>> unittests/Transforms/Instrumentation/CMakeFiles/InstrumentationTests.dir/MemProfUseTest.cpp.o:((anonymous namespace)::MemProf_ExtractDirectCallsFromIR_Test::TestBody())
>>> referenced 1 more times
```
Commit: 594e11ce4247feb3197dc3cf0da331e96f9a098b
https://github.com/llvm/llvm-project/commit/594e11ce4247feb3197dc3cf0da331e96f9a098b
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Avoid incorrect ICP symtab canonicalization (#115419)
ICP builds a symtab from the symbols in the module allowing mapping from
the VP metadata GUIDs to the Function. MemProf uses this same symtab
handling for its ICP during cloning. When symbols are added to the
symtab, the handling adds both a GUID computed from the function name,
or from the attached PGOFuncName metadata for locals, as well as a GUID
computed from the "canonicalized" name, which strips all "." suffixes
other than ".__uniq". This was originally meant to remove the ".llvm.*"
suffix added to promoted locals (done earlier in the ThinLTO backend).
In theory, it should no longer be needed as locals should have
PGOFuncName metadata.
However, this was causing a linker unsat, in code that used coroutines.
For an original coroutine function, there were several additional
functions created that had the same name, but different "." suffixes.
Therefore the canonical name for these additional functions had the same
GUID as that of the original function, leading to extra entries in the
symtab, and to selecting the wrong function for promotion. For regular
ICP this can happen, but is just a performance issue. However, for
memprof the promoted direct call calls a memprof clone, and because we
called the wrong function, in this case it didn't have a memprof clone
and we got a linker unsat.
We may be able to remove the canonical name handling for ICP in general,
but for now disable it for MemProf. At worst this could lead to not
finding a GUID in the symtab and not performing an ICP, so should be
conservatively correct.
Commit: ae509a085836079585228aede8a5017ad80e1aa9
https://github.com/llvm/llvm-project/commit/ae509a085836079585228aede8a5017ad80e1aa9
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
Log Message:
-----------
[RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (#115269)
Commit: 694719a4801179198489d8dc492341b0ef0e59fa
https://github.com/llvm/llvm-project/commit/694719a4801179198489d8dc492341b0ef0e59fa
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
Log Message:
-----------
[RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. (#115391)
Commit: b613a54075c6e704dcaa15a676bf732955eb4352
https://github.com/llvm/llvm-project/commit/b613a54075c6e704dcaa15a676bf732955eb4352
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Utils/FoldUtils.cpp
Log Message:
-----------
[mlir][IR][NFC] Cleanup insertion point API usage (#115415)
Use `setInsertionPointToStart` / `setInsertionPointToEnd` when possible.
Commit: 3ad640357744890a20494a4943d9a8a94c5b3776
https://github.com/llvm/llvm-project/commit/3ad640357744890a20494a4943d9a8a94c5b3776
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ShadowCallStack.rst
M clang/include/clang/Driver/Options.td
M clang/test/Driver/riscv-features.c
Log Message:
-----------
[Clang][RISCV] Remove forced-sw-shadow-stack (#115355)
This option was used to override the behavior of
`-fsanitize=shadowcallstack` on RISC-V backend, which by default use a
hardware implementation if possible, to use the software implementation
instead. After #112477 and #112478, now two implementation
is represented by independent options and we no longer need it.
Commit: 2f40e3e713efb550c05ff5f911ab4ce2e4a8dddf
https://github.com/llvm/llvm-project/commit/2f40e3e713efb550c05ff5f911ab4ce2e4a8dddf
Author: Janis Heims <janis.heims at undertheprinter.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kSubtarget.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
A llvm/test/CodeGen/M68k/CodeModel/large-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/large-static.ll
Log Message:
-----------
[M68k] implement large code model (#106381)
Fixes #106208.
Commit: 37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
https://github.com/llvm/llvm-project/commit/37b4df434d2cf82feb3672eeeb469e54ee8f7ff2
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
[Clang] Remove the wrong assumption when rebuilding SizeOfPackExprs for constraint normalization (#115120)
In 463a4f150, we assumed that all the template argument packs are of
size 1 when normalizing a constraint expression because I mistakenly
thought those packs were obtained from their injected template
parameters. This was wrong because we might be checking constraints when
instantiating a friend declaration within a class template
specialization, where the parent class template is specialized with
non-dependent template arguments.
In that sense, we shouldn't assume any pack size nor expand anything in
such a scenario. Moreover, there are no intermediate (substituted but
unexpanded) AST nodes for template template parameters, so we have to
special-case their transformations by looking into the instantiation
scope instead of extracting anything from template arguments.
Fixes #115098
Commit: c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
https://github.com/llvm/llvm-project/commit/c6414970d76ad79168fe7ec3c4400c5a5ca89d2d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
Log Message:
-----------
[Coroutines] Inline the `.noalloc` ramp function marked coro_safe_elide (#114004)
Commit: d233fedfb0de882353c348cd1ac57dab619efa6d
https://github.com/llvm/llvm-project/commit/d233fedfb0de882353c348cd1ac57dab619efa6d
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
Log Message:
-----------
[Coroutines] Respect noinline attributes when eliding heap allocation (#115384)
Commit: 9061e6e58a78046963f0eb5991e98346e01a0bf7
https://github.com/llvm/llvm-project/commit/9061e6e58a78046963f0eb5991e98346e01a0bf7
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
Log Message:
-----------
[GlobalISel][AArch64] Legalize G_EXTRACT_VECTOR_ELT for SVE (#115161)
AArch64InstrGISel.td defines:
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
There are many patterns for SVE. Let's exploit that fact.
Commit: c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
https://github.com/llvm/llvm-project/commit/c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
Author: T-Tie <t_tttie at 163.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)
Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
Commit: 1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
https://github.com/llvm/llvm-project/commit/1adca7af21f1d8cc12b0f1c33db8ab869b36ae48
Author: Sebastian Kreutzer <SebastianKreutzer at gmx.net>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M clang/test/Driver/XRay/xray-shared.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
Log Message:
-----------
Reapply "[XRay][AArch64] Support -fxray-shared (#114431)" (#115300)
This patch implements support for `-fxray-shared` on AArch64 and fixes a
remaining issue in the previous PR #114431.
A bug in the XRay `CMakeLists.txt` caused the XRay assembly sources to
be built for every architecture in `XRAY_DSO_SUPPORTED_ARCH` on Apple.
This led to the compiler trying to compile AArch64 assembly for X86
targets and vice versa.
This is addressed here by ensuring that assembly sources are only built
for the matching architecture (see fixup commit).
**Original PR description:**
This patch adds support for `-fxray-shared` on AArch64. This feature,
introduced in #113548 for x86_64, enables the instrumentation of shared
libraries with XRay.
Changes:
- Adds AArch64 to the list of targets supporting `-fxray-shared`
- Introduces PIC versions of the AArch64 XRay trampolines
- Adjusts relevant XRay tests
Commit: a25d91a164b0a283dd809cf9b4d9442d24173fb7
https://github.com/llvm/llvm-project/commit/a25d91a164b0a283dd809cf9b4d9442d24173fb7
Author: Gergely Futo <gergely.futo at hightec-rt.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
Log Message:
-----------
[RISCV] Skip DAG combine for bitcast fabs/fneg (#115325)
Disable the DAG combine for bitcast fabs/fneg in case of the zdinx
extension.
The combine folds the fabs/fneg nodes in some cases. This might result
in suboptimal code if compiled with the zdinx extension. In case of the
zdinx extension, there is no need to load the double value from an x
register to an f register, so the combine can be skipped.
Commit: 984bca9d1faaa1fa5c694f8f2a5524b2374d204a
https://github.com/llvm/llvm-project/commit/984bca9d1faaa1fa5c694f8f2a5524b2374d204a
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
Log Message:
-----------
[GVN][NewGVN] Take call attributes into account in expressions (#114545)
Drop `canBeReplacedBy` and take call attributes into account in
expressions.
Address comment
https://github.com/llvm/llvm-project/pull/114011#pullrequestreview-2409772313.
Commit: f02b1cc99e12ac0147d5c334f130a305d85e477a
https://github.com/llvm/llvm-project/commit/f02b1cc99e12ac0147d5c334f130a305d85e477a
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
Log Message:
-----------
[ASTWriter] Detect more non-affecting FileIDs to reduce source location duplication (#112015)
Currently, any FileID that references a module map file that was
required for a compilation is considered as affecting. This misses an
important opportunity to reduce the source location space taken by the
resulting PCM.
In particular, consider the situation where the same module map file is
passed multiple times in the dependency chain:
```shell
$ clang -fmodule-map-file=foo.modulemap ... -o mod1.pcm
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod1.pcm ... -o mod2.pcm
...
$ clang -fmodule-map-file=foo.modulemap -fmodule-file=mod$((N-1)).pcm ... -o mod$N.pcm
```
Because `foo.modulemap` is read before reading any of the `.pcm` files,
we have to create a unique `FileID` for it when creating each module.
However, when reading the `.pcm` files, we will reuse the `FileID`
loaded from it for the same module map file and the `FileID` we created
can never be used again, but we will still mark it as affecting and it
will take the source location space in the output PCM.
For a chain of N dependencies, this results in the file taking `N *
(size of file)` source location space, which could be significant. For
examples, we observer internally that some targets that run out of 2GB
of source location space end up wasting up to 20% of that space in
module maps as described above.
I take extra care to still write the InputFile entries for those files that occupied
source location space before. It is required for correctness of clang-scan-deps.
Commit: d6d73ec89e493c69cf24dc3a710d861e2ce08acb
https://github.com/llvm/llvm-project/commit/d6d73ec89e493c69cf24dc3a710d861e2ce08acb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable vector.flat_transpose for scalable vectors (#115338)
Disables `vector.flat_transpose` for scalable vectors. As per the docs:
> This is the counterpart of llvm.matrix.transpose in MLIR
I'm not aware of any use of any matrix-multiply intrinsics in the
context of scalable vectors, hence disabling.
Note, this is a follow-on for #102573 in which I disabled
`vector.matrix_multiply`.
Commit: ff07df6620c32571c7e13ff96ec7976c63ed0ab8
https://github.com/llvm/llvm-project/commit/ff07df6620c32571c7e13ff96ec7976c63ed0ab8
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
Log Message:
-----------
[InstCombine] Drop nsw in negation of select (#112893)
Closes https://github.com/llvm/llvm-project/issues/112666 and
https://github.com/llvm/llvm-project/issues/114181.
Commit: b9dd60228cbb2a173380a450f0f71ca43e917783
https://github.com/llvm/llvm-project/commit/b9dd60228cbb2a173380a450f0f71ca43e917783
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/sve-hadd.ll
Log Message:
-----------
[DAGCombiner] Remove a hasOneUse check in visitAND (#115142)
For some reason there was a hasOneUse check on the splat for the
second operand and it's not obvious to me why. The check blocks
optimisations for lowering of nodes like AVGFLOORU and AVGCEILU.
In a follow-on patch I also plan to improve the generated code
for AVGCEILU further by teaching computeKnownBits about
zero-extending masked loads.
Commit: 58a17e1bbc54357385d0b89cfc5635e402c31ef6
https://github.com/llvm/llvm-project/commit/58a17e1bbc54357385d0b89cfc5635e402c31ef6
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-AVX512 (#114070)
Commit: 4f3bf1c62ceb85d2e33857ada26b565822e65600
https://github.com/llvm/llvm-project/commit/4f3bf1c62ceb85d2e33857ada26b565822e65600
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 58a17e1bbc54
Commit: d74127e78aa7f8ab07b0926d25920444dde6c73c
https://github.com/llvm/llvm-project/commit/d74127e78aa7f8ab07b0926d25920444dde6c73c
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[flang][OpenMP][MLIR] Add MLIR op for loop directive (#113911)
Adds MLIR op that corresponds to the `loop` directive.
Commit: 546066e4f74d50c974248b0ed247f65ebf24b75c
https://github.com/llvm/llvm-project/commit/546066e4f74d50c974248b0ed247f65ebf24b75c
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/DIBuilder.cpp
Log Message:
-----------
Fix DIBuilder::createVariantPart after f6617d65e496
which ended up passing 0 for the Discriminator arg, Discriminator for
the DataLocation arg, etc.
The DICompositeType::get's new NumExtraInhabitants parameter is at the
end, and has a default value, so no change in the caller is necessary.
See comment on https://github.com/llvm/llvm-project/pull/112590
Commit: ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
https://github.com/llvm/llvm-project/commit/ffe49b7bcfb37cbca8523b59cb5b26a74369a7d1
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/PDB.cpp
A lld/test/COFF/arm64ec-pdb.test
Log Message:
-----------
[LLD][COFF] Use correct machine types in PDB records on ARM64EC (#115309)
Commit: 799e520c51f47c54769e5bd8ce6ce2d2d3931445
https://github.com/llvm/llvm-project/commit/799e520c51f47c54769e5bd8ce6ce2d2d3931445
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/attr-target-clones-aarch64.c
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/lib/Target/AArch64/AArch64FMV.td
Log Message:
-----------
[FMV] Remove feature dgh. (#115363)
It belongs to the HINT space so it can be executed as NOP if the
hardware doesn't support it.
Reviewed in ACLE -> https://github.com/ARM-software/acle/pull/357
Commit: 4bcd4d843f660c1a435159a2964f0c4cf4564ab1
https://github.com/llvm/llvm-project/commit/4bcd4d843f660c1a435159a2964f0c4cf4564ab1
Author: Weaver <Tom.Weaver at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGenHIP/default-attributes.hip
Log Message:
-----------
Revert "clang/AMDGPU: Restore O3 checks in default-attributes.hip (#115238)"
This reverts commit 889d67785905ea85cdb17b2bf2b4b6f010b641f5.
Caused the following build bot failures, author has failed to address:
https://lab.llvm.org/buildbot/#/builders/144/builds/11132
https://lab.llvm.org/buildbot/#/builders/46/builds/7541
https://lab.llvm.org/buildbot/#/builders/190/builds/9077
Please fix before recommitting.
Commit: 2c49301d91d743c4424997c5f670a453439b4b86
https://github.com/llvm/llvm-project/commit/2c49301d91d743c4424997c5f670a453439b4b86
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
Log Message:
-----------
[IR] Remove variadic overload of StructType::setBody. NFC. (#114421)
This is unused in-tree.
Commit: 31af00fda73df8e85e30c71f66e096d486ec8c8b
https://github.com/llvm/llvm-project/commit/31af00fda73df8e85e30c71f66e096d486ec8c8b
Author: amilendra <amilendra.kodithuwakku at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/test/MC/AArch64/spe.s
Log Message:
-----------
[AArch64][v8.7-A] Fix inconsistency in SPE_EEF feature (#115296)
The `SPE-EEF` system-register only feature introduced in Armv8.7-a adds
support for an extra system register (`PMSNEVFR_EL1`) to the Statistical
Profiling extension.
However, `SPE-EEF` is gated even for Armv8.7-a and the `spe-eef`
subtarget-feature is needed to enable it.
This behavior is inconsistent with the implementation for other
system-register only features as they can be used ungated under
supported architectures.
(e.g. HCX : Enable Armv8.7-A `HCRX_EL2` system register).
GCC/Binutils too do not add command line flags for features that only
enable system registers.
Fix by enabling `SPE-EEF` unconditionally under v8.7-A and above.
Commit: 0a7e5e34569737447e9e3e08b5f87883300061e5
https://github.com/llvm/llvm-project/commit/0a7e5e34569737447e9e3e08b5f87883300061e5
Author: Alona Enraght-Moony <code at alona.page>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/docs/UserDocumentation.rst
Log Message:
-----------
[libc++][docs] Document _LIBCPP_ENABLE_CXX17_REMOVED_UNARY_BINARY_FUNCTION (#115405)
This was added in 681cde7dd8b5613dbafc9ca54e0288477f946be3, but isn't
currently documented.
Commit: df3f18b071d853896318d2d37186fc6289ffdb2b
https://github.com/llvm/llvm-project/commit/df3f18b071d853896318d2d37186fc6289ffdb2b
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of Windows host (#115337)
Fixed the @skipUnlessAArch64MTELinuxCompiler decorator in case of
Windows host.
Commit: 39bce77bd6cdb334810ed95249683484e44c1165
https://github.com/llvm/llvm-project/commit/39bce77bd6cdb334810ed95249683484e44c1165
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: XFAIL on Darwin for older compiler verions
Follow-up to https://github.com/llvm/llvm-project/pull/111859. Prior
to this PR we would never run these tests with DWARFv5 on older Clang
versions (since default wasn't DWARFv5 on macOS until recently). The
patch explicitly started running some of these tests with DWARFv5.
These were failing on the macOS matrix bot (with Clang-15/Clang-17).
```
======================================================================
FAIL: test_inline_static_members_dwarf5_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 150, in test_inline_static_members_dwarf5
self.check_inline_static_members("-gdwarf-5")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
```
Commit: 34bf9dd6d39cb2bf75731cea7a26c3563720cb67
https://github.com/llvm/llvm-project/commit/34bf9dd6d39cb2bf75731cea7a26c3563720cb67
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: fix XFAIL decorators
The `compiler` parameter is not supported in the `expectedFailureDarwin`
decorator.
Change the decorator to `expectedFailureAll`, which is fine because
this only affects the `dsym` variant (which is only a macOS variant).
Commit: 3797daa5448f3471c0d7d1c67838922a83a06fa1
https://github.com/llvm/llvm-project/commit/3797daa5448f3471c0d7d1c67838922a83a06fa1
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
Log Message:
-----------
[AArch64] Create set.fpmr intrinsic and assembly lowering (#114248)
This patch introduces new llvm.set.fpmr intrinsics for setting value in
FPMR register and adds its lowering to series of read-compare-write
instructions. This intrinsic will be generated during lowering of FP8 C
intrinsics into LLVM-IR introduced in later patch.
***This is an experimental implementation of handling fp8 intriniscs and
is likely to change in the future.***
Commit: 6e4cd463e580046feb66597a61db352c63fd783b
https://github.com/llvm/llvm-project/commit/6e4cd463e580046feb66597a61db352c63fd783b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
Log Message:
-----------
[lldb] s/assertEquals/assertEqual TestDAP_sendEvent
New unittest versions don't have the "s" version.
Commit: e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
https://github.com/llvm/llvm-project/commit/e3b0ef7aaacb7f1374cb0fc5f6dde4b95ebfa624
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Remove forced-sw-shadow-stack in RISCVFeatures.td (#115447)
This patch removes forced-sw-shadow-stack related statements in
RISCVFeatures.td, which was missed in the last patch
https://github.com/llvm/llvm-project/pull/115355
Commit: 0daca808ce111f21db8c0ee9ea5d2509d6034557
https://github.com/llvm/llvm-project/commit/0daca808ce111f21db8c0ee9ea5d2509d6034557
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/C/C2y/n3344.c
Log Message:
-----------
Fix issues with WG14 N3344 changes
This amends 24e2e259a06d9aa67dc278ac24dcb98da9dd63f6 with a fix for
'register void *', which is still okay as a function parameter.
Commit: 724b432410fd59c63cc313d41824eda5ec84052f
https://github.com/llvm/llvm-project/commit/724b432410fd59c63cc313d41824eda5ec84052f
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/stdalign.h
Log Message:
-----------
[z/OS] Make sure __alignas_is_defined and __alignof_is_defined are defined on z/OS. (#115368)
Commit: afa178d36017ab565c33a8639be16355a054b95b
https://github.com/llvm/llvm-project/commit/afa178d36017ab565c33a8639be16355a054b95b
Author: lfrenot <leon.frenot at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
Log Message:
-----------
[mlir][LLVM] Add exact flag (#115327)
The implementation is mostly based on the one existing for the nsw and
nuw flags.
If the exact flag is present, the corresponding operation returns a
poison value when the result is not exact. (For a division, if rounding
happens; for a right shift, if a non-zero bit is shifted out.)
Commit: 5fbe9b958dc3035480406c2cd4524e4827d2dfaf
https://github.com/llvm/llvm-project/commit/5fbe9b958dc3035480406c2cd4524e4827d2dfaf
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lld/COFF/Writer.cpp
A lld/test/COFF/cfguard-off-instrumented.s
Log Message:
-----------
[LLD][COFF] Set __guard_flags to CF_INSTRUMENTED if any object is instrumented (#115374)
Commit: 0e39b1348e5fcadb129a6f113e5d708a526d8faa
https://github.com/llvm/llvm-project/commit/0e39b1348e5fcadb129a6f113e5d708a526d8faa
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/test/CMakeLists.txt
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
[mlir] Remove the mlir-spirv-cpu-runner (move to mlir-cpu-runner) (#114563)
This commit builds on and completes the work done in
9f6c632ecda08bfff76b798c46d5d7cfde57b5e9 to eliminate the need for a
separate mlir-spirv-cpu-runner binary. Since the MLIR processing is
already done outside this runner, the only real difference between it
and the mlir-cpu-runner is the final linking step between the nested
LLVM IR modules. By moving this step into mlir-cpu-runner behind a new
command-line flag (`--link-nested-modules`), this commit is able to
completely remove the runner component of the mlir-spirv-cpu-runner.
The runtime libraries and the tests are moved and renamed to fit into
the Execution Engine and Integration tests, following the model of the
similar migration done for the CUDA Runner in D97463.
Commit: 231e03ba7e82896847dbc27d457dbb208f04699c
https://github.com/llvm/llvm-project/commit/231e03ba7e82896847dbc27d457dbb208f04699c
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[AArch64] Add select-opt test with select transformed to cast.
Add tests with add and sub binops with zext i1 operands.
Commit: e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
https://github.com/llvm/llvm-project/commit/e5c6d1f4e6d6c8709f92b47717cffc486947ff1b
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
A clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros (#112849)
So far, these macros can be used in contexts where no meaningful
wavefront size is available. We therefore deprecate these macros, to
replace them with a more resilient interface to access wavefront size
information where it is available.
For SWDEV-491529.
Commit: 32c744ae339dc356060636bcdf75a5e2a67fca00
https://github.com/llvm/llvm-project/commit/32c744ae339dc356060636bcdf75a5e2a67fca00
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Fixed the @skipUnlessAArch64MTELinuxCompiler decorator (#115480)
It is broken after #115337
https://lab.llvm.org/buildbot/#/builders/195/builds/794
Commit: b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
https://github.com/llvm/llvm-project/commit/b0cfbfd74bfd9d077f7c1854a1b38dcbe9d402e4
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ast-print-openacc-loop-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
Log Message:
-----------
[OpenACC] Implement `loop` restrictions on `for` loops. (#115370)
OpenACC restricts the contents of a 'for' loop affected by a 'loop'
construct without a 'seq'. The loop variable must be integer, pointer,
or random-access-iterator, it must monotonically increase/decrease, and
the trip count must be computable at runtime before the function.
This patch tries to implement some of these limitations to the best of
our ability, though it causes us to be perhaps overly restrictive at the
moment. I expect we'll revisit some of these rules/add additional
supported forms of loop-variable and 'monotonically increasing' here,
but the currently enforced rules are heavily inspired by the OMP
implementation here.
Commit: 844fe8f662de6d1a51f4a04b37fadb96b2009bd0
https://github.com/llvm/llvm-project/commit/844fe8f662de6d1a51f4a04b37fadb96b2009bd0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][nfc] Rename @genbool_* as @constant_mask_* (#115335)
Renames `@genbool_*` tests as `@constant_mask_*`. That's to better
highlight which Op is tested and for better consistency with other test.
In addition,`@genbool_2d` is moved _above_ it's counterparts with
scalable vectors (again, for consistency).
Commit: d5677b630d0faf38e2e92797415ff80676f86063
https://github.com/llvm/llvm-project/commit/d5677b630d0faf38e2e92797415ff80676f86063
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/commands/target/basic/TestTargetCommand.py
Log Message:
-----------
[lldb] Fixed TestTargetCommand.py in case of Windows host and Linux target (#115470)
Fixed TestTargetCommand.py in case of Windows host and Linux target.
Commit: 107af4a62ee9afb4be2cba1bc7c12afb677445ef
https://github.com/llvm/llvm-project/commit/107af4a62ee9afb4be2cba1bc7c12afb677445ef
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Introduce struct PredInfo. NFC. (#115457)
This just provides a neater encapsulation of the info about the
predicate for an edge, rather than ValueWeightPair aka std::pair.
Commit: 644a9a4327af4fb4f7b09832cafe3c82843231b5
https://github.com/llvm/llvm-project/commit/644a9a4327af4fb4f7b09832cafe3c82843231b5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
Log Message:
-----------
[CodeExtractor][NFC] Refactor-out applyFirstDebugLoc. (#115358)
Split-off from #114419
Commit: ab9178e3e73dc715463e1019ed2cd449dc18bb18
https://github.com/llvm/llvm-project/commit/ab9178e3e73dc715463e1019ed2cd449dc18bb18
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
Log Message:
-----------
[ARM] Add a couple of new MVE reduction tests. NFC
Nowadays we generate add(zext(mul(sext, sext)) with nneg zext and the multi-use
test is awkward to get right. This should help our test coverage with the vplan
cost transition.
Commit: 3c3f19ca5ea03428edacbd5d087b991c447c47dc
https://github.com/llvm/llvm-project/commit/3c3f19ca5ea03428edacbd5d087b991c447c47dc
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/Intrinsics.cpp
Log Message:
-----------
Revert "[NFC][LLVM] Use namespace `Intrinsic` in `Intrinsics.cpp` (#114822)"
This reverts commit c2b61fcb3cd4ffa286b24437b7b6d66f0dee6c25.
Intrinsic namespace contains memcpy which is a naming conflict with
memcpy from string.h header.
Commit: 53e6f627d7e81633b2e159675884bfcce11bdc00
https://github.com/llvm/llvm-project/commit/53e6f627d7e81633b2e159675884bfcce11bdc00
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] _mm_movpi64_epi64 - convert to shufflevector pattern instead of bitcasting to i64
Don't bitcast a v1i64 to i64 as constant expressions will struggle to handle this - convert to a shufflevector concat pattern like _mm_move_epi64 instead
Commit: 0f040433d325aa68ec6840aa179f3f314c26153a
https://github.com/llvm/llvm-project/commit/0f040433d325aa68ec6840aa179f3f314c26153a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Update MMX intrinsic tests for both C/C++
Requires update to movmsk call to handle additional markers
Commit: 77bec78878762e34150fe23734fa43df796c873c
https://github.com/llvm/llvm-project/commit/77bec78878762e34150fe23734fa43df796c873c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Do not look for last instruction in schedule block for buildvectors
If looking for the insertion point for the node and the node is
a buildvector node, the compiler should not use scheduling info for such
nodes, they may contain only partial info, which is not fully correct
and may cause compiler crash.
Fixes #114082
Commit: f7bb12901e2955b972273a06dd028ab4b2822b44
https://github.com/llvm/llvm-project/commit/f7bb12901e2955b972273a06dd028ab4b2822b44
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Add tanpif16 function (#115183)
- Implementation of `tan` for 16-bit floating point inputs scaled by pi.
i.e,. `tanpif16()`
- Implementation of Tanpi in MPFRWrapper for MPFR versions < 4.2
- Exhaustive tests for `tanpif16()`
Commit: 1645d99bc9c16b1f9e2f08e36d67054498d8751e
https://github.com/llvm/llvm-project/commit/1645d99bc9c16b1f9e2f08e36d67054498d8751e
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
Log Message:
-----------
[libc++][hardening] Use `static_assert` for `__(static_)bounded_iter` (#115304)
We can't `static_assert` `__libcpp_is_contiguous_iterator` for
`__wrap_iter` currently because `__wrap_iter` is also used for wrapping
user-defined fancy pointers.
Fixes #115002.
Commit: 9aea6671085f02e6127750103ca48ae6a09ceeb8
https://github.com/llvm/llvm-project/commit/9aea6671085f02e6127750103ca48ae6a09ceeb8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Log Message:
-----------
[symbolizer] Change the ErrorHandler from llvm::function_ref to std::function. (#115477)
This fixes dangling `ErrorHandler` references
([here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp#L48-L53)
is an example).
`llvm::function_ref` doesn't own the callable, and it is not safe to
store a function_ref (the `PlainPrinterBase` stores a
`llvm::function_ref` which can easily lead to dangling references).
Commit: 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
https://github.com/llvm/llvm-project/commit/8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-lifetimebound.c
Log Message:
-----------
[clang] Permit lifetimebound in all language modes (#115482)
Lifetimebound annotations can help diagnose common cases of dangling
including escaping the address of a stack variable from a function. This
is useful in all C family languages, restricting these diagnostics to
C++ is an artificial limitation.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: da9499ebfb323602c42aeb674571fe89cec20ca6
https://github.com/llvm/llvm-project/commit/da9499ebfb323602c42aeb674571fe89cec20ca6
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293)
This patch introduces the amended feature flag for
[FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES),
'**sve-aes**'. The existing flag associated with this feature,
'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for
backwards compatibility.
The
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension)
documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1
when
> there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions
and if the associated ACLE intrinsics are available.
The front-end has been amended such that it is compatible with +sve2-aes
and +sve2+sve-aes.
Commit: 7844257fc2afe490ae4b923a770d20dabed5c3c6
https://github.com/llvm/llvm-project/commit/7844257fc2afe490ae4b923a770d20dabed5c3c6
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Use explicit #include instead of transitive #include (#115420)
This benchmark test currently uses `std::unique_ptr` without explicitly
`#include <memory>`. I think we should not rely on transitive inclusion.
Commit: c93eb43a63d3b5c90e828608b5c2063644a3b161
https://github.com/llvm/llvm-project/commit/c93eb43a63d3b5c90e828608b5c2063644a3b161
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lua_api/TestFileHandle.lua
Log Message:
-----------
[lldb] Fix TestFileHandle.lua
- Explicitly create an `SBFile`.
- Add missing call to `close`.
- Use `SetErrorFile` in TestLegacyFileErr.
Commit: e734de1f5a3c2ec0c88221eb0991b0922e30d902
https://github.com/llvm/llvm-project/commit/e734de1f5a3c2ec0c88221eb0991b0922e30d902
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
Revert "[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros" (#115499)
Reverts llvm/llvm-project#112849 due to test failure on Mac, reported by
@nico
Commit: 6737ba40406030cd8a7ea706cd56302f8be7a4b4
https://github.com/llvm/llvm-project/commit/6737ba40406030cd8a7ea706cd56302f8be7a4b4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Update the lifetimebound doc.
The lifetimebound attr is not C++ only anymore after 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Commit: c9552283c0bf277eba490cde9fd913510f4111c0
https://github.com/llvm/llvm-project/commit/c9552283c0bf277eba490cde9fd913510f4111c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for MMX _mm_set*_pi* intrinsics
Commit: 2407ff4645e9124507a4b5d910603ff7fc9e5734
https://github.com/llvm/llvm-project/commit/2407ff4645e9124507a4b5d910603ff7fc9e5734
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_movpi64_epi64
Commit: 51e8f822f39174eaf83b1d5798de329518970b02
https://github.com/llvm/llvm-project/commit/51e8f822f39174eaf83b1d5798de329518970b02
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr62014.ll
Log Message:
-----------
[X86] pr62014.ll - regenerate test checks with vpternlog comments
Commit: 71f82bba35c48eaf98c50aeeb4d2675156681c02
https://github.com/llvm/llvm-project/commit/71f82bba35c48eaf98c50aeeb4d2675156681c02
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
Log Message:
-----------
[SPIRV] Use heterogenous lookups with std::map (NFC) (#115425)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 6ce44266fc2d06dfcbefd8146279473ccada52ca
https://github.com/llvm/llvm-project/commit/6ce44266fc2d06dfcbefd8146279473ccada52ca
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/lib/IR/Dialect.cpp
Log Message:
-----------
[mlir] Use heterogenous lookups with std::map (NFC) (#115426)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: a4819d6aa30f849770c258abba67a4b721642ebf
https://github.com/llvm/llvm-project/commit/a4819d6aa30f849770c258abba67a4b721642ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/IR/MLIRContext.cpp
Log Message:
-----------
[mlir] Simplify code with StringMap::operator[] (NFC) (#115427)
Commit: bc7e5c2016e287b768d2a3a1de15f6bb644622ae
https://github.com/llvm/llvm-project/commit/bc7e5c2016e287b768d2a3a1de15f6bb644622ae
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Avoid repeated hash lookups (NFC) (#115428)
Commit: 2f243a5fb754c3688dfa225ce8073a281bca1a24
https://github.com/llvm/llvm-project/commit/2f243a5fb754c3688dfa225ce8073a281bca1a24
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for 0e39b1348e5fcadb129a6f113e5d708a526d8faa
Commit: 3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
https://github.com/llvm/llvm-project/commit/3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
Log Message:
-----------
[llvm-reduce] Reduce samesign flag from icmp (#115492)
Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Log Message:
-----------
[AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)
We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
`fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
`fma extract(Rn, 0), Rm, Ra -> fmadd`
The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
`fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
`fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`
Commit: 4027400d2ceefb5ce68d4508e5f30dc40c4f535b
https://github.com/llvm/llvm-project/commit/4027400d2ceefb5ce68d4508e5f30dc40c4f535b
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
A clang/test/C/C2y/n3342.c
M clang/test/Misc/warning-flags.c
M clang/test/Sema/declspec.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3342 (#115494)
This paper made qualified function types implementation-defined. We have
always supported this as an extension, so now we're documenting our
behavior.
Note, we still warn about this by default even in C2y mode because a
qualified function type is a sign of programmer confusion.
Commit: f756d38abf2ec40ee06ee5aa668db444e5d6f485
https://github.com/llvm/llvm-project/commit/f756d38abf2ec40ee06ee5aa668db444e5d6f485
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3342.c
Log Message:
-----------
Fix failing test bot
Fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11191
Commit: e5e15f9128b69f77668465b715b7984b8d5ad75a
https://github.com/llvm/llvm-project/commit/e5e15f9128b69f77668465b715b7984b8d5ad75a
Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
add QuietMisdreavus to Clang/ExtractAPI code owners (#115206)
Adding myself to the ExtractAPI code owners listing so i can participate
in code reviews.
Commit: 19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
https://github.com/llvm/llvm-project/commit/19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/vector-sext.ll
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use broadcast on AVX2+ targets
Make use of AVX2 broadcasts to splat the source integer across all lanes to simplify the per-lane byte shuffles.
Prep work to avoid a regression in the fix for #66150
Commit: 79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
https://github.com/llvm/llvm-project/commit/79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use SelectionDAG::getSplat helper instead of shuffle(scalar_to_vector(x))
Commit: 92e0fb0c944254312d7b9c6ca64a026643617f60
https://github.com/llvm/llvm-project/commit/92e0fb0c944254312d7b9c6ca64a026643617f60
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
Log Message:
-----------
[DebugInfo][LoopUnroll] Preserve DebugLocs on optimized cond branches (#114225)
This patch fixes a simple error where as part of loop unrolling we
optimize conditional loop-exiting branches into unconditional branches
when we know that they will or won't exit the loop, but does not
propagate the source location of the original branch to the new one.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
Log Message:
-----------
[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)
Fixes 2 old TODOs
Commit: b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
https://github.com/llvm/llvm-project/commit/b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Remove one SSAUpdater::AddAvailableValue. NFCI. (#115472)
Commit: 39358f846d1e336def88ff9c25581fab392d59fe
https://github.com/llvm/llvm-project/commit/39358f846d1e336def88ff9c25581fab392d59fe
Author: stefankoncarevic <skoncare at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/named-ops.mlir
Log Message:
-----------
[mlir][linalg] Add Grouped Convolution Ops: conv_2d_nhwgc_gfhwc and conv_2d_nhwgc_gfhwc_q (#108192)
This patch adds two new ops: linalg::Conv2DNhwgcGfhwcOp and
linalg::Conv2DNhwgcGfhwcQOp, and uses them to convert tosa group conv2d
Ops.
- Added linalg::Conv2DNhwgcGfhwcOp and linalg::Conv2DNhwgcGfhwcQOp.
- Updated the conversion process to use these new ops for tosa group
conv2d operations.
Commit: c3c2f46f7bd5891af13fef56a8754007f11ff6c1
https://github.com/llvm/llvm-project/commit/c3c2f46f7bd5891af13fef56a8754007f11ff6c1
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/test/C/C2y/n3346.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Claim conformance and add test coverage for WG14 N3346 (#115516)
This converts some undefined behaviors during initialization to instead
be constraint violations. Clang has always implemented these as
constraints, so no compiler changes were needed.
Commit: f7eba08497a2a46f2c10737a110f6b778faf1615
https://github.com/llvm/llvm-project/commit/f7eba08497a2a46f2c10737a110f6b778faf1615
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ObjectYAML/ELFEmitter.cpp
Log Message:
-----------
[ObjectYAML][ELF] Fix misspelling in `Elf_Verdaux` var name (NFC)
Commit: 60972a893e2bf915f6ff043c9396dea9619456fb
https://github.com/llvm/llvm-project/commit/60972a893e2bf915f6ff043c9396dea9619456fb
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/obj2yaml/elf2yaml.cpp
Log Message:
-----------
[ObjectYAML][ELF] Allow verdaux entry offset to be user-defined
Commit: b85e5b49d3efc37e837757a5154884648dc57113
https://github.com/llvm/llvm-project/commit/b85e5b49d3efc37e837757a5154884648dc57113
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Speculatively fix test bots
This should address the issues found by:
https://lab.llvm.org/buildbot/#/builders/12/builds/9226
https://lab.llvm.org/buildbot/#/builders/140/builds/10487
https://lab.llvm.org/buildbot/#/builders/27/builds/1752
Commit: d30a6dcfa06196dd98fc898219eb12bab04a56de
https://github.com/llvm/llvm-project/commit/d30a6dcfa06196dd98fc898219eb12bab04a56de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
Log Message:
-----------
[AMDGPU] Reorganize tests to unblock #112403 (#115503)
We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the `[15 x i32]` arguments to
`[13 x i32]` to bypass the issue.
Commit: e215a1e27d84adad2635a52393621eb4fa439dc9
https://github.com/llvm/llvm-project/commit/e215a1e27d84adad2635a52393621eb4fa439dc9
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
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M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
Commit: 4661467003e7bc7f9bb89ab581517617d2a36c62
https://github.com/llvm/llvm-project/commit/4661467003e7bc7f9bb89ab581517617d2a36c62
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
A clang/test/C/C2y/n3341.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3341 (#115478)
This paper made empty structures and unions implementation-defined. We
have always supported this as a GNU extension, so now we're documenting
our behavior and removing the extension warning in C2y mode.
Commit: b70d1302cf2edaf95817a90f161691c684945273
https://github.com/llvm/llvm-project/commit/b70d1302cf2edaf95817a90f161691c684945273
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Another speculative fix for WG14 N3346
This time it's for builders that don't default to C11 or later, such as:
https://lab.llvm.org/buildbot/#/builders/144/builds/11201
Commit: 2808f05e83643b3d5ef128340f6f4da994ed71e3
https://github.com/llvm/llvm-project/commit/2808f05e83643b3d5ef128340f6f4da994ed71e3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3341.c
Log Message:
-----------
Update test case for bots which don't default to C17
Commit: 17f3e00911b860d535f41185e605c47babcc2039
https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
The increase in fallbacks that was previously reported were not caused
by this change.
Original description:
This matches InstCombine and DAGCombine.
RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.
Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
Commit: e4d57d6a729fd955ccbdd8834065356f26284f3d
https://github.com/llvm/llvm-project/commit/e4d57d6a729fd955ccbdd8834065356f26284f3d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
Log Message:
-----------
[OpenACC] Remove 'loop' link to parent construct
After implementing 'loop', we determined that the link to its parent
only ever uses the type, not the construct itself. This patch removes
it, as it is both a waste and causes problems with serialization.
Commit: e53c46a9084caac115d7f694e5f16f904b0d7124
https://github.com/llvm/llvm-project/commit/e53c46a9084caac115d7f694e5f16f904b0d7124
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
Log Message:
-----------
[Statepoint] Treat result of atomicrmw xchg as a base pointer (#97280)
Atomic RMW Xchg wasn't handled before when searching for known base
pointers in the IR.
Commit: 40740c4494d971ce410e2051b8d3ea7bbe081c76
https://github.com/llvm/llvm-project/commit/40740c4494d971ce410e2051b8d3ea7bbe081c76
Author: Siddhesh Deodhar <153800103+siddhesh195 at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
Log Message:
-----------
Fix crash when using when using --finalize-memref-to-llvm (#112433)
This patch fixes crash when attempting to convert uint to int address
space during finalize-memref-to-llvm by doing the following:
1. Add a check to verify that IntegerAttr is signed int before calling
IntegerAttr::getInt()
2. Emit error when getMemRefAddressSpace returns a failure()
Closes #111242
---------
Co-authored-by: Christian Ulmann <christianulmann at gmail.com>
Commit: 2b885f056585f82903f067840e54557a5b444b65
https://github.com/llvm/llvm-project/commit/2b885f056585f82903f067840e54557a5b444b65
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Fix test for bots that don't default to C17
Commit: a749c98b49dc9a3863b685212d70be98b4f189c3
https://github.com/llvm/llvm-project/commit/a749c98b49dc9a3863b685212d70be98b4f189c3
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Baze] Add missing lldbDataFormatter.py back to BUILD.bazel. (#115519)
- [x] Add `utils/lldbDataFormatters.py` back.
Commit: fe5a64d1160209f22624b112b2629b0d6c4bb264
https://github.com/llvm/llvm-project/commit/fe5a64d1160209f22624b112b2629b0d6c4bb264
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
Log Message:
-----------
[fang][cuda] Allow * in call chevron syntax (#115381)
Using `*` in call chevron syntax should be allowed. This patch updates
the parser to allow this usage.
```
call sub<<<*,nbBlock>>>()
```
Commit: 86405ed1012c97b063cbde12350fdea141e1ab78
https://github.com/llvm/llvm-project/commit/86405ed1012c97b063cbde12350fdea141e1ab78
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
Log Message:
-----------
[DebugInfo][Reassociate] Preserve DebugLocs when reassociating subs (#114226)
In NegateValue in Reassociate, we return the negation of an existing
value in order to break a subtract into an negate + add, potentially
creating a new instruction to perform the negation, but we neglect to
propagate the DebugLoc of the sub being replaced to the negate
instruction if one is created. This patch adds that propagation.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 40e545098e8bb5a18988316331e46c4557378afa
https://github.com/llvm/llvm-project/commit/40e545098e8bb5a18988316331e46c4557378afa
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[clang][CIR] Move CIRGen types into clang::CIRGen (#115385)
https://github.com/llvm/clangir/issues/1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.
Commit: b0c5bb19f3befd4856fdde12cd572af40e121df1
https://github.com/llvm/llvm-project/commit/b0c5bb19f3befd4856fdde12cd572af40e121df1
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Core/BinaryBasicBlock.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/FunctionLayout.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Core/FunctionLayout.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/AArch64/compact-code-model.s
A bolt/test/X86/callcont-fallthru.s
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/ShadowCallStack.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TemplateArgumentVisitor.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/stdalign.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
M clang/test/AST/ast-print-openacc-loop-construct.cpp
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
M clang/test/C/C2y/n3344.c
A clang/test/C/C2y/n3346.c
M clang/test/CXX/temp/temp.res/p4.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/aarch64-cpu-supports-target.c
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/attr-target-x86.c
A clang/test/CodeGen/builtin-counted-by-ref.c
A clang/test/CodeGenHLSL/builtins/WaveActiveCountBits.hlsl
M clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/clamp.hlsl
M clang/test/Driver/XRay/xray-shared.cpp
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
M clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
M clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-features.c
M clang/test/Driver/x86-target-features.c
M clang/test/Misc/warning-flags.c
A clang/test/Modules/prune-non-affecting-module-map-repeated.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-target-clones-aarch64.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
M clang/test/Sema/declspec.c
A clang/test/SemaHLSL/BuiltIns/WaveActiveCountBits-errors.hlsl
M clang/test/SemaOpenACC/compute-construct-async-clause.c
M clang/test/SemaOpenACC/compute-construct-attach-clause.c
M clang/test/SemaOpenACC/compute-construct-copy-clause.c
M clang/test/SemaOpenACC/compute-construct-copyin-clause.c
M clang/test/SemaOpenACC/compute-construct-copyout-clause.c
M clang/test/SemaOpenACC/compute-construct-create-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-no_create-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.c
M clang/test/SemaOpenACC/compute-construct-num_workers-clause.c
M clang/test/SemaOpenACC/compute-construct-present-clause.c
M clang/test/SemaOpenACC/compute-construct-self-clause.c
M clang/test/SemaOpenACC/compute-construct-vector_length-clause.c
M clang/test/SemaOpenACC/compute-construct-wait-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-ast.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-ast.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-clause.cpp
M clang/test/SemaOpenACC/loop-construct-private-clause.c
M clang/test/SemaOpenACC/loop-construct-private-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-ast.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-tile-ast.cpp
M clang/test/SemaOpenACC/loop-construct-tile-clause.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-clause.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-clause.cpp
A clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/SemaOpenACC/loop-loc-and-stmt.c
M clang/test/SemaOpenACC/loop-loc-and-stmt.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/www/c_status.html
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_trampoline_AArch64.S
M compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
M compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
M compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
M compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
M compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/target-loop-unparse.f90
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
A flang/test/Semantics/OpenMP/loop-bind.f90
M flang/test/Semantics/OpenMP/nested-distribute.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
A libc/src/math/exp10m1f.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/exp10m1f.cpp
M libc/src/math/generic/explogxf.h
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/exp10m1f_test.cpp
A libc/test/src/math/exp10m1f_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/exp10m1f_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libcxx/docs/UserDocumentation.rst
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
M lld/COFF/PDB.cpp
M lld/COFF/Writer.cpp
M lld/ELF/Thunks.cpp
A lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/cfguard-off-instrumented.s
M lldb/include/lldb/Utility/ArchSpec.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/source/Plugins/ABI/CMakeLists.txt
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
A lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
A lldb/source/Plugins/ABI/LoongArch/CMakeLists.txt
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/test/API/commands/target/basic/TestTargetCommand.py
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/STLFunctionalExtras.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Coroutines/CoroAnnotationElide.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/M68k/M68kSubtarget.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
A llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroAnnotationElide.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/arm64-fpenv.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
A llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
A llvm/test/CodeGen/DirectX/WaveActiveCountBits.ll
R llvm/test/CodeGen/DirectX/clamp-vec.ll
M llvm/test/CodeGen/DirectX/clamp.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/large-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/large-static.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fptoi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
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M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveCountBits.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
A llvm/test/CodeGen/SPIRV/opencl/clamp.ll
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/vector-sext.ll
A llvm/test/CodeGen/Xtensa/branch-relaxation.ll
M llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/ELF_LoongArch_relocations.s
A llvm/test/ExecutionEngine/RuntimeDyld/LoongArch/lit.local.cfg
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/test/MC/AArch64/spe.s
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
M llvm/test/ThinLTO/X86/memprof-icp.ll
A llvm/test/Transforms/Coroutines/coro-split-noinline.ll
M llvm/test/Transforms/Coroutines/coro-transform-must-elide.ll
A llvm/test/Transforms/Coroutines/gh114487-crash-in-cgscc.ll
A llvm/test/Transforms/Coroutines/gh114487-non-inlinable.ll
M llvm/test/Transforms/GVN/pr113997.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/isspacep.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/NewGVN/pr113997.ll
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
A llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Instrumentation/BUILD.gn
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/Shape/Transforms/OutlineShapeComputation.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
A mlir/lib/ExecutionEngine/SpirvCpuRuntimeWrappers.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Transforms/Utils/FoldUtils.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/CMakeLists.txt
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Vector/invalid.mlir
A mlir/test/Integration/GPU/SPIRV/double.mlir
A mlir/test/Integration/GPU/SPIRV/lit.local.cfg
A mlir/test/Integration/GPU/SPIRV/simple_add.mlir
A mlir/test/Target/LLVMIR/Import/exact.ll
A mlir/test/Target/LLVMIR/exact.mlir
M mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/lit.cfg.py
R mlir/test/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/test/mlir-spirv-cpu-runner/double.mlir
R mlir/test/mlir-spirv-cpu-runner/lit.local.cfg
R mlir/test/mlir-spirv-cpu-runner/mlir_test_spirv_cpu_runner_c_wrappers.cpp
R mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/CMakeLists.txt
M mlir/tools/mlir-cpu-runner/mlir-cpu-runner.cpp
R mlir/tools/mlir-spirv-cpu-runner/CMakeLists.txt
R mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/smeenai/2/head
Compare: https://github.com/llvm/llvm-project/compare/d6f7f57e206c...b0c5bb19f3be
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