[all-commits] [llvm/llvm-project] 17f3e0: Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonica...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 17f3e00911b860d535f41185e605c47babcc2039
      https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll

  Log Message:
  -----------
  Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"

The increase in fallbacks that was previously reported were not caused
by this change.

Original description:

This matches InstCombine and DAGCombine.

RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.

Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.



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