[all-commits] [llvm/llvm-project] bde3d4: [RISCV] Only allow 5 bit shift amounts in disassem...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
      https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt

  Log Message:
  -----------
  [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)

Fixes 2 old TODOs



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