[all-commits] [llvm/llvm-project] 92a9bc: [AArch64] Add tablegen patterns for fmla index wit...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
      https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
  Author: David Green <david.green at arm.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
    M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll

  Log Message:
  -----------
  [AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)

We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
  `fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
  `fma extract(Rn, 0), Rm, Ra -> fmadd`

The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
  `fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
  `fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`



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