[all-commits] [llvm/llvm-project] afa178: [mlir][LLVM] Add exact flag (#115327)

[lfrenot via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: afa178d36017ab565c33a8639be16355a054b95b
      https://github.com/llvm/llvm-project/commit/afa178d36017ab565c33a8639be16355a054b95b
  Author: lfrenot <leon.frenot at gmail.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
    M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
    M mlir/lib/Target/LLVMIR/ModuleImport.cpp
    M mlir/test/Dialect/LLVMIR/roundtrip.mlir
    A mlir/test/Target/LLVMIR/Import/exact.ll
    A mlir/test/Target/LLVMIR/exact.mlir

  Log Message:
  -----------
  [mlir][LLVM] Add exact flag (#115327)

The implementation is mostly based on the one existing for the nsw and
nuw flags.

If the exact flag is present, the corresponding operation returns a
poison value when the result is not exact. (For a division, if rounding
happens; for a right shift, if a non-zero bit is shifted out.)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications