[all-commits] [llvm/llvm-project] a25d91: [RISCV] Skip DAG combine for bitcast fabs/fneg (#1...

[Gergely Futo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a25d91a164b0a283dd809cf9b4d9442d24173fb7
      https://github.com/llvm/llvm-project/commit/a25d91a164b0a283dd809cf9b4d9442d24173fb7
  Author: Gergely Futo <gergely.futo at hightec-rt.com>
  Date:   2024-11-08 (Fri, 08 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Skip DAG combine for bitcast fabs/fneg (#115325)

Disable the DAG combine for bitcast fabs/fneg in case of the zdinx
extension.

The combine folds the fabs/fneg nodes in some cases. This might result
in suboptimal code if compiled with the zdinx extension. In case of the
zdinx extension, there is no need to load the double value from an x
register to an f register, so the combine can be skipped.



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