[all-commits] [llvm/llvm-project] de41b1: [Offload] Provide a CMake cache file to easily bui...
Yuxuan Chen via All-commits
all-commits at lists.llvm.org
Thu Nov 7 14:42:55 PST 2024
Branch: refs/heads/users/yuxuanchen1997/coro-respect-noinline
Home: https://github.com/llvm/llvm-project
Commit: de41b137ddb68b5172f1ab042b0b0b495afbb490
https://github.com/llvm/llvm-project/commit/de41b137ddb68b5172f1ab042b0b0b495afbb490
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A offload/cmake/caches/Offload.cmake
M openmp/docs/SupportAndFAQ.rst
Log Message:
-----------
[Offload] Provide a CMake cache file to easily build offloading (#115074)
Summary:
This patch adds a cache file that will automatically enable openpm,
offload, and all the fancy GPU libraries.
Commit: e109c493210572535de25950e7b83f74b8d11a6a
https://github.com/llvm/llvm-project/commit/e109c493210572535de25950e7b83f74b8d11a6a
Author: Pranav Kant <prka at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLFunctionalExtras.h
Log Message:
-----------
Revert "Add clang::lifetimebound annotation to llvm::function_ref (#1… (#115376)
…15019)"
This reverts commit 9f796159f28775b3f93d77e173c1fd3413c2e60e.
This is breaking compiler-rt/lib/sanitizer_common/...
Author knows about the breakage.
Commit: dec38399795a7f238508ee100e5b057165724a60
https://github.com/llvm/llvm-project/commit/dec38399795a7f238508ee100e5b057165724a60
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP][NFC]Add a test with the missed vectorization opportunity for stores with same address
Commit: ae9d0623ad65d84022bb4ed8446b6491451ae575
https://github.com/llvm/llvm-project/commit/ae9d0623ad65d84022bb4ed8446b6491451ae575
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as
fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as
fcvt.s.wu. There are still some regressions that suggest we should match
g_zero_extend in zexti32.
Commit: 7475156d49406785a974b1205d11fe3de9c1553e
https://github.com/llvm/llvm-project/commit/7475156d49406785a974b1205d11fe3de9c1553e
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
A clang/test/CodeGen/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
Log Message:
-----------
[Clang] Add __builtin_counted_by_ref builtin (#114495)
The __builtin_counted_by_ref builtin is used on a flexible array
pointer and returns a pointer to the "counted_by" attribute's COUNT
argument, which is a field in the same non-anonymous struct as the
flexible array member. This is useful for automatically setting the
count field without needing the programmer's intervention. Otherwise
it's possible to get this anti-pattern:
ptr = alloc(<ty>, ..., COUNT);
ptr->FAM[9] = 42; /* <<< Sanitizer will complain */
ptr->count = COUNT;
To prevent this anti-pattern, the user can create an allocator that
automatically performs the assignment:
#define alloc(TY, FAM, COUNT) ({ \
TY __p = alloc(get_size(TY, COUNT)); \
if (__builtin_counted_by_ref(__p->FAM)) \
*__builtin_counted_by_ref(__p->FAM) = COUNT; \
__p; \
})
The builtin's behavior is heavily dependent upon the "counted_by"
attribute existing. It's main utility is during allocation to avoid
the above anti-pattern. If the flexible array member doesn't have that
attribute, the builtin becomes a no-op. Therefore, if the flexible
array member has a "count" field not referenced by "counted_by", it
must be set explicitly after the allocation as this builtin will
return a "nullptr" and the assignment will most likely be elided.
---------
Co-authored-by: Bill Wendling <isanbard at gmail.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
https://github.com/llvm/llvm-project/commit/bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)
Enable pattern matching from "x<<32-y>>32-y" to "bfe x, 0, y" when we
know y is in [0,31].
This is the follow-up for the PR:
https://github.com/llvm/llvm-project/pull/114279 to fix the issue:
https://github.com/llvm/llvm-project/issues/114282
Commit: 62db1c8a076c7167e404412182f4a8915f4ff6ee
https://github.com/llvm/llvm-project/commit/62db1c8a076c7167e404412182f4a8915f4ff6ee
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
Log Message:
-----------
[SLP]Better decision making on whether to try stores packs for vectorization
Since the stores are sorted by distance, comparing the indices in the
original array and early exit, if the index is less than the index of
the last store, not always the best strategy. Better to remove such
stores explicitly to try better to check for the vectorization
opportunity.
Fixes #115008
Commit: c02da382471fd0b338af76ce220e9567e3cb854a
https://github.com/llvm/llvm-project/commit/c02da382471fd0b338af76ce220e9567e3cb854a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
Log Message:
-----------
[RISCV] Add tests for deinterleave(2-8) shuffles
Commit: 02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
https://github.com/llvm/llvm-project/commit/02668f60a9b5c0d5b8b6e60b4e897f763ad59a91
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Match single source deinterleave shuffles for vnsrl (#114878)
We had previously only been matching the two source case where both
sources came from a wider source type. We can also match the single
source case - provided the result is m4 or smaller because we will need
a wider type to represent the source.
The main goal of this to ensure that vnsrl matching is robust to a
possible change in canonicalization for length changing shuffles that
I'm considering, but it has the nice effect of picking up a few cases we
missed along the way.
Commit: e189d61924ba0165b3a344c3d945b3e2aa373485
https://github.com/llvm/llvm-project/commit/e189d61924ba0165b3a344c3d945b3e2aa373485
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
A llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Add extractCallsFromIR (#115218)
This patch adds extractCallsFromIR, a function to extract calls from
the IR, which will be used to undrift call site locations in the
MemProf profile.
In a nutshell, the MemProf undrifting works as follows:
- Extract call site locations from the IR.
- Extract call site locations from the MemProf profile.
- Undrift the call site locations with longestCommonSequence.
This patch implements the first bullet point above. Specifically,
given the IR, the new function returns a map from caller GUIDs to
lists of corresponding call sites. For example:
Given:
foo() {
f1();
f2(); f3();
}
extractCallsFromIR returns:
Caller: foo ->
{{(Line 1, Column 3), Callee: f1},
{(Line 2, Column 3), Callee: f2},
{(Line 2, Column 9), Callee: f3}}
where the line numbers, relative to the beginning of the caller, and
column numbers are sorted in the ascending order. The value side of
the map -- the list of call sites -- can be directly passed to
longestCommonSequence.
To facilitate the review process, I've only implemented basic features
in extractCallsFromIR in this patch.
- The new function extracts calls from the LLVM "call" instructions
only. It does not look into the inline stack.
- It does not recognize or treat heap allocation functions in any
special way.
I will address these missing features in subsequent patches.
Commit: 53e49f15ab0b9b03e5671faea6f7870914b8f0ea
https://github.com/llvm/llvm-project/commit/53e49f15ab0b9b03e5671faea6f7870914b8f0ea
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
Log Message:
-----------
[clang][serialization] Pass `ASTContext` explicitly (#115235)
This patch removes `ASTWriter::Context` and starts passing `ASTContext
&` explicitly to functions that actually need it. This is a
non-functional change with the end-goal of being able to write
lightweight PCM files with no `ASTContext` at all.
Commit: 0d4250f96014fec29788fa15e45f0a45f462eea9
https://github.com/llvm/llvm-project/commit/0d4250f96014fec29788fa15e45f0a45f462eea9
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
A clang/test/AST/ast-print-builtin-counted-by-ref.c
A clang/test/CodeGen/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.c
A clang/test/Sema/builtin-counted-by-ref.cpp
M llvm/include/llvm/ADT/STLFunctionalExtras.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/repeated-address-store.ll
M llvm/unittests/Transforms/Instrumentation/CMakeLists.txt
A llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
A offload/cmake/caches/Offload.cmake
M openmp/docs/SupportAndFAQ.rst
Log Message:
-----------
Merge branch 'main' into users/yuxuanchen1997/coro-respect-noinline
Compare: https://github.com/llvm/llvm-project/compare/2603db7ce6bf...0d4250f96014
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