[all-commits] [llvm/llvm-project] ae9d06: [RISCV][GISel] Remove s32 input support for G_SITO...
Craig Topper via All-commits
all-commits at lists.llvm.org
Thu Nov 7 13:57:33 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: ae9d0623ad65d84022bb4ed8446b6491451ae575
https://github.com/llvm/llvm-project/commit/ae9d0623ad65d84022bb4ed8446b6491451ae575
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-07 (Thu, 07 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-itofp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-f16-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/itofp-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as
fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as
fcvt.s.wu. There are still some regressions that suggest we should match
g_zero_extend in zexti32.
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