[all-commits] [llvm/llvm-project] 87feaf: [RISCV][GISel] Custom promote s32 G_ROTL/ROTR on R...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 87feafc391ab1e35997994ad378af727e4947c67
      https://github.com/llvm/llvm-project/commit/87feafc391ab1e35997994ad378af727e4947c67
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll

  Log Message:
  -----------
  [RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)

I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.

RORW/ROLW target opcodes are added to match SelectionDAG.

The regression in rv64zbb-zbkb.ll requires factoring
isSExtCheaperThanZExt into the G_ANYEXT constant folder. That requires
some interface changes so I didn't do it in this patch.



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