[all-commits] [llvm/llvm-project] e8b70e: [TableGen] Make `!and` and `!or` short-circuit (#1...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e8b70e97447dc0d93a277b0373345d3a1bae1aa9
      https://github.com/llvm/llvm-project/commit/e8b70e97447dc0d93a277b0373345d3a1bae1aa9
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/docs/TableGen/ProgRef.rst
    M llvm/lib/TableGen/Record.cpp
    M llvm/test/TableGen/true-false.td

  Log Message:
  -----------
  [TableGen] Make `!and` and `!or` short-circuit (#113963)

The idea is that by preemptively simplifying the result of `!and` and `!or`, we can fold
some of the conditional operators, like `!if` or `!cond`, as early as
possible.



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