[all-commits] [llvm/llvm-project] 9f0295: [ARM] Allow spilling FPSCR for MVE adc/sbc intrins...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f02950a1589ebfc542f4f5a2475c2cc03e4e2e9
      https://github.com/llvm/llvm-project/commit/9f02950a1589ebfc542f4f5a2475c2cc03e4e2e9
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    A llvm/test/CodeGen/Thumb2/mve-vadc-vsbc-spill.ll

  Log Message:
  -----------
  [ARM] Allow spilling FPSCR for MVE adc/sbc intrinsics (#115174)

The MVE VADC and VSBC instructions read and write a carry bit in FPSCR,
which is exposed through the intrinsics. This makes it possible to write
code which has the FPSCR live across a function call, or which uses the
same value twice, so it needs to be possible to spill and reload it.

There is a missed optimisation in one of the test cases, where we reload
the FPSCR from the stack despite it still being live, I've not found a
simple way to prevent the register allocator from doing this.



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