[all-commits] [llvm/llvm-project] 1b0106: [NVPTX] Add TMA bulk tensor copy intrinsics (#96083)

[Durgadoss R via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1b01064faad2cd93c516341cfaf047b7a0f8da42
      https://github.com/llvm/llvm-project/commit/1b01064faad2cd93c516341cfaf047b7a0f8da42
  Author: Durgadoss R <durgadossr at nvidia.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/docs/NVPTXUsage.rst
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
    A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll

  Log Message:
  -----------
  [NVPTX] Add TMA bulk tensor copy intrinsics (#96083)

This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.S2G.1D -> 5D variants, supporting both Tile and
   Im2Col modes. These intrinsics optionally support cache_hints as
   indicated by the boolean flag argument.
* cp.async.bulk.tensor.G2S.1D -> 5D variants, with support for both Tile
  and Im2Col modes. The Im2Col variants have an extra set of offsets as
  parameters. These intrinsics optionally support multicast and cache_hints,
  as indicated by the boolean arguments at the end of the intrinsics.
* The backend looks through these flag arguments and lowers to the
   appropriate PTX instruction.
* Lit tests are added for all combinations of these intrinsics in
  cp-async-bulk-tensor-g2s/s2g.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
  https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-tensor

Signed-off-by: Durgadoss R <durgadossr at nvidia.com>



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