[all-commits] [llvm/llvm-project] 343a81: [RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as le...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 343a810725f27bfe92fbd04a42d42aa9caaee7a6
      https://github.com/llvm/llvm-project/commit/343a810725f27bfe92fbd04a42d42aa9caaee7a6
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll

  Log Message:
  -----------
  [RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal strided access (#115264)

This is also split off from the zvfhmin/zvfbfmin
isLegalElementTypeForRVV work.

Enabling this will cause SLP and RISCVGatherScatterLowering to emit
@llvm.experimental.vp.strided.{load,store} intrinsics, and codegen
support for this was added in #109387 and #114750.



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