[all-commits] [llvm/llvm-project] f0e230: [RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as le...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f0e2301b7c3f2576a4fbc53441e9378b966e21ef
      https://github.com/llvm/llvm-project/commit/f0e2301b7c3f2576a4fbc53441e9378b966e21ef
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Allow f16/bf16 with zvfhmin/zvfbfmin as legal interleaved access (#115257)

This is another piece split off from the work to add zvfhmin/zvfbfmin to
isLegalElementTypeForRVV.
This is needed to get InterleavedAccessPass to lower [de]interleaves to
segment load/stores.



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