[all-commits] [llvm/llvm-project] 7ef7c0: [RISCV] Refine vector division latencies in SiFive...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4
      https://github.com/llvm/llvm-project/commit/7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-11-06 (Wed, 06 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s

  Log Message:
  -----------
  [RISCV] Refine vector division latencies in SiFive P600's scheduling model (#115038)

For both vector integer and floating point divisions.

Co-authored-by: Yeting Kuo <yeting.kuo at sifive.com>



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