[all-commits] [llvm/llvm-project] b5d8a0: [AArch64] Add missing ASIMD FP convert instruction...

[Rin Dobrescu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5d8a03de453b79ca3c0bf841931bcaacf2fc830
      https://github.com/llvm/llvm-project/commit/b5d8a03de453b79ca3c0bf841931bcaacf2fc830
  Author: Rin Dobrescu <irina.dobrescu at arm.com>
  Date:   2024-11-06 (Wed, 06 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s

  Log Message:
  -----------
  [AArch64] Add missing ASIMD FP convert instructions to scheduling model (#115146)

Some ASIMD FP convert instructions have incorrect scheduling
information. These instructions currently have latency 2, throughput 4
and utilise pipeline V. This patch corrects the scheduling models to
match the relevant Software Optimization Guide.

The V1 and V2 Software Optimization Guide show that ASIMD FP convert
instructions should all utilise pipelines V02. Their execution latency
and throughput should also differ depending on form. See section 3.17
"ASIMD floating-point instructions" in the Neoverse-V1 and Neoverse-V2
Software Optimization Guide for characteristics of instruction
performance.

Reference:
- V1 SOG: https://developer.arm.com/documentation/109897/latest/
- V2 SOG: https://developer.arm.com/documentation/109898/latest/



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