[all-commits] [llvm/llvm-project] 37ce18: [RISCV] Add requirement of asserts

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 37ce18951fded6be1de319b05b968918cb45c00b
      https://github.com/llvm/llvm-project/commit/37ce18951fded6be1de319b05b968918cb45c00b
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-06 (Wed, 06 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/misched-mem-clustering.mir

  Log Message:
  -----------
  [RISCV] Add requirement of asserts

We forgot to add `REQUIRES: asserts` here.



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