[all-commits] [llvm/llvm-project] a90520: [RISCV] Prefer strided load for interleave load wi...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a905203b9ea5ff1b68ca5ab760d6101f64ff3362
      https://github.com/llvm/llvm-project/commit/a905203b9ea5ff1b68ca5ab760d6101f64ff3362
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [RISCV] Prefer strided load for interleave load with only one lane active (#115069)

If only one of the elements is actually used, then we can legally use a
strided load in place of the segment load. Doing so reduces vector
register pressure, so if both segment and strided are believed to be
element/segment at a time, then prefer the strided load variant.

Note that I've seen the vectorizer emitting wide interleave loads to
represent a strided load, so this does happen in practice. It doesn't
matter much for small LMUL*NF, but at large NF can start causing
problems in register allocation.

Note that this patch only covers the fixed vector formation cases. In
theory, we should do the same patch for scalable, but we can currently
only represent NF2 in scalable IR, and NF2 is assumed to be optimized to
better than segment-at-a-time by default, so there's currently nothing
to do.



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