[all-commits] [llvm/llvm-project] 963003: [SelectionDAGBuilder][X86] Don't form FMAXNUM for ...

[Nikolas Klauser via All-commits]

  Branch: refs/heads/users/rampitec/11-04-_amdgpu_simplify_dpp_builtin_handling
  Home:   https://github.com/llvm/llvm-project
  Commit: 9630036835ddaa83170b43dd0e947537ee43250e
      https://github.com/llvm/llvm-project/commit/9630036835ddaa83170b43dd0e947537ee43250e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    A llvm/test/CodeGen/X86/pr114520.ll

  Log Message:
  -----------
  [SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors if FMAXNUM needs to be promoted. (#114943)

In #70357, I changed a isLegalOrCustom to isLegalOrCustomOrPromote in
visitSelect to enable integer min/max to be formed when the operation
was promoted. Unfortunately, this also affected floating point. For
floating point, fmaxnum may require a libcall so we also need to check
if the operation on the promoted type is legal or custom.

Other changes to RISC-V have seen made the original change untested so
this patch restores the original isLegalOrCustom.

Fixes #114520.


  Commit: 94b9e357fe374dedc3d9df0249520c2f1555510b
      https://github.com/llvm/llvm-project/commit/94b9e357fe374dedc3d9df0249520c2f1555510b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV][GISel] Copy some Zbb and Zbkb IR tests. NFC

These are copies of SDAG tests with some of the more specialized
cases removed. We can add them later when we're ready to improve them.


  Commit: 5696fd23ce62eb15492d216cfd3f5afa4a46ccff
      https://github.com/llvm/llvm-project/commit/5696fd23ce62eb15492d216cfd3f5afa4a46ccff
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCombine.td
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll

  Log Message:
  -----------
  [RISCV][GISel] Enable commute_constant_to_rhs in RISCVPostLegalizerCombiner.


  Commit: 6f42c25c7b244ab97df3f906ed7cb019d0fb5958
      https://github.com/llvm/llvm-project/commit/6f42c25c7b244ab97df3f906ed7cb019d0fb5958
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

  Log Message:
  -----------
  [RISCV][GISel] Use boolean predicated legalization action methods to simplify code. NFC (#115063)

These allow us to pass a subtarget feature to conditionally enable the
legalization action.

These were added by a3010c77910c706be4c51ce4a95d51211e335a1f and are
used by AArch64.


  Commit: d9f965654eaafc4d388144c7328a2b0eb65f8002
      https://github.com/llvm/llvm-project/commit/d9f965654eaafc4d388144c7328a2b0eb65f8002
  Author: Nikolas Klauser <nikolasklauser at berlin.de>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M libcxx/include/__flat_map/flat_map.h
    M libcxx/test/libcxx/transitive_includes/cxx03.csv
    M libcxx/test/libcxx/transitive_includes/cxx11.csv
    M libcxx/test/libcxx/transitive_includes/cxx14.csv
    M libcxx/test/libcxx/transitive_includes/cxx17.csv
    M libcxx/test/libcxx/transitive_includes/cxx20.csv
    M libcxx/test/libcxx/transitive_includes/cxx23.csv
    M libcxx/test/libcxx/transitive_includes/cxx26.csv

  Log Message:
  -----------
  [libc++] Remove <string> and <vector> includes from <flat_map> (#114876)

`<string>` doesn't seem to be required at all and `flat_map` doesn't
support `vector<bool>`, so we can include just `vector<T>`. This cuts
the include time in half on my system.


Compare: https://github.com/llvm/llvm-project/compare/50a473be4267...d9f965654eaa

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