[all-commits] [llvm/llvm-project] a6fdfe: [compiler-rt] Include stdlib.h for exit() (#115025)
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Nov 5 14:05:46 PST 2024
Branch: refs/heads/users/vitalybuka/spr/nfctsan-eliminate-a-few-macros
Home: https://github.com/llvm/llvm-project
Commit: a6fdfefbd04d2b85ba6c23def5790b735c075314
https://github.com/llvm/llvm-project/commit/a6fdfefbd04d2b85ba6c23def5790b735c075314
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerExtFunctionsWindows.cpp
Log Message:
-----------
[compiler-rt] Include stdlib.h for exit() (#115025)
It was originally included transitively, but no longer is after recent
<vector> cleanups in libc++.
Similar to #113951.
Commit: 3297858c19f3914513041d2c8407bc26c889793a
https://github.com/llvm/llvm-project/commit/3297858c19f3914513041d2c8407bc26c889793a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/tools/llvm-readobj/ObjDumper.cpp
Log Message:
-----------
[llvm-readobj] Use heterogenous lookups with std::map (NFC) (#114929)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 8b8778bae5aab471e426632c755fff1fff0ec979
https://github.com/llvm/llvm-project/commit/8b8778bae5aab471e426632c755fff1fff0ec979
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Log Message:
-----------
[WebAssembly] Use heterogenous lookups with std::set (NFC) (#114930)
Commit: 665dd23a2a9e6a7694b80ad3f333327dc4fe00f5
https://github.com/llvm/llvm-project/commit/665dd23a2a9e6a7694b80ad3f333327dc4fe00f5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
Log Message:
-----------
[Utils] Simplify code with DenseMap::operator[] (NFC) (#114932)
Commit: e28d44086f9d23b2aa6e4ae563bd4932b382477b
https://github.com/llvm/llvm-project/commit/e28d44086f9d23b2aa6e4ae563bd4932b382477b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/tools/clang-refactor/TestSupport.cpp
Log Message:
-----------
[clang-refactor] Simplify code with std::map::operator[] (NFC) (#114933)
Commit: 380fd09d982eb199e3c79834fc0f6dc92eb90239
https://github.com/llvm/llvm-project/commit/380fd09d982eb199e3c79834fc0f6dc92eb90239
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
A llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
Log Message:
-----------
[WebAssembly] Fix unwind mismatches in new EH (#114361)
This fixes unwind mismatches for the new EH spec.
The main flow is similar to that of the legacy EH's unwind mismatch
fixing. The new EH shared `fixCallUnwindMismatches` and
`fixCatchUnwindMismatches` functions, which gather the range of
instructions we need to fix their unwind destination for, with the
legacy EH. But unlike the legacy EH that uses `try`-`delegate`s to fix
them, the new EH wrap those instructions with nested
`try_table`-`end_try_table`s that jump to a "trampoline" BB, where we
rethrow (using a `throw_ref`) the exception to the correct `try_table`.
For a simple example of a call unwind mismatch, suppose if `call foo`
should unwind to the outer `try_table` but is wrapped in another
`try_table` (not shown here):
```wast
try_table
...
call foo ;; Unwind mismatch. Should unwind to the outer try_table
...
end_try_table
```
Then we wrap the call with a new nested `try_table`-`end_try_table`, add
a `block` / `end_block` right inside the target `try_table`, and make
the nested `try_table` jump to it using a `catch_all_ref` clause, and
rethrow the exception using a `throw_ref`:
```wast
try_table
block $l0 exnref
...
try_table (catch_all_ref $l0)
call foo
end_try_table
...
end_block ;; Trampoline BB
throw_ref
end_try_table
```
---
This fixes two existing bugs. These are not easy to test independently
without the unwind mismatch fixing. The first one is how we calculate
`ScopeTops`. Turns out, we should do it in the same way as in the legacy
EH even though there is no `end_try` at the end of `catch` block
anymore. `nested_try` in `cfg-stackify-eh.ll` tests this case.
The second bug is in `rewriteDepthImmediates`. `try_table`'s immediates
should be computed without the `try_table` itself, meaning
```wast
block
try_table (catch ... 0)
end_try_table
end_block
```
Here 0 should target not `end_try_table` but `end_block`. This bug
didn't crash the program because `placeTryTableMarker` generated only
the simple form of `try_table` that has a single catch clause and an
`end_block` follows right after the `end_try_table` in the same BB, so
jumping to an `end_try_table` is the same as jumping to the `end_block`.
But now we generate `catch` clauses with depths greater than 0 with when
fixing unwind mismatches, which uncovered this bug.
---
One case that needs a special treatment was when `end_loop` precedes an
`end_try_table` within a BB and this BB is a (true) unwind destination
when fixing unwind mismatches. In this case we need to split this
`end_loop` into a predecessor BB. This case is tested in
`unwind_mismatches_with_loop` in `cfg-stackify-eh.ll`.
---
`cfg-stackify-eh.ll` contains mostly the same set of tests with the
existing `cfg-stackify-eh-legacy.ll` with the updated FileCheck
expectations. As in `cfg-stackify-eh-legacy.ll`, the FileCheck lines
mostly only contain control flow instructions and calls for readability.
- `nested_try` and `unwind_mismatches_with_loop` are added to test newly
found bugs in the new EH.
- Some tests in `cfg-stackify-eh-legacy.ll` about the legacy-EH-specific
asepcts have not been added to `cfg-stackify-eh.ll`.
(`remove_unnecessary_instrs`, `remove_unnecessary_br`,
`fix_function_end_return_type_with_try_catch`, and
`branch_remapping_after_fixing_unwind_mismatches_0/1`)
Commit: b14c436311e3ff78f61dd59c90486432d13bf38e
https://github.com/llvm/llvm-project/commit/b14c436311e3ff78f61dd59c90486432d13bf38e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/include/sanitizer/tsan_interface_atomic.h
M compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
Revert "[tsan] Don't use `enum __tsan_memory_order` in tsan interface" (#115032)
Reverts llvm/llvm-project#114724
Breaks OSX builds
Commit: 6a263cef2d6a38f92265e819310bc60bb2ba49ee
https://github.com/llvm/llvm-project/commit/6a263cef2d6a38f92265e819310bc60bb2ba49ee
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp:202:2:
error: extra ';' outside of a function is incompatible with C++98
[-Werror,-Wc++98-compat-extra-semi]
Commit: c8221359f0507a12d6b1159ab85ba768960cbd3f
https://github.com/llvm/llvm-project/commit/c8221359f0507a12d6b1159ab85ba768960cbd3f
Author: Pranav Kant <prka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Add dep on Analysis to fix build break (#115033)
Commit: dbb4858a8c0cd883ff4e4d5df20152c4b295b909
https://github.com/llvm/llvm-project/commit/dbb4858a8c0cd883ff4e4d5df20152c4b295b909
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[mlir] Fix warnings
This patch fixes:
mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp:137:8:
error: unused variable 'vectorType' [-Werror,-Wunused-variable]
mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp:154:8:
error: unused variable 'srcType' [-Werror,-Wunused-variable]
mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp:155:8:
error: unused variable 'destType' [-Werror,-Wunused-variable]
Commit: b509eb7740b3300b79b90f8a43c374e28d13dc48
https://github.com/llvm/llvm-project/commit/b509eb7740b3300b79b90f8a43c374e28d13dc48
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
A clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
Log Message:
-----------
[HLSL] add IsTypedResourceElementCompatible type trait (#114864)
This PR implements a new type trait as a builtin,
__builtin_hlsl_is_typed_resource_element_compatible
This type traits verifies that the given input type is suitable as a
typed resource element type.
It checks that the given input type is homogeneous, has no more than 4
sub elements, does not exceed 16 bytes, and does not contain any arrays,
booleans, or enums.
Fixes an issue in https://github.com/llvm/llvm-project/pull/113730 that
needed to cause that PR to be reverted.
Fixes https://github.com/llvm/llvm-project/issues/113223
Commit: 76f993b6f66822e5067fa22bc645b6f51f860710
https://github.com/llvm/llvm-project/commit/76f993b6f66822e5067fa22bc645b6f51f860710
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
R libcxx/test/support/experimental_any_helpers.h
Log Message:
-----------
[libc++][NFC] Remove unused header in test/support
Commit: 5f8b83e40cfe36c376e44ef4459becb64458cdba
https://github.com/llvm/llvm-project/commit/5f8b83e40cfe36c376e44ef4459becb64458cdba
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/depobj-construct-v50.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
Log Message:
-----------
[flang][OpenMP] Deprecation message for DESTROY with no argument (#114988)
[5.2:625:17] The syntax of the DESTROY clause on the DEPOBJ construct
with no argument was deprecated.
Commit: ff5551cdb07f07e15900be3593c56c5760f8dd38
https://github.com/llvm/llvm-project/commit/ff5551cdb07f07e15900be3593c56c5760f8dd38
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
A clang/include/clang/AST/DynamicRecursiveASTVisitor.h
M clang/lib/AST/CMakeLists.txt
A clang/lib/AST/DynamicRecursiveASTVisitor.cpp
Log Message:
-----------
[Clang] [NFC] Introduce `DynamicRecursiveASTVisitor` (#110040)
See #105195 as well as the big comment in DynamicRecursiveASTVisitor.cpp
for more context.
Commit: 02e5c25f62d33202be6cca2650d3ae60c896775f
https://github.com/llvm/llvm-project/commit/02e5c25f62d33202be6cca2650d3ae60c896775f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] SimplifyDemandedBitsForTargetNode - cleanup SSE shift-by-immediate handlers. NFC.
Cleanup the SHLI/SRLI/SRAI handlers to be more consistent - prep for a future patch.
Commit: 61d5addd942a5ef8128e48d3617419e6320d8280
https://github.com/llvm/llvm-project/commit/61d5addd942a5ef8128e48d3617419e6320d8280
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
Log Message:
-----------
[X86] SimplifyDemandedBitsForTargetNode - call SimplifyMultipleUseDemandedBits on SSE shift-by-immediate nodes.
Attempt to peek through multiple-use SHLI/SRLI/SRAI source vectors.
Commit: 04aaa35d40d8c5ff030014866691f9a56e59c142
https://github.com/llvm/llvm-project/commit/04aaa35d40d8c5ff030014866691f9a56e59c142
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M libc/test/src/__support/OSUtil/linux/vdso_test.cpp
M libc/test/src/__support/integer_literals_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_long_double_test.cpp
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/msync_test.cpp
M libc/test/src/sys/mman/linux/shm_test.cpp
M libc/test/src/unistd/access_test.cpp
Log Message:
-----------
[libc][NFC] Correct test header inclusion, license (#114604)
Some tests were including LibcTest.h directly. Instead you should
include Test.h which does proper indirection for other test frameworks
we support (zxtest, gtest). Also added some license headers to tests
that were missing them.
Commit: 3cdac0670823e2da58001bc2600d2e74c929ae5b
https://github.com/llvm/llvm-project/commit/3cdac0670823e2da58001bc2600d2e74c929ae5b
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlsl
A clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/DirectX/dot4add_i8packed.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll
Log Message:
-----------
[HLSL][SPIRV][DXIL] Implement `dot4add_i8packed` intrinsic (#113623)
- create a clang built-in in Builtins.td
- link dot4add_i8packed in hlsl_intrinsics.h
- add lowering to spirv backend through expansion of operation as OPSDot
is missing up to SPIRV 1.6 in SPIRVInstructionSelector.cpp
- add lowering to spirv backend using OpSDot in applicable SPIRV version
or if SPV_KHR_integer_dot_product is enabled
- add dot4add_i8packed intrinsic to IntrinsicsDirectX.td and mapping to
DXIL.td op Dot4AddI8Packed
- add tests for HLSL intrinsic lowering to dx/spv intrinsic in
dot4add_i8packed.hlsl
- add tests for sema checks in dot4add_i8packed-errors.hlsl
- add test of spir-v lowering in SPIRV/dot4add_i8packed.ll
- add test to dxil lowering in DirectX/dot4add_i8packed.ll
Resolves #99220
Commit: e952728f88c8b0e0208dc991dd9a04fe8c211cfb
https://github.com/llvm/llvm-project/commit/e952728f88c8b0e0208dc991dd9a04fe8c211cfb
Author: walter erquinigo <walter at modular.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/commands/process/launch/TestProcessLaunch.py
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[LLDB] Retry Add a target.launch-working-dir setting
This retries the PR 113521 skipping a test in a remote environment.
Commit: 23a01a413d29f2d5b1f6204d0237e3884ae0231e
https://github.com/llvm/llvm-project/commit/23a01a413d29f2d5b1f6204d0237e3884ae0231e
Author: jimingham <jingham at apple.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py
Log Message:
-----------
More refinement of call site handling in stepping. (#114628)
When you set a "next branch breakpoint" and run to it while stepping,
you have to claim the stop at that breakpoint to be the top of the
inlined call stack, or you will seem to "step in" and then plans might
try to step back out again.
This records the PrefferedLineEntry for next branch breakpoints and adds
a test to make sure this works.
Commit: 7780cf01e2c6912684fae10d68f76d7d5a21d675
https://github.com/llvm/llvm-project/commit/7780cf01e2c6912684fae10d68f76d7d5a21d675
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
Log Message:
-----------
[AMDGPU][MC] Fix disassemble of image_gather4 with d16 (#114609)
For GFX10+, image_gather4 instructions that have v[254:255] as dst reg
and the d16 bit on can be assembled correctly but the generated binary
fails to disassemble (e.g. image_gather4 v[254:255], v[1:2], s[8:15], s[12:15]
dmask:0x8 dim:SQ_RSRC_IMG_2D d16). This patch fixes this problem.
Commit: bac7a6b390c0b9d195089d5b211949a25ffdf20c
https://github.com/llvm/llvm-project/commit/bac7a6b390c0b9d195089d5b211949a25ffdf20c
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps5-linker.c
Log Message:
-----------
[PS5][Driver] Pass `-z rodynamic` to the linker (#115009)
Until now, suppression of `DT_DEBUG` has been hardcoded as a downstream
patch in lld. This can instead be achieved by passing `-z rodynamic`.
Have the driver do this so that the private patch can be removed.
If the scope of lld's `-z rodynamic` is broadened (within reason) to do
more in future, that's likely to be fine as `PT_DYNAMIC` isn't writable
on PlayStation.
PS5 only. On PS4, the equivalent hardcoded configuration will remain in
the proprietary linker.
SIE tracker: TOOLCHAIN-16704
Commit: ce067c5a3b96e009964dc60d6b6a0f4b33c345c7
https://github.com/llvm/llvm-project/commit/ce067c5a3b96e009964dc60d6b6a0f4b33c345c7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
R llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
Log Message:
-----------
AMDGPU: Rename test file
Commit: 592c0fe55f6d9a811028b5f3507be91458ab2713
https://github.com/llvm/llvm-project/commit/592c0fe55f6d9a811028b5f3507be91458ab2713
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Evaluate/fold-real.cpp
M flang/test/Evaluate/errors01.f90
Log Message:
-----------
[flang] Tweak a SCALE/IEEE_SCALB folding overflow warning message (#114994)
Commit: 7c3fdcc27603cd2d6b01fa7b057b3099da75bc8d
https://github.com/llvm/llvm-project/commit/7c3fdcc27603cd2d6b01fa7b057b3099da75bc8d
Author: Artem Belevich <tra at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/CodeGenCUDA/Inputs/cuda.h
A clang/test/CodeGenCUDA/grid-constant.cu
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/SemaCUDA/Inputs/cuda.h
A clang/test/SemaCUDA/grid-constant.cu
Log Message:
-----------
[CUDA] Add support for __grid_constant__ attribute (#114589)
LLVM support for the attribute has been implemented already, so it just
plumbs it through to the CUDA front-end.
One notable difference from NVCC is that the attribute can be used
regardless of the targeted GPU. On the older GPUs it will just be
ignored. The attribute is a performance hint, and does not warrant a
hard error if compiler can't benefit from it on a particular GPU
variant.
Commit: a993dfcdbf64ef7a8bd7e5ec4d97287b650d4f50
https://github.com/llvm/llvm-project/commit/a993dfcdbf64ef7a8bd7e5ec4d97287b650d4f50
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
A flang/test/Transforms/debug-assumed-rank-array.fir
Log Message:
-----------
[flang][debug] Support assumed-rank arrays. (#114404)
The assumed-rank array are represented by DIGenericSubrange in debug
metadata. We have to provide 2 things.
1. Expression to get rank value at the runtime from descriptor.
2. Assuming the dimension number for which we want the array information
has been put on the DWARF expression stack, expressions which will
extract the lowerBound, count and stride information from the descriptor
for the said dimension.
With this patch in place, this is how I see an assumed_rank variable
being evaluated by GDB.
```
function mean(x) result(y)
integer, intent(in) :: x(..)
...
end
program main
use mod
implicit none
integer :: x1,xvec(3),xmat(3,3),xtens(3,3,3)
x1 = 5
xvec = 6
xmat = 7
xtens = 8
print *,mean(xvec), mean(xmat), mean(xtens), mean(x1)
end program main
(gdb) p x
$1 = (6, 6, 6)
(gdb) p x
$2 = ((7, 7, 7) (7, 7, 7) (7, 7, 7))
(gdb) p x
$3 = (((8, 8, 8) (8, 8, 8) (8, 8, 8)) ((8, 8, 8) (8, 8, 8) (8, 8, 8)) ((8, 8, 8) (8, 8, 8) (8, 8, 8)))
(gdb) p x
$4 = 5
```
Commit: 9b9369e0bb0131ba0336d9adb4ef098b6dafc7f4
https://github.com/llvm/llvm-project/commit/9b9369e0bb0131ba0336d9adb4ef098b6dafc7f4
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir][tensor] Improve `FoldTensorCastProducerOp` (dynamic shapes) (#114559)
Currently, `FoldTensorCastProducerOp` incorrectly folds the following:
```mlir
%pack = tensor.pack %src
padding_value(%pad : i32)
inner_dims_pos = [0, 1]
inner_tiles = [%c8, 1]
into %cast : tensor<7x?xi32> -> tensor<1x1x?x1xi32>
%res = tensor.cast %pack : tensor<1x1x?x1xi32> to tensor<1x1x8x1xi32>
```
as (note the static trailing dim in the result and dynamic tile
dimension that corresponds to that):
```mlir
%res = tensor.pack %src
padding_value(%pad : i32)
inner_dims_pos = [0, 1]
inner_tiles = [%c8, 1]
into %cast : tensor<7x?xi32> -> tensor<1x1x8x1xi32>
```
This triggers an Op verification failure and is due to the fact that the
folder does not update the inner tile sizes in the pack Op. This PR
addresses that.
Note, supporting other Ops with size-like attributes is left as a TODO.
Commit: d02d9ce314f823181430e9f21c89806f9227c95f
https://github.com/llvm/llvm-project/commit/d02d9ce314f823181430e9f21c89806f9227c95f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/Tensor/IR/TensorOps.cpp:4781:17: error: unused
variable 'tileSize' [-Werror,-Wunused-variable]
Commit: a33d42ad5f916f5b782076ca84fe565589079c6f
https://github.com/llvm/llvm-project/commit/a33d42ad5f916f5b782076ca84fe565589079c6f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
Log Message:
-----------
[gn build] Port ff5551cdb07f
Commit: c695a32576525b047f92b90de71eb707c152e29c
https://github.com/llvm/llvm-project/commit/c695a32576525b047f92b90de71eb707c152e29c
Author: David Olsen <dolsen at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
A clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CIRGenAction.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CIR/hello.c
Log Message:
-----------
[CIR] Call code gen; create empty cir.func op (#113483)
Finish hooking up ClangIR code gen into the Clang control flow,
initializing enough that basic code gen is possible.
Add an almost empty `cir.func` op to the ClangIR dialect. Currently the
only property of the function is its name. Add the code necessary to
code gen a cir.func op.
Create essentially empty files
clang/lib/CIR/Dialect/IR/{CIRAttrs.cpp,CIRTypes.cpp}. These will be
filled in later as attributes and types are defined in the ClangIR
dialect.
(Part of upstreaming the ClangIR incubator project into LLVM.)
Commit: 803f957e87e4083f6d61c8991171eeeaf0e6bd61
https://github.com/llvm/llvm-project/commit/803f957e87e4083f6d61c8991171eeeaf0e6bd61
Author: jimingham <jingham at apple.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M lldb/source/Symbol/CompileUnit.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpoinsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/common.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/main.cpp
Log Message:
-----------
Fix a thinko in the CallSite handling code: (#114896)
I have to check for the sc list size being changed by the call-site
search, not just that it had more than one element.
Added a test for multiple CU's with the same name in a given module,
which would have caught this mistake.
We were also doing all the work to find call sites when the found decl
and specified decl's only difference was a column, but the incoming
specification hadn't specified a column (column number == 0).
Commit: 17d956588a2cc508acf98574f913eaef6d0e1af3
https://github.com/llvm/llvm-project/commit/17d956588a2cc508acf98574f913eaef6d0e1af3
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/include/sanitizer/tsan_interface_atomic.h
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
Reapply "[tsan] Don't use `enum __tsan_memory_order` in tsan interface"" (#115034)
In C++ it's UB to use undeclared values as enum.
And there is support __ATOMIC_HLE_ACQUIRE and
__ATOMIC_HLE_RELEASE need such values.
So use `int` in TSAN interface, and mask out
irrelevant bits and cast to enum ASAP.
`ThreadSanitizer.cpp` already declare morder parameterd
in these functions as `i32`.
This may looks like a slight change, as we
previously didn't mask out additional bits for `fmo`,
and `NoTsanAtomic` call. But from implementation
it's clear that they are expecting exact enum.
Reverts llvm/llvm-project#115032
Reapply llvm/llvm-project#114724
Commit: db69d6939a93d1e401abe6bfe114e55b69297975
https://github.com/llvm/llvm-project/commit/db69d6939a93d1e401abe6bfe114e55b69297975
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/memory.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Support data transfer from descriptor to a pointer (#115023)
Data transfer from a variable with a descriptor to a pointer. We create
a descriptor for the pointer so we can use the flang runtime to perform
the transfer. The Assign function handles all corner cases. We add a new
entry points `CUFDataTransferDescDescNoRealloc` to avoid reallocation
since the variable on the LHS is not an allocatable.
Commit: e566ae8812af77d4ebfd14f4ebe6055a1f71cc02
https://github.com/llvm/llvm-project/commit/e566ae8812af77d4ebfd14f4ebe6055a1f71cc02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 support for G_ABS on RV64.
I plan to remove s32 as a legal type to match SelectionDAG
and to remove i32 from the GPR regclass on RV64.
Commit: 8b659736f7393314a797b6cf2fa346316a624ecb
https://github.com/llvm/llvm-project/commit/8b659736f7393314a797b6cf2fa346316a624ecb
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
Log Message:
-----------
[SystemZ] Make lit test more specific (#115050)
The lit test fmuladd-soft-float.ll only specifies s390x as platform,
but the test is Linux specific, causing problems when run on z/OS.
This change updates the triple to fix this.
Commit: db1882e2484013066139f0b3f77d968d84a79158
https://github.com/llvm/llvm-project/commit/db1882e2484013066139f0b3f77d968d84a79158
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
M compiler-rt/lib/xray/xray_interface_internal.h
A compiler-rt/lib/xray/xray_s390x.cpp
A compiler-rt/lib/xray/xray_trampoline_s390x.S
M compiler-rt/lib/xray/xray_tsc.h
Log Message:
-----------
[SystemZ][XRay] XRay runtime support for SystemZ (#113252)
Adds the runtime support routines for XRay on SystemZ. Only function
entry/exit is implemented.
Commit: 4a37799a489d80e505e3e20722570c47673476be
https://github.com/llvm/llvm-project/commit/4a37799a489d80e505e3e20722570c47673476be
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSubtarget.h
A llvm/test/CodeGen/SystemZ/xray.ll
Log Message:
-----------
[SystemZ][XRay] Implement XRay instrumentation for SystemZ (#113253)
Expands pseudo instructions PATCHABLE_FUNCTION_ENTER and PATCHABLE_RET
into a small instruction sequence which calls into the XRay library.
Commit: 0c60573d1c2d19133d84da092b240f32e0574be5
https://github.com/llvm/llvm-project/commit/0c60573d1c2d19133d84da092b240f32e0574be5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
clang/AMDGPU: Emit grid size builtins with range metadata (#113038)
These cannot be 0.
Commit: 0b40f979298a2e7d4c3da7c067fc9747d0f93653
https://github.com/llvm/llvm-project/commit/0b40f979298a2e7d4c3da7c067fc9747d0f93653
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
R llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
Log Message:
-----------
AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)
0 does not make sense as a value for this to be, much less the default.
Also stop emitting each individual field if it is the default, rather than
if any element was the default. Also fix the name of the test since it didn't
exactly match the real attribute name.
Commit: 0428f2cb5a91cc93897252c9dc4883efea3dbd9a
https://github.com/llvm/llvm-project/commit/0428f2cb5a91cc93897252c9dc4883efea3dbd9a
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M clang/lib/Driver/XRayArgs.cpp
M clang/test/Driver/XRay/xray-mode-flags.cpp
Log Message:
-----------
[SystemZ][XRay] Enable XRay for SystemZ in clang (#113254)
With the support for xray for SystemZ in place, the option can now be
enabled in clang.
Commit: e8644e3b474136da43344a5afeeae63268f980e1
https://github.com/llvm/llvm-project/commit/e8644e3b474136da43344a5afeeae63268f980e1
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
Log Message:
-----------
[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)
Some old "t16" VOP2 instructions are actually in fake16 format. Correct
and update test file
Commit: fbbd8b0741586794721639715d1d974db56f83ac
https://github.com/llvm/llvm-project/commit/fbbd8b0741586794721639715d1d974db56f83ac
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/lib/Semantics/rewrite-parse-tree.cpp
A flang/test/Semantics/rewrite03.f90
Log Message:
-----------
[flang] Fix rewriting of misparsed statement functions (#112934)
Fortran's syntax is ambiguous for some assignment statements (to array
elements or to the targets of pointers returned by functions) that
appear as the first executable statements in a subprogram or BLOCK
construct. Is A(I)=X a statement function definition at the end of the
specification part, or ar array element assignment statement, or an
assignment to a pointer returned by a function named A?
Since f18 builds a parse tree for the entire source file before
beginning any semantic analysis, we can't tell which is which until
after name resolution, at which point the symbol table has been built.
So we have to walk the parse tree and rewrite some misparsed statement
function definitions that really were assignment statements.
There's a bug in that code, though, due to the fact that the
implementation used state in the parse tree walker to hold a list of
misparsed statement function definitions extracted from one
specification part to be reinserted at the beginning of the next
execution part that is visited; it didn't work for misparsed cases BLOCK
constructs. Their parse tree nodes encapsulate a parser::Block, not an
instance of the wrapper class parser::ExecutionPart. So misparsed
statement functions in BLOCK constructs were being rewritten into
assignment statement that were inserted at the beginning of the
executable part of the following subprogram, if and wherever one
happened to occur. This led to crashes in lowering and much
astonishment.
A simple fix would have been to adjust the rewriting code to always
insert the list at the next visited parser::Block, since
parser::ExecutionPart is just a wrapper around Block anyway; but this
patch goes further to do the "right thing", which is a restructuring of
the rewrite that avoids the use of state and any assumptions about parse
tree walking visitation order.
Fixes https://github.com/llvm/llvm-project/issues/112549.
Commit: 07e053fb95e131244dafab04aae84650de383664
https://github.com/llvm/llvm-project/commit/07e053fb95e131244dafab04aae84650de383664
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/runtime/assign.cpp
Log Message:
-----------
[flang][runtime] Fix finalization case in assignment (#113611)
There were two bugs in derived type array assignment processing that
caused finalization to fail to occur for a test case. The first bug was
an off-by-one error in address overlap testing that caused a false
positive result for the test, whose left-hand side's allocatable's
descriptor was immediately adjacent in memory to the right-hand side's
array's data.
The second bug was that in such overlap cases (even when legitimate)
finalization would fail due to the LHS's descriptor having been copied
to a temporary for deferred deallocation and then nullified.
This patch corrects the overlap analysis for this test, and also
properly finalizes the LHS when overlap does exist. Some nearby dead
code was removed to avoid future confusion.
Fixes https://github.com/llvm/llvm-project/issues/113375.
Commit: 850d42fb145c636a3b56a7616c3e3c5c188c1916
https://github.com/llvm/llvm-project/commit/850d42fb145c636a3b56a7616c3e3c5c188c1916
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Parser/token-sequence.h
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/token-sequence.cpp
A flang/test/Preprocessing/defined-in-macro.F90
Log Message:
-----------
[flang] Handle "defined" in macro expansions (#114844)
The preprocessor implements "defined(X)" and "defined X" in if/elif
directive expressions in such a way that they only work at the top
level, not when they appear in macro expansions. Fix that, which is a
little tricky due to the need to detect the "defined" keyword before
applying any macro expansion to its argument, and add a bunch of tests.
Fixes https://github.com/llvm/llvm-project/issues/114064.
Commit: 97982a8c605fac7c86d02e641a6cd7898b3ca343
https://github.com/llvm/llvm-project/commit/97982a8c605fac7c86d02e641a6cd7898b3ca343
Author: dlav-sc <daniil.avdeev at syntacore.com>
Date: 2024-11-06 (Wed, 06 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/branch-relaxation.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/kcfi-mir.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr58025.ll
M llvm/test/CodeGen/RISCV/pr58286.ll
M llvm/test/CodeGen/RISCV/pr63365.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr88365.ll
M llvm/test/CodeGen/RISCV/prolog-epilogue.ll
M llvm/test/CodeGen/RISCV/push-pop-opt-crash.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvbi.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
M llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
Log Message:
-----------
[RISCV][CFI] add function epilogue cfi information (#110810)
This patch adds CFI instructions in the function epilogue.
Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret
After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret
This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.
Commit: b8ac87f34a6f4405bf8d91339a10f188db30aa3b
https://github.com/llvm/llvm-project/commit/b8ac87f34a6f4405bf8d91339a10f188db30aa3b
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/lib/AsmParser/LLLexer.cpp
A llvm/test/Assembler/c-style-comment.ll
A llvm/test/Assembler/invalid-c-style-comment0.ll
A llvm/test/Assembler/invalid-c-style-comment1.ll
A llvm/test/Assembler/invalid-c-style-comment2.ll
A llvm/test/Assembler/invalid-c-style-comment3.ll
Log Message:
-----------
[LLVM][AsmParser] Add support for C style comments (#111554)
Add support for C style comments in LLVM assembly.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 97262afa6d78bcf332f26a02834b43ac31f87f94
https://github.com/llvm/llvm-project/commit/97262afa6d78bcf332f26a02834b43ac31f87f94
Author: Eric <eric at efcs.ca>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
Allow specifying libcxx builder image. (#110303)
This change attempts to shift the libc++ builders over to new backend
infrastructure that allows running an arbitrary container for the
libc++ job.
This has been a long time in the making, and support from github
and gke is finally at the point where it's possible (hopefully).
This change should also demonstrate another important property:
No Downtime Upgrades.
If this goes well, we'll be able to test the upgrade as a part
of the PR process, and then commiting it to main should (ideally)
not break anything.
Commit: fedb9fdb98314ff0ddff065dbd6ef8b2b7e6ec96
https://github.com/llvm/llvm-project/commit/fedb9fdb98314ff0ddff065dbd6ef8b2b7e6ec96
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M libc/src/sys/socket/linux/recvmsg.cpp
Log Message:
-----------
[libc] Fix sendmsg iovec unpoisoning (#115057)
The unpoisoning for sendmsg had a typo where it would not unpoison all
of the elements in the iovec, causing msan errors. This patch fixes
that.
Commit: a353e258ba495be58263d6cc6e382e6dde298361
https://github.com/llvm/llvm-project/commit/a353e258ba495be58263d6cc6e382e6dde298361
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
M llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
M llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-3.ll
M llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
Log Message:
-----------
[LAA] Don't require Stride == 1/-1 for inbounds pointer AddRecs nowrap. (#113126)
If we have a pointer AddRec, the maximum increment is
2^(pointer-index-wdith - 1) - 1. This means that if incrementing the
AddRec wraps, the distance between the previously accessed location and
the wrapped location is > 2^(pointer-index-wdith - 1), i.e. if the GEP
for the AddRec is inbounds, this would be poison due to the object being
larger than half the pointer index type space. The poison would be
immediate UB when the memory access gets executed..
Similar reasoning can be applied for decrements.
PR: https://github.com/llvm/llvm-project/pull/113126
Commit: 823625cf1d9aba4017a486cfdd3e4b9b94c5ef49
https://github.com/llvm/llvm-project/commit/823625cf1d9aba4017a486cfdd3e4b9b94c5ef49
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[nfc][tsan] Simplify morder conversion (#115075)
All valid values should fit into a byte.
This slightly reduce generated code on x86_64.
Commit: 649df394cd86e2d13c129040f29f459b57bb7eb4
https://github.com/llvm/llvm-project/commit/649df394cd86e2d13c129040f29f459b57bb7eb4
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M clang/docs/ReleaseNotes.rst
A clang/include/clang/AST/DynamicRecursiveASTVisitor.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/CMakeLists.txt
A clang/lib/AST/DynamicRecursiveASTVisitor.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
A clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/IR/CMakeLists.txt
M clang/lib/CIR/FrontendAction/CIRGenAction.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/XRayArgs.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/CIR/hello.c
M clang/test/CodeGenCUDA/Inputs/cuda.h
A clang/test/CodeGenCUDA/grid-constant.cu
A clang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/Driver/XRay/xray-mode-flags.cpp
M clang/test/Driver/ps5-linker.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/SemaCUDA/Inputs/cuda.h
A clang/test/SemaCUDA/grid-constant.cu
A clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl
A clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
A clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
M clang/tools/clang-refactor/TestSupport.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/fuzzer/FuzzerExtFunctionsWindows.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
M compiler-rt/lib/tsan/rtl/tsan_interface.h
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M compiler-rt/lib/xray/CMakeLists.txt
M compiler-rt/lib/xray/xray_interface.cpp
M compiler-rt/lib/xray/xray_interface_internal.h
A compiler-rt/lib/xray/xray_s390x.cpp
A compiler-rt/lib/xray/xray_trampoline_s390x.S
M compiler-rt/lib/xray/xray_tsc.h
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Parser/token-sequence.h
M flang/include/flang/Runtime/CUDA/memory.h
M flang/lib/Evaluate/fold-real.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/token-sequence.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/runtime/CUDA/memory.cpp
M flang/runtime/assign.cpp
M flang/test/Evaluate/errors01.f90
M flang/test/Fir/CUDA/cuda-data-transfer.fir
A flang/test/Preprocessing/defined-in-macro.F90
M flang/test/Semantics/OpenMP/depobj-construct-v50.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
A flang/test/Semantics/rewrite03.f90
A flang/test/Transforms/debug-assumed-rank-array.fir
M libc/src/sys/socket/linux/recvmsg.cpp
M libc/test/src/__support/OSUtil/linux/vdso_test.cpp
M libc/test/src/__support/integer_literals_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_long_double_test.cpp
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/msync_test.cpp
M libc/test/src/sys/mman/linux/shm_test.cpp
M libc/test/src/unistd/access_test.cpp
R libcxx/test/support/experimental_any_helpers.h
M lldb/include/lldb/Target/Target.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/Options.td
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/test/API/commands/process/launch/TestProcessLaunch.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/Makefile
A lldb/test/API/functionalities/breakpoint/same_cu_name/TestFileBreakpoinsSameCUName.py
A lldb/test/API/functionalities/breakpoint/same_cu_name/common.cpp
A lldb/test/API/functionalities/breakpoint/same_cu_name/main.cpp
M lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/AsmParser/LLLexer.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSubtarget.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
M llvm/test/Analysis/LoopAccessAnalysis/evaluate-at-symbolic-max-backedge-taken-count-may-wrap.ll
M llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
A llvm/test/Assembler/c-style-comment.ll
A llvm/test/Assembler/invalid-c-style-comment0.ll
A llvm/test/Assembler/invalid-c-style-comment1.ll
A llvm/test/Assembler/invalid-c-style-comment2.ll
A llvm/test/Assembler/invalid-c-style-comment3.ll
A llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
R llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
R llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
M llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir
A llvm/test/CodeGen/DirectX/dot4add_i8packed.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/stacksave-stackrestore.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/branch-relaxation.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-mem-constraint.ll
M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/kcfi-mir.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr58025.ll
M llvm/test/CodeGen/RISCV/pr58286.ll
M llvm/test/CodeGen/RISCV/pr63365.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr88365.ll
M llvm/test/CodeGen/RISCV/prolog-epilogue.ll
M llvm/test/CodeGen/RISCV/push-pop-opt-crash.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll
M llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr93587.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/stack-inst-compress.mir
M llvm/test/CodeGen/RISCV/stack-offset.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvbi.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
M llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll
M llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
A llvm/test/CodeGen/SystemZ/xray.ll
A llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
M llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
M llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-3.ll
M llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
M llvm/tools/llvm-readobj/ObjDumper.cpp
M llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/433ea2847b81...649df394cd86
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