[all-commits] [llvm/llvm-project] dccb1f: [RISCV] Update latency of MUL & CPOP in SiFive P60...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dccb1fe879d6a949884523eab66a8a51cee93d1a
      https://github.com/llvm/llvm-project/commit/dccb1fe879d6a949884523eab66a8a51cee93d1a
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mul-cpop.s

  Log Message:
  -----------
  [RISCV] Update latency of MUL & CPOP in SiFive P600's scheduling model (#115042)

It should be 2 cycles rather than 3 cycles.



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