[all-commits] [llvm/llvm-project] ec9624: Revert "AMDGPU/GlobalISel: Add stub custom regbank...

Petar Avramovic via All-commits all-commits at lists.llvm.org
Tue Nov 5 07:50:10 PST 2024 

  Branch: refs/heads/users/petar-avramovic/new-rbs-revert-amdgpu-regbankselect
  Home:   https://github.com/llvm/llvm-project
  Commit: ec962429ce31c4d568cbddac34c7d745aa18caed
      https://github.com/llvm/llvm-project/commit/ec962429ce31c4d568cbddac34c7d745aa18caed
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
    M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
    R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

  Log Message:
  -----------
  Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass"

This reverts commit e9c49901a43f5b16c3df416460b7e4dbdd24ce03.
Current AMDGPURegBankSelect does nothing different then RegBankSelect.
Revert to using generic RegBankSelect in preparation for adding new
regbankselect passes. New AMDGPURegBankSelect, that will use uniformity
analysis for regbank select decisions, will not subclass RegBankSelect.
Revert regression tests to use regbankselect since amdgpu-regbankselect
will be used by new pass and behavior will be different.



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