[all-commits] [llvm/llvm-project] d0bbe4: [RISCV] Improve interleave load coverage (NF7, NF8...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d0bbe4fb546bf4d4283d453725867204e443fa8c
      https://github.com/llvm/llvm-project/commit/d0bbe4fb546bf4d4283d453725867204e443fa8c
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [RISCV] Improve interleave load coverage (NF7, NF8, and one hot)

NF7 and NF8 were just missing from the coverage.  The one active lane
cases should be a strided load instead.



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