[all-commits] [llvm/llvm-project] afbef7: [𝘀𝗽𝗿] changes introduced through rebase

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-support-memcmp-expansion-for-vectors
  Home:   https://github.com/llvm/llvm-project
  Commit: afbef79f1b5a3d7fd332f54e1c3c62b34c1e7af4
      https://github.com/llvm/llvm-project/commit/afbef79f1b5a3d7fd332f54e1c3c62b34c1e7af4
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]


  Commit: c01cddd50d1575c242d131aa5c2e0400d59b86a7
      https://github.com/llvm/llvm-project/commit/c01cddd50d1575c242d131aa5c2e0400d59b86a7
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-05 (Tue, 05 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll

  Log Message:
  -----------
  Rebase and change AllowOverlappingLoads

Created using spr 1.3.6-beta.1


Compare: https://github.com/llvm/llvm-project/compare/afbbd9dd1523...c01cddd50d15

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