[all-commits] [llvm/llvm-project] ffe96a: [RISCV] Allow undef elements in isDeinterleaveShuf...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ffe96ad105464763f6f9521fbd93e2767e2561e5
      https://github.com/llvm/llvm-project/commit/ffe96ad105464763f6f9521fbd93e2767e2561e5
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-11-04 (Mon, 04 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

  Log Message:
  -----------
  [RISCV] Allow undef elements in isDeinterleaveShuffle (#114585)

This allows us to form vnsrl deinterleaves from non-power-of-two
shuffles after they've been legalized to a power of two.



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