[all-commits] [llvm/llvm-project] 0ac2e4: [DAG] SimplifyDemandedBits - ignore SRL node if we...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ac2e42227ff565a8eab4c7c65c3ddb36aff3409
      https://github.com/llvm/llvm-project/commit/0ac2e42227ff565a8eab4c7c65c3ddb36aff3409
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-04 (Mon, 04 Nov 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/X86/scmp.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - ignore SRL node if we're just demanding known sign bits (#114805)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node.

We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.

Same fold as #114389 which added this for SimplifyMultipleUseDemandedBits



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