[all-commits] [llvm/llvm-project] 9a211f: [TableGen] Fix concatenation of subreg and artific...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a211fe7e49b8b1376772a40ca31153fb7d504dd
      https://github.com/llvm/llvm-project/commit/9a211fe7e49b8b1376772a40ca31153fb7d504dd
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-11-04 (Mon, 04 Nov 2024)

  Changed paths:
    A llvm/test/TableGen/ArtificialSubregs.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Fix concatenation of subreg and artificial subregs (#114391)

When CoveredBySubRegs is true and a sub-register consists of two
parts; a regular subreg and an artificial subreg, then TableGen
should consider only concatenating the non-artificial subregs. 
For example, S0_S1 is a concatenated subreg from D0_D1,
but S0_S1_HI should not be considered.



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