[all-commits] [llvm/llvm-project] 7bf0d6: [RISCV] Lower fixed-length strided VP loads and st...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7bf0d6d032c5ef04a0f4966df8760664aaefc871
      https://github.com/llvm/llvm-project/commit/7bf0d6d032c5ef04a0f4966df8760664aaefc871
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-11-04 (Mon, 04 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll

  Log Message:
  -----------
  [RISCV] Lower fixed-length strided VP loads and stores for zvfhmin/zvfbfmin (#114750)

Similarly to #114731, these don't actually require any instructions from
the extensions.

The motivation for this and #114731 is to eventually enable
isLegalElementTypeForRVV for f16 with zvfhmin and bf16 with zvfbfmin in
order to enable scalable vectorization.

Although the scalable codegen support for f16 and bf16 is now complete
enough for anything the loop vectorizer may emit, enabling
isLegalElementTypeForRVV would make certian hooks like
isLegalInterleavedAccessType and isLegalStridedLoadStore return true for
f16 and bf16. This means SLP would start emitting these intrinsics, so
we need to add fixed-length codegen support.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications