[all-commits] [llvm/llvm-project] beb12f: [RISCV] Add +optimized-nfN-segment-load-store (#11...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: beb12f92c71981670e07e47275efc6b5647011c1
      https://github.com/llvm/llvm-project/commit/beb12f92c71981670e07e47275efc6b5647011c1
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-11-04 (Mon, 04 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll

  Log Message:
  -----------
  [RISCV] Add +optimized-nfN-segment-load-store (#114414)

This is a follow up to #111511, where after benchmarking we learnt that
the Banana Pi F3 has fast segmented loads for not just NF=2, but also
NF=3 and NF=4:
https://github.com/preames/bp3-microarch#vlseg_lmul_x_sew_throughput

This adds tuning features to allow these segment loads and stores to be
costed cheaper and enables it for the spacemit-x60.

It also enables +optimized-nf2-segment-load-store by default in the
generic tuning to maintain the previous behaviour when compiled without
-mcpu or -mtune.



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