[all-commits] [llvm/llvm-project] 309820: [ISel] Propagate disjoint flag in ShrinkDemandedOp...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3098200fccabc781c68c0119ce33c89b500f6272
      https://github.com/llvm/llvm-project/commit/3098200fccabc781c68c0119ce33c89b500f6272
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-11-03 (Sun, 03 Nov 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll

  Log Message:
  -----------
  [ISel] Propagate disjoint flag in ShrinkDemandedOp (#114560)

When trying to evaluate an expression in a narrower type, the
DAGCombine should propagate the disjoint flag, as it's equally
valid on the narrower expression.

This helps improve better use of addressing modes for some
Arm SME instructions, for example.



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