[all-commits] [llvm/llvm-project] b9d711: [RISCV] Assign separate PseudoVSHA2MS_VV opcodes f...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9d7117ebd1f09a88ad5068e0a27de6c8324675a
      https://github.com/llvm/llvm-project/commit/b9d7117ebd1f09a88ad5068e0a27de6c8324675a
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleZvk.td

  Log Message:
  -----------
  [RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)

The vsha2ms.vv from Zvknh[ab] currently supports both SEW=32 and SEW=64.
It might have different performance characteristics depending on the SEW
on some processors. This patch splits these two different SEWs into
their own VPsuedo opcodes and scheduling classes.

This is effectively a NFC change.



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