[all-commits] [llvm/llvm-project] 9fb4bc: [DAG] SimplifyMultipleUseDemandedBits - ignore SRL...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9fb4bc5bf4ecdc8f53bd1b8eeea20390fb6e642e
      https://github.com/llvm/llvm-project/commit/9fb4bc5bf4ecdc8f53bd1b8eeea20390fb6e642e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/RISCV/pr95284.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/scmp.ll

  Log Message:
  -----------
  [DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node.

We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.



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