[all-commits] [llvm/llvm-project] 9c7188: [RISCV] Cost ordered bf16/f16 w/ zvfhmin reduction...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c7188871cbf0618b1920415d364bd90c5122436
      https://github.com/llvm/llvm-project/commit/9c7188871cbf0618b1920415d364bd90c5122436
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll

  Log Message:
  -----------
  [RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (#114250)

In #111000 we removed promotion of fadd/fmul reductions for bf16 and f16
without zvfh, and marked the cost as invalid to prevent the vectorizers
from emitting them. However it inadvertently didn't change the cost for
ordered reductions, so this moves the check earlier to fix this.

This also uses BasicTTIImpl instead which now assigns a valid but
expensive cost for fixed-length vectors, which reflects how codegen will
actually scalarize them.



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