[all-commits] [llvm/llvm-project] eeee5a: [Clang][SYCL] Introduce clang-sycl-linker to link ...

[Arvind Sudarsanam via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eeee5a44bbf24f2f30a313ecf66e6a76de365658
      https://github.com/llvm/llvm-project/commit/eeee5a44bbf24f2f30a313ecf66e6a76de365658
  Author: Arvind Sudarsanam <arvind.sudarsanam at intel.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    A clang/docs/ClangSYCLLinker.rst
    M clang/docs/index.rst
    M clang/include/clang/Driver/Options.td
    M clang/lib/Driver/Driver.cpp
    M clang/lib/Driver/ToolChains/SPIRV.cpp
    M clang/lib/Driver/ToolChains/SPIRV.h
    M clang/test/CMakeLists.txt
    A clang/test/Driver/clang-sycl-linker-test.cpp
    A clang/test/Driver/sycl-link-spirv-target.cpp
    M clang/test/lit.cfg.py
    M clang/tools/CMakeLists.txt
    A clang/tools/clang-sycl-linker/CMakeLists.txt
    A clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
    A clang/tools/clang-sycl-linker/SYCLLinkOpts.td

  Log Message:
  -----------
  [Clang][SYCL] Introduce clang-sycl-linker to link SYCL offloading device code (Part 1 of many) (#112245)

This PR is one of the many PRs in the SYCL upstreaming effort focusing
on device code linking during the SYCL offload compilation process. RFC:
https://discourse.llvm.org/t/rfc-offloading-design-for-sycl-offload-kind-and-spir-targets/74088

In this PR, we introduce a new tool that will be used to perform device
code linking for SYCL offload kind. It accepts SYCL device objects in
LLVM IR bitcode format and will generate a fully linked device object
that can then be wrapped and linked into the host object.

A primary use case for this tool is to perform device code linking for
objects with SYCL offload kind inside the clang-linker-wrapper. It can
also be invoked via clang driver as follows:

`clang --target=spirv64 --sycl-link input.bc`

Device code linking for SYCL offloading kind has a number of known
quirks that makes it difficult to use in a unified offloading setting.
Two of the primary issues are:
1. Several finalization steps are required to be run on the fully-linked
LLVM IR bitcode to gaurantee conformance to SYCL standards. This step is
unique to SYCL offloading compilation flow.
2. SPIR-V LLVM Translator tool is an extenal tool and hence SPIR-V IR
code generation cannot be done as part of LTO. This limitation will be
lifted once SPIR-V backend is available as a viable LLVM backend.

Hence, we introduce this new tool to provide a clean wrapper to perform
SYCL device linking.

Co-Author: Michael Toguchi
Thanks

---------

Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam at intel.com>



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