[all-commits] [llvm/llvm-project] 18f0f7: [RISCV] Support llvm.masked.expandload intrinsic (...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18f0f709345cc7e611c4f944832edb71284caacb
      https://github.com/llvm/llvm-project/commit/18f0f709345cc7e611c4f944832edb71284caacb
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    A llvm/test/CodeGen/RISCV/rvv/expandload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll

  Log Message:
  -----------
  [RISCV] Support llvm.masked.expandload intrinsic (#101954)


We can use `viota`+`vrgather` to synthesize `vdecompress` and lower
expanding load to `vcpop`+`load`+`vdecompress`.

And if `%mask` is all ones, we can lower expanding load to a normal
unmasked load.

Fixes #101914.



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