[all-commits] [llvm/llvm-project] cf9d1c: [SDAG] Simplify `SDNodeFlags` with bitwise logic (...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf9d1c1486ef53213b434700a4117d71a2cb67e3
      https://github.com/llvm/llvm-project/commit/cf9d1c1486ef53213b434700a4117d71a2cb67e3
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-10-31 (Thu, 31 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/SDPatternMatch.h
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp

  Log Message:
  -----------
  [SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)

This patch allows using enumeration values directly and simplifies the
implementation with bitwise logic. It addresses the comment in
https://github.com/llvm/llvm-project/pull/113808#discussion_r1819923625.



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