[all-commits] [llvm/llvm-project] 45f420: [lldb] Use Py_InitializeFromConfig with Python >= ...
Paul Kirth via All-commits
all-commits at lists.llvm.org
Wed Oct 30 16:57:39 PDT 2024
Branch: refs/heads/users/ilovepi/spr/main.llvmfatlto-drop-any-cfi-related-instrumentation-after-emitting-bitcode
Home: https://github.com/llvm/llvm-project
Commit: 45f420e34476d2963e13b2f916be1e5a73ec95ae
https://github.com/llvm/llvm-project/commit/45f420e34476d2963e13b2f916be1e5a73ec95ae
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Log Message:
-----------
[lldb] Use Py_InitializeFromConfig with Python >= 3.8 (NFC) (#114112)
This fixes the deprecation warning for Py_SetPythonHome, which was
deprecated in Python 3.11. With this patch, when building against Python
3.8 or later, we now use Py_InitializeFromConfig instead.
Fixes #113475
Commit: eac2c182c6f852fc187af9952250a43d6fb17b28
https://github.com/llvm/llvm-project/commit/eac2c182c6f852fc187af9952250a43d6fb17b28
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py
Log Message:
-----------
Remove a flaky and unnecessary check (#114251)
The order in which the libraries appear is not always stable and even if
it were, this test is not the right place to check for this.
Commit: 4b028773b2c977eb8494a39e4b3fb2f114d1e2b5
https://github.com/llvm/llvm-project/commit/4b028773b2c977eb8494a39e4b3fb2f114d1e2b5
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
R llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll
R llvm/test/CodeGen/MIR/icmp-flags.mir
Log Message:
-----------
Revert "[GlobalISel] Import samesign flag" (#114256)
Reverts llvm/llvm-project#113090
Commit: 8ee5e19c879ee2d467aa0f1eb8f1d8ed34321496
https://github.com/llvm/llvm-project/commit/8ee5e19c879ee2d467aa0f1eb8f1d8ed34321496
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
Log Message:
-----------
[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)
The correct behaviour is to insert a readfirstlane. SelectionDAG was
already doing this in some cases, but not in the general case for chain
calls. GlobalISel was already doing this for return values but not for
arguments.
Commit: 1ddea4fc13eb12ddb4e71f7675a496de6d517ec4
https://github.com/llvm/llvm-project/commit/1ddea4fc13eb12ddb4e71f7675a496de6d517ec4
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
Log Message:
-----------
[AArch64] NFC: Refactoring of the SubRegIndexes in AArch64RegisterInfo.td
This is just moving some of the definitions around to all have them in
the same place. This is preparation for a follow-up patch that redefines
the SubRegIndexes to require less bits, and to define the top bits
of registers.
Commit: 6bf4476ffb6bab661d59dee361ab845b2f68d9b1
https://github.com/llvm/llvm-project/commit/6bf4476ffb6bab661d59dee361ab845b2f68d9b1
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
Log Message:
-----------
[AMDGPU] Fix @llvm.amdgcn.cs.chain with callee not provably uniform (#114200)
The correct behavior is to insert a readfirstlane. This worked except
for an inappropriate assertion in SITargetLowering::LowerCall.
Commit: a575e6e5ca1eb7b2ae4b906f9bf3be2ba20a80a0
https://github.com/llvm/llvm-project/commit/a575e6e5ca1eb7b2ae4b906f9bf3be2ba20a80a0
Author: jimingham <jingham at apple.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py
M lldb/test/API/python_api/type/TestTypeList.py
Log Message:
-----------
Fix a couple of tests that were incorrectly using configuration.dwarf_version (#114161)
The tests were using the variable directly to get the dwarf version used
for the test. That's only the overridden value, and won't be set if
we're using the compiler default. I also put a comment by the variable
to make sure people don't make the same mistake in the future.
Commit: 9cd30b1ef311edb0aa0527bead52e2fc490160ef
https://github.com/llvm/llvm-project/commit/9cd30b1ef311edb0aa0527bead52e2fc490160ef
Author: jimingham <jingham at apple.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/source/Commands/CommandObjectType.cpp
Log Message:
-----------
Fix the sort function for languages to have "strict weak ordering". (#114160)
If you build libstdc++ with "debug" strictness, the test
TestTypeLookup.py will assert. That's because we're calling llvm::sort
(which redirects to std::sort) with a function that doesn't obey strict
weak ordering.
The error was that when the two languages were equal, we're sometimes
returning `true` but strict weak ordering requires that always be false.
This patch just makes the function behave properly.
Commit: 7dbbd2b251412b7b0809aabe672f3f57f0805dbb
https://github.com/llvm/llvm-project/commit/7dbbd2b251412b7b0809aabe672f3f57f0805dbb
Author: jimingham <jingham at apple.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/BreakpointSite.h
M lldb/include/lldb/Core/Declaration.h
M lldb/include/lldb/Target/StopInfo.h
M lldb/include/lldb/Target/ThreadPlanStepInRange.h
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Core/Declaration.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadPlanStepInRange.cpp
M lldb/source/Target/ThreadPlanStepOverRange.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py
M lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py
M lldb/test/API/functionalities/inline-stepping/calling.cpp
Log Message:
-----------
Fix call site breakpoint patch (#114158)
This fixes the two test suite failures that I missed in the PR:
https://github.com/llvm/llvm-project/pull/112939
One was a poorly written test case - it assumed that on connect to a
gdb-remote with a running process, lldb MUST have fetched all the frame
0 registers. In fact, there's no need for it to do so (as the CallSite
patch showed...) and if we don't need to we shouldn't. So I fixed the
test to only expect a `g` packet AFTER calling read_registers.
The other was a place where some code had used 0 when it meant
LLDB_INVALID_LINE_NUMBER, which I had fixed but missed one place where
it was still compared to 0.
Commit: 49277253f016268e4a10109f1db2e53c60d35881
https://github.com/llvm/llvm-project/commit/49277253f016268e4a10109f1db2e53c60d35881
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/include/lldb/Host/Editline.h
M lldb/source/Host/common/Editline.cpp
Log Message:
-----------
[lldb] Use LLVM's helper for Unicode conversion (NFC) (#112582)
The codecvt header has been deprecated in C++17. Use LLVM's unicode
helpers to convert between UTF-8 and UTF-16.
Commit: 0c9a02355abc3b037be53c072fc46a13bb5aa2c1
https://github.com/llvm/llvm-project/commit/0c9a02355abc3b037be53c072fc46a13bb5aa2c1
Author: Asher Mancinelli <ashermancinelli at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/box.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/embox-char.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/tbaa.fir
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/allocatable-polymorphic.f90
Log Message:
-----------
[flang][fir] always use memcpy for fir.box (#113949)
@jeanPerier explained the importance of converting box loads and stores
into `memcpy`s instead of aggregate loads and stores, and I'll do my
best to explain it here.
* [(godbolt link) Example comparing opt transformations on memcpys vs
aggregate load/stores](https://godbolt.org/z/be7xM83cG)
* LLVM can more effectively reason about memcpys compared to aggregate
load/stores.
* This came up when others were discussing array descriptors for
assumed-rank arrays passed to `bind(c)` subroutines, with the
implication that the array descriptors are known to have lower bounds of
1 and that they are not pointer/allocatable types.
* [(godbolt link) Clang also uses memcpys so we should probably follow
them, assuming the clang developers are generatign what they know Opt
will handle more effectively.](https://godbolt.org/z/YT4x7387W)
* This currently may not help much without the `nocapture` attribute
being propagated to function calls, but [it looks like someone may do
this soon (discourse
link)](https://discourse.llvm.org/t/applying-the-nocapture-attribute-to-reference-passed-arguments-in-fortran-subroutines/81401/23)
or I can do this in a follow-up patch.
Note on test `flang/test/Fir/embox-char.fir`: it looks like the original
test was auto-generated. I wasn't too sure which parts were especially
important to test, so I regenerated the test. If we want the updated
version to look more like the old version, I'll make those changes.
Commit: 0227b73b513154a2bde90ddf1e167b6257765d05
https://github.com/llvm/llvm-project/commit/0227b73b513154a2bde90ddf1e167b6257765d05
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
A llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_err-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][test] update VOP2 asm/dasm file with true16/fake16 (#113101)
This is a non-functional change
update GFX11/GFX12 VOP2 asm/dasm test for true16/fake16:
1. duplicate files to be true16/fake16 by adding
"-mattr=+real-true16/-mattr=-real-true16" while true16 test file will be
updated to true16 format when the true16 instructions are supported
2. sort "*t16_err.s" and "*t16_promote.s" tests to alphabetic order.
This is for the upcoming true16 mc changes, and mainly trying to help
repo maintainer to resolve conflicts in the tests quickly. A script is
proposed to help for the sorting
https://github.com/llvm/llvm-project/pull/111769. Since these two files
are t16 only, it should not create conflicts in downstream branches
3. add -filetype=null to seperate stdout and stderr to avoid disordered
output from llvm-mc
Commit: 311c0772f9e67a694f3038ab63ea4ec981ce6a9a
https://github.com/llvm/llvm-project/commit/311c0772f9e67a694f3038ab63ea4ec981ce6a9a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
Log Message:
-----------
[AMDGPU] Fix test failures after #114232 and #114200
Commit: 463a4c16ea9c1a3c1210d0ac39e56a75b43b5a8d
https://github.com/llvm/llvm-project/commit/463a4c16ea9c1a3c1210d0ac39e56a75b43b5a8d
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGObjCGNU.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
Log Message:
-----------
[clang] Remove some uses of llvm::StructType::setBody. NFC. (#113691)
It is simple to create the struct body up front, now that we have
transitioned to opaque pointers.
Commit: cc2d8e7616762710b284aa9af44a297b633b270a
https://github.com/llvm/llvm-project/commit/cc2d8e7616762710b284aa9af44a297b633b270a
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening.s
Log Message:
-----------
[AArch64] Add assembly/disassembly of FMOP4{A,S} (non-widening) single-precision instructions (#113344)
The new instructions are described in
https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions
Commit: d7e6cba030f34162ea45aef1dc18f708b5d2ec70
https://github.com/llvm/llvm-project/commit/d7e6cba030f34162ea45aef1dc18f708b5d2ec70
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Use bit or bits for some tablegen class arguments. NFC
These eventually end up in TSFlags so we should use the same types.
Commit: cf6ca98481a90728f1d3adc748aa0f271afc59aa
https://github.com/llvm/llvm-project/commit/cf6ca98481a90728f1d3adc748aa0f271afc59aa
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[Clang] Add and use mangleVendorType helper. NFC. (#108970)
Commit: 0c8e12fc64073a889956e790881cdf0d58018372
https://github.com/llvm/llvm-project/commit/0c8e12fc64073a889956e790881cdf0d58018372
Author: Roland McGrath <mcgrathr at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/include/llvm-libc-types/fexcept_t.h
Log Message:
-----------
[libc] Fix fexcept_t type to match canonical ABI and API (#113666)
In glibc and musl, fexcept_t is unsigned short int on x86 and
unsigned int on other machines that llvm-libc supports. Match
that ABI (only different from before on x86) and API (different
everywhere as it was previously signed).
Commit: 5192cb772ad58af4b557539791ff8de60ab450a3
https://github.com/llvm/llvm-project/commit/5192cb772ad58af4b557539791ff8de60ab450a3
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
Log Message:
-----------
[AArch64] Add hidden option to enable subreg liveness tracking.
Subreg liveness tracking is disabled by default for now until all issues
are ironed out. This option allows the feature to be used in tests.
Commit: 70d35fbdb6c01e2ccd76ce5c5fe7610ab77d0ea1
https://github.com/llvm/llvm-project/commit/70d35fbdb6c01e2ccd76ce5c5fe7610ab77d0ea1
Author: Lang Hames <lhames at gmail.com>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
Log Message:
-----------
[ORC] Fix include guard names. NFC.
Commit: b94762d5a7fbf883707c4018dbf43d7525a06e12
https://github.com/llvm/llvm-project/commit/b94762d5a7fbf883707c4018dbf43d7525a06e12
Author: Lang Hames <lhames at gmail.com>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h
Log Message:
-----------
[ORC] Add comment on include guard #endif
Commit: feb2d867fac3b6339c169fff97ddf0716fce6f0a
https://github.com/llvm/llvm-project/commit/feb2d867fac3b6339c169fff97ddf0716fce6f0a
Author: Kenji Mouri / 毛利 研二 <Mouri_Naruto at Outlook.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
Log Message:
-----------
[TLI] Add support for hypot libcall. (#113724)
This patch adds basic support for `hypot`. Constant folding support will
be submitted in a subsequent patch.
Related issue: https://github.com/llvm/llvm-project/issues/113711
Note: It's my first time contributing to the LLVM with encouragement
from one of my friends, @fawdlstty. I learned a lot from
https://github.com/llvm/llvm-project/pull/99611, and thanks for that.
Kenji Mouri
Commit: 04549500562783b01db262de62fe324c7ee471c4
https://github.com/llvm/llvm-project/commit/04549500562783b01db262de62fe324c7ee471c4
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening.s
Log Message:
-----------
[AArch64] Add assembly/disassembly for FMOP4{A,S} (non-widening) double-precision instructions (#113345)
The new instructions are described in
https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions
Commit: 705f3ebf1458c154fe63552ca984be6a16711661
https://github.com/llvm/llvm-project/commit/705f3ebf1458c154fe63552ca984be6a16711661
Author: Chris Apple <cja-private at pm.me>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/docs/RealtimeSanitizer.rst
Log Message:
-----------
[rtsan][NFC] Add documentation link to Function Effects (#113979)
Commit: 5545f76dc94e76ef6800823bdd1e107ad2264717
https://github.com/llvm/llvm-project/commit/5545f76dc94e76ef6800823bdd1e107ad2264717
Author: Sean Perry <perry at ca.ibm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
Log Message:
-----------
Pass the executable name as arg[0] when calling ExecuteAndWait() (#114067)
PR https://github.com/llvm/llvm-project/pull/111976 was enabling the
tests updated in the PR to run on all systems. We found a few didn't run
on z/OS. I tracked the problem down to:
1. the ExecuteToolChainProgram() function wasn't passing the executable
name as the first arg. That was causing exec on z/OS to fail.
2. the temp file needs to be a text file so codepage conversion happens.
Commit: ca1154d1d41c75db6594428a8cdf263cf7041896
https://github.com/llvm/llvm-project/commit/ca1154d1d41c75db6594428a8cdf263cf7041896
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Disable pattern matching "x<<32-y>>32-y" to "bfe x, 0, y" (#114279)
It is not correct to lower "x<<32-y>>32-y" to "bfe x, 0, y". When y
equals to 32, the left-hand side is still x (unchanged), however, the
right-hand side will be evaluated to 0. So it is not always correct to
do such transformation.
We may be able to keep the pattern for immediate y while y is within [0,
31]. However, the immediate operands of the sub (32 - y) are easily
folded, and "(x << imm) >> imm" will be lowered to "and x,
(2^(32-imm))-1" anyway. So no bfe matching is needed.
Commit: a518ed2d815c16010a6262edd0414a5f60a63a39
https://github.com/llvm/llvm-project/commit/a518ed2d815c16010a6262edd0414a5f60a63a39
Author: Dana Jansens <danakj at chromium.org>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
Log Message:
-----------
Respect the [[clang::unsafe_buffer_usage]] attribute for field and constructor initializers (#91991)
CXXCtorInitializers are not statements , but they point to an
initializer expression which is. When visiting a FunctionDecl, also
walk through any constructor initializers and run the warning
checks/matchers against their initializer expressions. This catches
warnings for initializing fields and calling other constructors, such
as:
struct C {
C(P* Ptr) : AnUnsafeCtor(Ptr) {}
}
Field initializers can be found by traversing CXXDefaultInitExprs. This
catches warnings in places such as:
struct C {
P* Ptr;
AnUnsafeCtor U{Ptr};
};
We add tests for explicit construction, for field initialization, base
class constructor calls, delegated constructor calls, and aggregate
initialization.
Note that aggregate initialization is not fully covered where a field
specifies an initializer and it's not overridden in the aggregate initialization,
such as in:
struct AggregateViaValueInit {
UnsafeMembers f1;
// FIXME: A construction of this class does initialize the field
// through this initializer, so it should warn. Ideally it should
// also point to where the site of the construction is in
// testAggregateViaValueInit().
UnsafeMembers f2{3};
};
void testAggregateViaValueInit() {
auto A = AggregateViaValueInit();
};
There are 3 tests for different types of aggregate initialization with
FIXMEs documenting this future work.
One attempt to fix this involved returning true from
MatchDescendantVisitor::shouldVisitImplicitCode(), however, it breaks expectations
for field in-class initializers by moving the SourceLocation, possibly
to inside the implicit ctor instead of on the line where the field
initialization happens.
struct C {
P* Ptr;
AnUnsafeCtor U{Ptr}; // expected-warning{{this is never seen then}}
};
Tests are also added for std::span(ptr, size) constructor being called
from a field initializer and a constructor initializer.
Issue #80482
Commit: 2bc5302706e710d125752c215392043fd5bf80fa
https://github.com/llvm/llvm-project/commit/2bc5302706e710d125752c215392043fd5bf80fa
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Log Message:
-----------
Revert "[lldb] Use Py_InitializeFromConfig with Python >= 3.8 (NFC)" (#114290)
Reverts llvm/llvm-project#114112 because this triggers a compile error:
```
no known conversion from 'str_type' (aka 'wchar_t *') to 'const char *' for 3rd argument
221 | PyAPI_FUNC(PyStatus) PyConfig_SetBytesString(
| ^
222 | PyConfig *config,
223 | wchar_t **config_str,
224 | const char *str);
| ~~~~~~~~~~~~~~~
1 error generated.
```
Commit: 5bd1af5abcb7b9f92741dd7209e84b5607f7e88a
https://github.com/llvm/llvm-project/commit/5bd1af5abcb7b9f92741dd7209e84b5607f7e88a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Directly store VPlan in InnerLoopVectorizer (NFC).
The current VPlan is already passed to multiple functions and more in
the future. Store it once directly in InnerLoopVectorizer.
Commit: c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
https://github.com/llvm/llvm-project/commit/c3724ba8667c695f29d5af93f2b0d1b23c1b41e7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
Log Message:
-----------
[RISCV] Add OperandType for vector rounding mode operands. (#114179)
Use TSFlags to distinquish which type of rounding mode it is. We use the same tablegen base classes for vxrm and frm sometimes so its hard to have different types for different instructions.
Commit: 71b6f6b8a1cd9a63b9d382fe15f40bbb427939b9
https://github.com/llvm/llvm-project/commit/71b6f6b8a1cd9a63b9d382fe15f40bbb427939b9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. (#114186)
We need an implicit FRM read operand anytime the rounding mode is
dynamic. The post isel hook is responsible for this when isel creates an
instruction with dynamic rounding mode.
Add a MachineVerifier check to verify the operand is present.
Commit: 90786adade22784a52856a0e8b545ec6710b47f6
https://github.com/llvm/llvm-project/commit/90786adade22784a52856a0e8b545ec6710b47f6
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/ast-dump-decl.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
Log Message:
-----------
[Clang][Sema] Always use latest redeclaration of primary template (#114258)
This patch fixes a couple of regressions introduced in #111852.
Consider:
```
template<typename T>
struct A
{
template<bool U>
static constexpr bool f() requires U
{
return true;
}
};
template<>
template<bool U>
constexpr bool A<short>::f() requires U
{
return A<long>::f<U>();
}
template<>
template<bool U>
constexpr bool A<long>::f() requires U
{
return true;
}
static_assert(A<short>::f<true>()); // crash here
```
This crashes because when collecting template arguments from the _first_
declaration of `A<long>::f<true>` for constraint checking, we don't add
the template arguments from the enclosing class template specialization
because there exists another redeclaration that is a member
specialization.
This also fixes the following example, which happens for a similar
reason:
```
// input.cppm
export module input;
export template<int N>
constexpr int f();
template<int N>
struct A {
template<int J>
friend constexpr int f();
};
template struct A<0>;
template<int N>
constexpr int f() {
return N;
}
```
```
// input.cpp
import input;
static_assert(f<1>() == 1); // error: static assertion failed
```
Commit: 47d9db762484afadeca1acb60534b6b88784464a
https://github.com/llvm/llvm-project/commit/47d9db762484afadeca1acb60534b6b88784464a
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening.s
Log Message:
-----------
[AArch64] Add asssembly/disassembly for FMOP4{A,S} (widening, 2-way, FP16 to FP32) instructions (#113346)
The new instructions are described in
https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions
Commit: 408c84f35b8b0338b630a6ee313c14238e62b5e6
https://github.com/llvm/llvm-project/commit/408c84f35b8b0338b630a6ee313c14238e62b5e6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
Log Message:
-----------
[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274)
Add Uses = [FRM] to the underlying MC instructions.
Tweak a couple test cases so the MachineVerifier would have caught this.
Commit: b3bb6f18bb5b2b8756b585b80d46d13ab3636a18
https://github.com/llvm/llvm-project/commit/b3bb6f18bb5b2b8756b585b80d46d13ab3636a18
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/icmp-flags.mir
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
Log Message:
-----------
[GlobalISel] Import samesign flag (#114267)
Credits: https://github.com/llvm/llvm-project/pull/111419
Fixes icmp-flags.mir
First attempt: https://github.com/llvm/llvm-project/pull/113090
Revert: https://github.com/llvm/llvm-project/pull/114256
Commit: dc1ff883caf687f00bd916ea997321ac411c73fd
https://github.com/llvm/llvm-project/commit/dc1ff883caf687f00bd916ea997321ac411c73fd
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/include/llvm-libc-macros/linux/signal-macros.h
Log Message:
-----------
[libc][i386] define MINSIGSTKSZ & SIGSTKSZ (#114249)
Link: #93709
Commit: bc79ec0c5bc3fce31448419846c343017ae1c5ad
https://github.com/llvm/llvm-project/commit/bc79ec0c5bc3fce31448419846c343017ae1c5ad
Author: Fred Tingaud <95592999+frederic-tingaud-sonarsource at users.noreply.github.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
Log Message:
-----------
[clang][ASTMatcher] Handle variable templates in `isInstantiated` and `isInTemplateInstantiation` matchers (#110666)
Fix `isInstantiated` and `isInTemplateInstantiation` matchers, so they
return true for instantiations of variable templates, and any
declaration in statements contained in such instantiations.
Commit: d8295e2eeceef37bfd9e0f84918735eff6cfc659
https://github.com/llvm/llvm-project/commit/d8295e2eeceef37bfd9e0f84918735eff6cfc659
Author: Steven Perron <stevenperron at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
R llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll
Log Message:
-----------
[SPIRV][HLSL] Handle arrays of resources (#111564)
This commit adds the ability to get a particular resource from an array
of resources using the handle_fromBinding intrinsic.
The main changes are:
1. Create an array when generating the type.
2. Add capabilities from
[SPV_EXT_descriptor_indexing](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_descriptor_indexing.html).
We are still missing the ability to declare a runtime array. That will
be done in a follow up PR.
Commit: b03c8c4fdda6e58cb1afe3aa90bf9f2df08a7970
https://github.com/llvm/llvm-project/commit/b03c8c4fdda6e58cb1afe3aa90bf9f2df08a7970
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/src/string/string_utils.h
M libc/test/src/string/strlcat_test.cpp
M libc/test/src/string/strlcpy_test.cpp
Log Message:
-----------
libc: strlcpy/strlcat shouldn't bzero the rest of `buf` (#114259)
When running Bionic's testsuite over llvm-libc, tests broke because
e.g.,
```
const char *str = "abc";
char buf[7]{"111111"};
strlcpy(buf, str, 7);
ASSERT_EQ(buf, {'1', '1', '1', '\0', '\0', '\0', '\0'});
```
On my machine (Debian w/ glibc and clang-16), a `printf` loop over `buf`
gets unrolled into a series of const `printf` at compile-time:
```
printf("%d\n", '1');
printf("%d\n", '1');
printf("%d\n", '1');
printf("%d\n", 0);
printf("%d\n", '1');
printf("%d\n", '1');
printf("%d\n", 0);
```
Seems best to match existing precedent here.
Commit: e4dfb51da4cd16cbb3ab18944a43ff5518d9f548
https://github.com/llvm/llvm-project/commit/e4dfb51da4cd16cbb3ab18944a43ff5518d9f548
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/docs/index.rst
Log Message:
-----------
Fix documentation build
This fixes the build after the removal of the clang-format status page.
Commit: d2109640a3e352b49a698edc232eeaac648fe590
https://github.com/llvm/llvm-project/commit/d2109640a3e352b49a698edc232eeaac648fe590
Author: Ilya Enkovich <ilya.enkovich at intel.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/AMX/legalize-for-llvm.mlir
Log Message:
-----------
[MLIR] [AMX] Fix strides used by AMX lowering for tile loads and stores. (#113476)
Commit: c616f24bcb00150fedc999d47933603e099dd659
https://github.com/llvm/llvm-project/commit/c616f24bcb00150fedc999d47933603e099dd659
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll
Log Message:
-----------
[SPIR-V] Do instruction selection for G_BITCAST on an earlier stage (#114216)
This PR implements instruction selection for G_BITCAST on an earlier
stage to avoid MachineVerifier complains on subtle semantics difference
between G_BITCAST and OpBitcast.
We do instruction selections for OpBitcast after IR Translation instead
of calling MIB.buildBitcast() generating the general op code G_BITCAST,
because when MachineVerifier validates G_BITCAST we see a check of a
kind: 'if Source Type is equal to Destination Type then report error
"bitcast must change the type"'. This doesn't take into account the
notion of a typed pointer that is important for SPIR-V where a user may
and should use bitcast between pointers with different pointee types
(https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpBitcast).
It's important for correct lowering in SPIR-V, because interpretation of
the data type is not left to instructions that utilize the pointer, but
encoded by the pointer declaration, and the SPIRV target can and must
handle the declaration and use of pointers that specify the type of data
they point to.
It's not feasible to improve validation of G_BITCAST using just
information provided by low level types of source and destination.
Therefore we don't produce G_BITCAST as the general op code with
semantics different from OpBitcast, but rather lower to OpBitcast
immediately.
See discussion in https://github.com/llvm/llvm-project/pull/110270 for
even more context.
Commit: b1320d36339e38b073088fd45013a3c692adb301
https://github.com/llvm/llvm-project/commit/b1320d36339e38b073088fd45013a3c692adb301
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/include/llvm-libc-types/jmp_buf.h
M libc/src/setjmp/x86_64/longjmp.cpp
M libc/src/setjmp/x86_64/setjmp.cpp
Log Message:
-----------
[libc][i386] setjmp/longjmp (#112437)
Link: #93709
Commit: e89f8212333ea8e9b534fb32382bb5cacae71b35
https://github.com/llvm/llvm-project/commit/e89f8212333ea8e9b534fb32382bb5cacae71b35
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NFC][NVPTX] Cleanup getPreferredVectorAction() (#114115)
`v2*16` is a legal type in NVPTX. Thus, this is dead code.
Commit: 0167a92e28d5c8eac00595300a1366bdce28678d
https://github.com/llvm/llvm-project/commit/0167a92e28d5c8eac00595300a1366bdce28678d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Use unsigned instead of int64_t for two small positive shift amounts. NFC
Commit: 1c2824e3a44f6c7cfd3e236597c4af671ce7c95e
https://github.com/llvm/llvm-project/commit/1c2824e3a44f6c7cfd3e236597c4af671ce7c95e
Author: Artem Pianykh <arr at fb.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Log Message:
-----------
[NFC][Coro] Add helpers for coro cloning with a TimeTraceScope (#112948)
A helper (2 overloads) that consolidates corocloner creation and the
actual cloning. The helpers create a TimeTraceScope to make it easier to
see how long the cloning takes.
Extracted from #109032 (commit 1)
Commit: 84a78abdf5999e58e4120e20594ac2ad37472295
https://github.com/llvm/llvm-project/commit/84a78abdf5999e58e4120e20594ac2ad37472295
Author: Artem Pianykh <arr at fb.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Transforms/Utils/CloneFunction.cpp
Log Message:
-----------
[NFC][Utils] Extract CloneFunctionAttributesInto from CloneFunctionInto (#112976)
This patch is a part of step-by-step refactoring of CloneFunctionInto.
The goal is to extract reusable pieces out of it that will be later used
to optimize function cloning e.g. in coroutine processing.
Extracted from #109032 (commit 2)
Commit: bfe486fe764667d514124faf2b39afb7e7322640
https://github.com/llvm/llvm-project/commit/bfe486fe764667d514124faf2b39afb7e7322640
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/memory.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
Passing descriptors by reference to CUDA runtime calls (#114288)
Passing a descriptor as a `const Descriptor &` or a `const Descriptor *`
generates a FIR signature where the box is passed by value.
This is an issue, as it requires a load of the box to be passed. But
since, ultimately, all boxes are passed by reference a temporary is
generated in LLVM and the reference to the temporary is passed.
The boxes addresses are registered with the CUDA runtime but the
temporaries are not, thus preventing the runtime to properly map a host
side address to its device side counterpart.
To address this issue, this PR changes the signatures to the transfer
functions to pass a descriptor as a `Descriptor *`, which will in turn
generate a FIR signature with that takes a box reference as an argument.
Commit: f7c36d2f88e05a1747fa7916ad2fefdd9d459a55
https://github.com/llvm/llvm-project/commit/f7c36d2f88e05a1747fa7916ad2fefdd9d459a55
Author: Wanyi <kusmour at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/test/API/python_api/process/io/TestProcessIO.py
Log Message:
-----------
[lldb] Fix API test for file redirection to existing files (#114119)
API test failed for remote platform in
[#112657](https://github.com/llvm/llvm-project/pull/112657)
Previously when putting files onto remote platform, I used `platform
file write -d <data>` which actually required a `platform file open
<path>` first in order to obtain a file descriptor.
eg. in file
[TestGDBRemotePlatformFile.py](https://github.com/llvm/llvm-project/blob/94e7d9c0bfe517507ea08b00fb00c32fb2837a82/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemotePlatformFile.py#L24-L32)
To fix this, use the `platform put-file` method, which is used in the
`redirect_stdin` from this test already.
Commit: 4afa9787560d00474c6ab600be70d59fa7eae87f
https://github.com/llvm/llvm-project/commit/4afa9787560d00474c6ab600be70d59fa7eae87f
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/ast-dump-decl.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
Log Message:
-----------
Revert "[Clang][Sema] Always use latest redeclaration of primary template" (#114304)
Clang importer doesn't seem to work well with this change, see
discussion in the original PR.
Reverts llvm/llvm-project#114258
Commit: 74d8f3952c4acf6d57948983d7c5b0d0a7763c28
https://github.com/llvm/llvm-project/commit/74d8f3952c4acf6d57948983d7c5b0d0a7763c28
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
R clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl
R clang/test/CodeGenHLSL/builtins/StructuredBuffer-annotations.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/cbuf.hlsl
Log Message:
-----------
[HLSL] Remove old resource annotations for UAVs and SRVs (#114139)
UAVs and SRVs have already been converted to use LLVM target types and
we can disable generating of the !hlsl.uavs and !hlsl.srvs! annotations.
This will enable adding tests for structured buffers with user defined
types that this old resource annotations code does not handle (it
crashes).
Part 1 of #114126
Commit: 14045de250ea126029d43ff8f2f68e9614c394bc
https://github.com/llvm/llvm-project/commit/14045de250ea126029d43ff8f2f68e9614c394bc
Author: Luke Lau <luke at igalia.com>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
Log Message:
-----------
[RISCV] Account for factor in interleave memory op costs (#111511)
Currently we cost an interleaved memory op as if it were a load/store of
the widened vector type, but this was undercosting in all cases when
compared to the measured performance of todays hardware.
On the x280 at NF=2 and spacemit-x60 at NF=2,3 and 4, a segmented load
is carried out as a wide load and NF LMUL shuffle ops:
https://github.com/preames/bp3-microarch#vlseg_lmul_x_sew_throughput
All other NFs go through a slow path. On the spacemit-x60 this is
proportional to VLMAX * NF, and on the x280 proportional to the number
of segments.
This patch increases the cost by implementing a wide load + NF LMUL
shuffle op cost for the lowest common denominator NF=2, and then a
slower cost proportional to VL for the other NFs.
In a follow up patch we can add a tuning flag to use the faster cost
model for NF=3 and 4 on the spacemit-x60.
Note that the FIXME about illegal vectors seems to have been fixed in
#100436
Commit: 56dcfbef453d6cc390fc7a734db417e047616526
https://github.com/llvm/llvm-project/commit/56dcfbef453d6cc390fc7a734db417e047616526
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Log Message:
-----------
[RISCV] Remove duplicate vector conversion pseudos. (#114287)
These pseudos used to be handled by CustomInserter to insert the
rounding
mode change for vector ceil, floor, etc. At some point they were changed
to use the InsertReadWriteCSR pass instead of the custom inserter. I
believe
that makes them redundant with the pseudos used by the RVV intrinsics
with rounding mode operand.
Commit: 5d35747f6de9295400327744b389f303e3e2b13d
https://github.com/llvm/llvm-project/commit/5d35747f6de9295400327744b389f303e3e2b13d
Author: Michael Jones <michaelrj at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/test/src/sys/statvfs/linux/CMakeLists.txt
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
Log Message:
-----------
[libc] Refactor statvfs tests (#114147)
The previous statvfs tests had several issues, this patch updates them
to meet current standards.
Commit: 50c44478fe3f680374edf1363d2a3617b8ff2a0b
https://github.com/llvm/llvm-project/commit/50c44478fe3f680374edf1363d2a3617b8ff2a0b
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/src/string/string_utils.h
M libc/test/UnitTest/LibcTest.h
M libc/test/src/string/StrchrTest.h
Log Message:
-----------
[libc] fix behavior of strrchr(x, '\0') (#112620)
`strrchr("foo", '\0')` is defined to point to the end of `foo`, rather
than returning NULL. This wasn't caught by tests, since llvm-libc's
`ASSERT_STREQ(nullptr, "");` is not an assertion error.
While I'm here, refactor the test slightly to check for NULL more
specifically. I considered adding fancier `ASSERT`s (and changing the
semantics of `ASSERT_STREQ`), but opted for a more local fix by fair
dice roll.
Commit: 36d56925706a32a065ec50d5a6b418e1f29a27b3
https://github.com/llvm/llvm-project/commit/36d56925706a32a065ec50d5a6b418e1f29a27b3
Author: gulfemsavrun <gulfem at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
Log Message:
-----------
Revert "[TLI] Add support for hypot libcall." (#114312)
Reverts llvm/llvm-project#113724
Commit: 1cecc58c3f15e3d0fe97b7f764d498e4005557e0
https://github.com/llvm/llvm-project/commit/1cecc58c3f15e3d0fe97b7f764d498e4005557e0
Author: Artem Belevich <tra at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
A llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/NVPTX/isspacep.ll
Log Message:
-----------
[NVPTX] instcombine known pointer AS checks. (#112964)
The change improves the code in general and, as a side effect, avoids crashing
on an impossible address space casts guarded by `__isGlobal/__isShared`, which
partially fixes https://github.com/llvm/llvm-project/issues/112760
It's still possible to trigger the issue by using explicit AS casts w/o
AS checks, but LLVM should no longer crash on valid code.
Commit: d043670d66ce7958aec7837ee572f3dc8948f11a
https://github.com/llvm/llvm-project/commit/d043670d66ce7958aec7837ee572f3dc8948f11a
Author: Matthias Springer <me at m-sp.org>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp
Log Message:
-----------
[mlir][func] Replace `ValueDecomposer` with target materialization (#114192)
The `ValueDecomposer` in `DecomposeCallGraphTypes` was a workaround
around missing 1:N support in the dialect conversion. Since #113032, the
dialect conversion infrastructure supports 1:N type conversions and 1:N
target materializations. The `ValueDecomposer` class is no longer
needed. (However, target materializations must still be inserted
manually, until we fully merge the 1:1 and 1:N drivers.)
Note for LLVM integration: Register 1:N target materializations on the
type converter instead of "decompose value conversions" on the
`ValueDecomposer`.
Commit: 04e876e6c6eee5332f5fff30c8778abe82ebf52f
https://github.com/llvm/llvm-project/commit/04e876e6c6eee5332f5fff30c8778abe82ebf52f
Author: Artem Belevich <tra at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
R llvm/include/llvm/Support/NVPTXAddrSpace.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
R llvm/test/Transforms/InstCombine/NVPTX/isspacep.ll
Log Message:
-----------
Revert "[NVPTX] instcombine known pointer AS checks." (#114319)
Reverts llvm/llvm-project#112964
Crashes MLIR: https://lab.llvm.org/buildbot/#/builders/138/builds/5665
Commit: 67c485798a16c4c656ff7a8a38cc98fe46d25154
https://github.com/llvm/llvm-project/commit/67c485798a16c4c656ff7a8a38cc98fe46d25154
Author: Caio Oliveira <caio.oliveira at intel.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
[mlir][spirv] Ignore extra comma for category_args in gen_spirv_dialect.py (#111776)
In the code being parsed, the comma separates following traits from the
category args. If there's no category args, it is still present.
Commit: 6e75eec866133620dcba956bc7d6dbc554642249
https://github.com/llvm/llvm-project/commit/6e75eec866133620dcba956bc7d6dbc554642249
Author: Caio Oliveira <caio.oliveira at intel.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
[mlir][spirv] Remove code for de-duplicating symbols in SPIR-V grammar (#111778)
SPIR-V grammar was updated in upstream to have an "aliases" field
instead of duplicating symbols with same values. See
https://github.com/KhronosGroup/SPIRV-Headers/pull/447 for details.
Commit: 3a782ef97de771af9fd565e0043d49bdd0f2c850
https://github.com/llvm/llvm-project/commit/3a782ef97de771af9fd565e0043d49bdd0f2c850
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M lldb/docs/index.rst
Log Message:
-----------
[lldb] Add a link to LLDB's Discord channel on the website (#114289)
Looking at #114276, I realized we have a link to Discourse on the
website, but not Discord. I think it would be helpful to have that link
there for real-time community discussion.
Commit: 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5
https://github.com/llvm/llvm-project/commit/1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5
Author: Luke Lau <luke at igalia.com>
Date: 2024-10-31 (Thu, 31 Oct 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
Log Message:
-----------
[RISCV] Remove redundant +zfh from +zvfh[min] tests. NFC
In the vast majority of f16 tests we don't end up emitting any scalar
code that needs +zfh, so remove it.
Commit: 6ffefbbc2593d82117924c5c18d2a4ed7689ea3f
https://github.com/llvm/llvm-project/commit/6ffefbbc2593d82117924c5c18d2a4ed7689ea3f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/docs/ClangLinkerWrapper.rst
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Log Message:
-----------
[LinkerWrapper] Remove handling of special bitcode flags (#114298)
Summary:
These flags were used in the very early days while we were trying to
port stuff. Now that we just pass bitcode to the device link job it
can be easily replaced by `-Xoffload-linker foo.bc`.
Commit: a39fb30a4928eef0619bcfaa709645309dff32f9
https://github.com/llvm/llvm-project/commit/a39fb30a4928eef0619bcfaa709645309dff32f9
Author: lntue <lntue at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M libc/test/UnitTest/LibcTest.h
Log Message:
-----------
[libc] Fix usage of std::nullptr_t in LibcTest.h. (#114321)
Commit: 847f4ef21b4a953bb6dd6477791e8d95b6db2509
https://github.com/llvm/llvm-project/commit/847f4ef21b4a953bb6dd6477791e8d95b6db2509
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Use getAllOnesConstant instead of getConstant(-1). NFC (#114299)
Commit: c1858cdd1dafd29f56cf6274cc03c1567d249daa
https://github.com/llvm/llvm-project/commit/c1858cdd1dafd29f56cf6274cc03c1567d249daa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[clang-link-wrapper] Fix a warning
This patch fixes:
clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp:221:23:
error: unused function 'getInputBitcodeLibrary'
[-Werror,-Wunused-function]
Commit: 51628faa0122d61b7725ec869fa5c0be1d739edd
https://github.com/llvm/llvm-project/commit/51628faa0122d61b7725ec869fa5c0be1d739edd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Sink hasPostISelHook = 1 for vector pseudos into the subclasses that set HasRoundModeOp. NFC (#114294)
Commit: b01e2a8b5620466c3b80cc6f049efbc90b9d103a
https://github.com/llvm/llvm-project/commit/b01e2a8b5620466c3b80cc6f049efbc90b9d103a
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
A llvm/test/Transforms/LowerTypeTests/drop_type_test.ll
M llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll
Log Message:
-----------
[llvm] Allow always dropping all llvm.type.test sequences
Currently, the `DropTypeTests` parameter only fully works with phi nodes
and llvm.assume instructions. However, we'd like CFI to work in
conjunction with FatLTO, in so far as the bitcode section should be able
to contain the CFI instrumentation, while any incompatible bits are
dropped when compiling the object code.
To do that, we need to drop the llvm.type.test instructions everywhere,
and not just their uses in phi nodes. This patch updates the
LowerTypeTest pass so that uses are removed, and replaced with `true` in
all cases, and not just in phi nodes.
Addressing this will allow us to fix #112053 by modifying the FatLTO
pipeline.
Reviewers: pcc, nikic
Reviewed By: pcc
Pull Request: https://github.com/llvm/llvm-project/pull/112787
Commit: 6b0ae129a6fbd2168d1b0bc8a88088e6ccf274dc
https://github.com/llvm/llvm-project/commit/6b0ae129a6fbd2168d1b0bc8a88088e6ccf274dc
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-10-30 (Wed, 30 Oct 2024)
Changed paths:
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/RealtimeSanitizer.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/index.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGObjCGNU.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/Driver/ToolChain.cpp
R clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl
R clang/test/CodeGenHLSL/builtins/StructuredBuffer-annotations.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/cbuf.hlsl
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M flang/include/flang/Runtime/CUDA/memory.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/box.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/embox-char.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/tbaa.fir
M flang/test/Integration/OpenMP/private-global.f90
M flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90
M flang/test/Lower/OpenMP/parallel-reduction-mixed.f90
M flang/test/Lower/allocatable-polymorphic.f90
M libc/include/llvm-libc-macros/linux/signal-macros.h
M libc/include/llvm-libc-types/fexcept_t.h
M libc/include/llvm-libc-types/jmp_buf.h
M libc/src/setjmp/x86_64/longjmp.cpp
M libc/src/setjmp/x86_64/setjmp.cpp
M libc/src/string/string_utils.h
M libc/test/UnitTest/LibcTest.h
M libc/test/src/string/StrchrTest.h
M libc/test/src/string/strlcat_test.cpp
M libc/test/src/string/strlcpy_test.cpp
M libc/test/src/sys/statvfs/linux/CMakeLists.txt
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
M lldb/docs/index.rst
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/BreakpointSite.h
M lldb/include/lldb/Core/Declaration.h
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Target/StopInfo.h
M lldb/include/lldb/Target/ThreadPlanStepInRange.h
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/Core/Declaration.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadPlanStepInRange.cpp
M lldb/source/Target/ThreadPlanStepOverRange.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py
M lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py
M lldb/test/API/functionalities/inline-stepping/calling.cpp
M lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py
M lldb/test/API/python_api/process/io/TestProcessIO.py
M lldb/test/API/python_api/type/TestTypeList.py
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
M llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/icmp-flags.mir
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll
R llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
R llvm/test/CodeGen/MIR/icmp-flags.mir
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
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M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
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M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
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M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vslidedown.ll
M llvm/test/CodeGen/RISCV/rvv/vslideup.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
R llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening-diagnostics.s
A llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop2_err-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
M mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h
M mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/test/Dialect/AMX/legalize-for-llvm.mlir
M mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/bb77205ad832...6b0ae129a6fb
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