[all-commits] [llvm/llvm-project] cba705: [SPIR-V] Fix BB ordering & register lifetime (#111...

Wed Oct 30 06:57:54 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cba70550ccf55c6ad3daa621bb8caf3c4ca6cbd7
      https://github.com/llvm/llvm-project/commit/cba70550ccf55c6ad3daa621bb8caf3c4ca6cbd7
  Author: Nathan Gauër <brioche at google.com>
  Date:   2024-10-30 (Wed, 30 Oct 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
    M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.h
    M llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll
    M llvm/test/CodeGen/SPIRV/OpVariable_order.ll
    M llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll
    M llvm/test/CodeGen/SPIRV/ShaderImage.ll
    M llvm/test/CodeGen/SPIRV/basic_float_types.ll
    M llvm/test/CodeGen/SPIRV/basic_int_types.ll
    M llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll
    M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll
    M llvm/test/CodeGen/SPIRV/literals.ll
    A llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll
    A llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll
    A llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll
    A llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
    M llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll
    M llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll
    M llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll
    M llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll
    M llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll
    M llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll
    A llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll
    M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll
    M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll
    M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll
    A llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll
    M llvm/test/CodeGen/SPIRV/structurizer/return-early.ll

  Log Message:
  -----------
  [SPIR-V] Fix BB ordering & register lifetime (#111026)

The "topological" sorting was behaving incorrectly in some cases: 
the exit of a loop could have a lower rank than a node in the loop.
This causes issues when structurizing some patterns, and also codegen
issues as we could generate BBs in the incorrect order in regard to the
SPIR-V spec.

Fixing this ordering alone broke other parts of the structurizer, which
by luck worked. Had to fix those.

Added more test cases, especially to test basic patterns.

I also needed to tweak/disable some tests for 2 reasons:
 - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores
   are optimized away. Some tests require tweaks to avoid having the
   whole function removed.
 - Mem2Reg will generate variable & load/stores. This generates
   G_BITCAST in several cases. And there is currently something wrong
   we do with G_BITCAST which causes MIR verifier to complain.
   Until this is resolved, I disabled -verify-machineinstrs flag on
   those tests.

---------

Signed-off-by: Nathan Gauër <brioche at google.com>

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