[all-commits] [llvm/llvm-project] 84b7bc: GlobalISel/MachineIRBuilder: Construct DstOp with ...

[Petar Avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84b7bcfcac02ca32c2211655627c352dd99ce296
      https://github.com/llvm/llvm-project/commit/84b7bcfcac02ca32c2211655627c352dd99ce296
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-10-30 (Wed, 30 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
    M llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
    M llvm/unittests/Target/AMDGPU/CMakeLists.txt
    A llvm/unittests/Target/AMDGPU/CSETest.cpp

  Log Message:
  -----------
  GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)

Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used in lowering code for reg-bank-select where
new registers need to have both register bank and LLT.
Add support for new type of DstOp in CSEMIRBuilder.



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