[all-commits] [llvm/llvm-project] 83ae17: [AArch64] Add ComputeNumSignBits for VASHR. (#113957)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 83ae171722bea2722afa4efb0558a6d8b8844305
      https://github.com/llvm/llvm-project/commit/83ae171722bea2722afa4efb0558a6d8b8844305
  Author: David Green <david.green at arm.com>
  Date:   2024-10-29 (Tue, 29 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll
    M llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

  Log Message:
  -----------
  [AArch64] Add ComputeNumSignBits for VASHR. (#113957)

As with a normal ISD::SRA node, they take the number of sign bits of the
incoming value and increase it by the shifted amount.



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