[all-commits] [llvm/llvm-project] c3260c: [IR] Add `llvm.sincos` intrinsic (#109825)

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3260c65e86ac363aa3a39f084db66a8a1d1af7d
      https://github.com/llvm/llvm-project/commit/c3260c65e86ac363aa3a39f084db66a8a1d1af7d
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-10-29 (Tue, 29 Oct 2024)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sincos.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/CodeGen/AArch64/llvm.frexp.ll
    A llvm/test/CodeGen/AArch64/llvm.sincos-fmf.ll
    A llvm/test/CodeGen/AArch64/llvm.sincos.ll
    A llvm/test/CodeGen/ARM/llvm.sincos.ll

  Log Message:
  -----------
  [IR] Add `llvm.sincos` intrinsic (#109825)

This adds the `llvm.sincos` intrinsic, legalization, and lowering.

The `llvm.sincos` intrinsic takes a floating-point value and returns
both the sine and cosine (as a struct).

```
declare { float, float }          @llvm.sincos.f32(float  %Val)
declare { double, double }        @llvm.sincos.f64(double %Val)
declare { x86_fp80, x86_fp80 }    @llvm.sincos.f80(x86_fp80  %Val)
declare { fp128, fp128 }          @llvm.sincos.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 }  @llvm.sincos.ppcf128(ppc_fp128  %Val)
declare { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float>  %Val)
```

The lowering is built on top of the existing FSINCOS ISD node, with
additional type legalization to allow for f16, f128, and vector values.



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