[all-commits] [llvm/llvm-project] 8d38fb: [LLVM][AArch64] Add assembly/disassembly for SVE I...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d38fbf2f027c72332c8ba03ff0ff0f83b4dcf02
      https://github.com/llvm/llvm-project/commit/8d38fbf2f027c72332c8ba03ff0ff0f83b4dcf02
  Author: CarolineConcatto <caroline.concatto at arm.com>
  Date:   2024-10-29 (Tue, 29 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/MC/AArch64/SVE2p2/unary_arithmetic_predicated_z-diagnotics.s
    A llvm/test/MC/AArch64/SVE2p2/unary_arithmetic_predicated_z.s

  Log Message:
  -----------
  [LLVM][AArch64] Add assembly/disassembly for SVE Integer Unary Arithm… (#113670)

…etic Predicated instructions

This patch adds the following instructions:

SVE bitwise unary operations (predicated)
CLS, CLZ, CNT, CNOT, FABS, FNEG, NOT

SVE integer unary operations (predicated)
SXT{B,H,W}, UXT{B,H,W}, ABS ,NEG

SVE2 integer unary operations (predicated)
URECPE, URSQRTE, SQABS, SQNEG

According to https://developer.arm.com/documentation/ddi0602

Co-authored-by: Spencer Abson Spencer.Abson at arm.com



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