[all-commits] [llvm/llvm-project] 0cbccb: [RISCV] Remove support for pre-RA vsetvli insertio...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cbccb13d6757b0ea7f2a7f29bb598e1935bcf37
      https://github.com/llvm/llvm-project/commit/0cbccb13d6757b0ea7f2a7f29bb598e1935bcf37
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-10-28 (Mon, 28 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/rvv/remat.ll

  Log Message:
  -----------
  [RISCV] Remove support for pre-RA vsetvli insertion (#110796)

Now that LLVM 19.1.0 has been out for a while with post-vector-RA
vsetvli insertion enabled by default, this proposes to remove the flag
that restores the old pre-RA behaviour so we only have one configuration
going forward.

That flag was mainly meant as a fallback in case users ran into issues,
but I haven't seen anything reported so far.



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